Firestorm: STLXRH measurements

Code:

  stlxrh w0, w1, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 50.673

Integer unit issues: 0.000

Load/store unit issues: 50.673

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	1f	22	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	64	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	38001	285	1	1	1	1	0	1998	14	0	37986	0	7267	50672	50673	87816	1003640	1	1000	49	34921	38001	38001	13147	5937	24402	87816	91440	182880	38001	38001	1001	1	1001	1000	1000	44982	15	44967	9	1	44981	0	2	2012	44966	1000	14	1000	1	0	16589	1	2063	1	1	37917	1000	38002	38002	38002	38002	38002
1004	38001	285	1	0	0	1	0	1998	14	1	37986	0	7267	50673	50672	87816	1003638	1	1000	49	34921	38001	38001	13147	5937	24402	87816	91440	182880	38001	38001	1001	1	1001	1000	1000	44980	14	44967	0	0	44980	0	0	2012	44967	1000	14	1000	1	1	16589	1	2057	1	1	37917	1000	38002	38002	38002	38002	38002
1004	38001	285	1	1	1	1	0	1998	14	0	37986	4	7267	50672	50673	87816	1003635	1	1000	49	34921	38001	38001	13147	5941	24402	87816	91440	182880	38001	38001	1001	1	1001	1000	1000	44982	14	44966	0	1	44981	0	0	2012	44966	1000	14	1000	1	0	16589	1	2063	1	1	37917	1000	38002	38002	38002	38002	38002
1004	38001	284	1	1	1	1	0	1998	14	0	37986	0	7267	50672	50673	87816	1003638	1	1000	49	34921	38001	38001	13148	5937	24402	87816	91440	182880	38001	38001	1001	1	1001	1000	1000	44980	14	44967	0	1	44981	0	1	2012	44967	1000	14	1000	1	0	16589	1	2057	1	1	37917	1000	38002	38002	38002	38002	38002
1004	38001	285	1	1	1	1	0	1998	14	0	37986	4	7267	50673	50672	87816	1003635	1	1000	49	34921	38001	38001	13147	5937	24402	87816	91440	182880	38001	38001	1001	1	1001	1000	1000	44981	14	44967	0	0	44980	0	1	2012	44967	1000	14	1000	1	1	16589	1	2059	1	1	37917	1000	38002	38002	38002	38002	38002
1004	38001	285	1	1	1	1	0	2010	14	0	37986	1	7267	50673	50672	87815	1003635	1	1000	49	34921	38001	38001	13148	5937	24403	87816	91440	182880	38001	38001	1001	1	1001	1000	1000	44981	14	44966	0	0	44981	0	1	2012	44966	1000	14	1000	1	1	16589	1	2055	1	1	37917	1000	38002	38002	38002	38002	38002
1004	38001	285	1	0	1	0	0	1998	14	0	37986	0	7267	50672	50673	87815	1003635	1	1000	49	34921	38001	38001	13147	5941	24402	87816	91440	182880	38001	38001	1001	1	1001	1000	1000	44982	14	44967	0	0	44980	0	0	2012	44966	1000	14	1000	1	0	16589	1	2063	1	1	37917	1000	38002	38002	38002	38002	38002
1004	38001	284	1	1	1	1	0	1998	14	0	37986	0	7267	50675	50676	87816	1003636	1	1000	49	34921	38001	38001	13147	5943	24402	87816	91440	182880	38001	38001	1001	1	1001	1000	1000	44981	15	44966	0	1	44981	0	1	2012	44967	1000	14	1000	1	1	16589	1	2063	1	1	37917	1000	38002	38002	38002	38002	38002
1004	38001	285	1	0	0	1	0	1998	14	0	37986	0	7267	50673	50672	87816	1003641	1	1000	49	34921	38001	38001	13148	5938	24402	87816	91440	182880	38001	38001	1001	1	1001	1000	1000	44981	16	44967	0	1	44981	0	1	2013	44966	1000	14	1000	1	1	16589	1	2063	1	1	37940	1000	38002	38002	38002	38002	38002
1004	38001	285	1	0	1	1	0	1998	14	0	37986	0	7267	50676	50676	87816	1003636	1	1000	49	34921	38001	38001	13147	5940	24402	87816	91440	182880	38001	38001	1001	1	1001	1000	1000	44982	15	44966	0	0	44980	0	0	2012	44966	1000	14	1000	1	0	16589	1	2063	1	1	37917	1000	38002	38002	38002	38002	38002

Test 2: throughput

Code:

  stlxrh w0, w1, [x6]
  add x6, x6, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 38.9135

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	23	29	3a	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20206	389161	2916	0	0	0	0	0	0	0	0	20004	0	136	2	0	0	108	0	389112	52	0	69279	558500	298924	259576	788774	697486	12744602	11717709	1	10000	0	49	386169	0	389130	389127	83534	59088	181304	1486286	794473	778667	794500	1557200	389250	389252	10001	1	20201	100	99	100	10000	10100	10000	100	229699	0	32114	12	9	111	229648	0	1	33	22	19998	229758	10000	0	1632	0	0	0	209452	1	55	11296	53	59	389190	291423	10000	10100	389128	389251	389128	389251	389253
20204	389127	2915	0	0	0	0	0	1	0	0	20003	0	89	2	0	0	90	0	389237	54	0	69402	558500	298924	259576	788800	697486	12745024	11717662	1	10000	0	49	386172	0	389252	389126	83528	59206	181294	1486256	794500	778665	794473	1557208	389250	389127	10001	1	20201	100	99	100	10000	10100	10000	100	229754	0	35796	16	0	131	229653	5	0	100	0	19998	229648	10000	0	1344	0	0	0	209452	1	55	10975	53	59	389067	291463	10000	10100	389253	389251	389253	389253	389128
20204	389252	2915	0	0	0	0	0	1	0	0	19998	0	96	2	0	0	102	0	389112	49	0	69402	558500	298924	259576	788772	697486	12744578	11717702	1	10000	0	49	386047	0	389127	389252	83528	59083	181302	1486283	794473	778606	794499	1557330	389250	389260	10001	1	20201	100	99	100	10000	10100	10000	100	229784	0	38004	11	0	136	229648	0	0	136	120	19998	229781	10000	0	1216	0	0	0	209452	1	55	10978	53	59	389190	291423	10000	10100	389253	389151	389251	389140	389129
20204	389126	2915	0	0	0	0	0	0	0	0	20033	0	96	0	0	0	102	0	389237	45	0	69404	558500	298924	259576	788772	697486	12744688	11716973	1	10000	14	49	386047	0	389127	389252	83528	59212	181253	1486259	794499	778665	794471	1557326	389249	389126	10001	1	20201	100	99	100	10000	10100	10000	100	229773	0	33587	12	0	127	229648	1	0	127	110	19998	229776	10000	0	1472	0	0	0	209451	1	55	10978	53	59	389067	291423	10000	10100	389253	389128	389253	389253	389251
20204	389250	2915	0	0	0	0	0	0	0	0	19998	0	120	1	0	0	104	0	389237	43	0	69279	558500	298924	259576	788772	697486	12744605	11717718	1	10000	0	98	386209	0	389126	389255	83527	59201	181170	1486282	794497	778665	794497	1557200	389128	389252	10001	1	20201	100	99	100	10000	10100	10000	100	229786	0	38004	20	0	142	229662	6	0	64	0	19998	229648	10000	0	1504	0	0	0	209452	1	55	10976	53	59	389190	291423	10000	10100	389253	389250	389129	389253	389128
20204	389127	2914	0	0	0	0	0	0	0	0	20010	0	127	2	0	0	94	0	389112	36	0	69279	558500	298924	259576	788797	697486	12744703	11717639	1	10000	0	49	386170	0	389252	389128	83531	59201	181173	1486260	794471	778604	794470	1557210	389127	389250	10001	1	20201	100	99	100	10000	10100	10000	100	229652	0	28438	2	0	86	229648	2	0	66	18	20001	229752	10000	0	1440	0	0	0	209467	1	56	10978	53	59	389190	291423	10000	10100	389251	389251	389129	389128	389231
20205	389258	2916	0	0	0	0	0	0	0	0	20027	0	42	0	0	0	50	0	389238	7	0	69278	558500	298924	259576	788773	697486	12744611	11717718	1	10000	0	49	386172	0	389250	389126	83464	59206	181171	1486258	794496	778605	794499	1557326	389126	389128	10001	1	20201	100	99	100	10000	10100	10000	100	229790	4	29178	8	0	8	229635	12	2	72	66	20004	229727	10000	0	1152	0	0	0	209454	1	55	10978	53	59	389070	291426	10000	10100	389128	389251	390230	389129	389250
20204	389127	2915	0	0	0	0	0	0	0	0	19998	0	0	0	0	0	99	0	389111	36	0	69402	558500	298924	259576	788797	697486	12744611	11716921	1	10000	14	49	386172	0	389127	389126	83468	59079	181293	1486310	794473	778600	794499	1557200	389252	389127	10001	1	20201	100	99	100	10000	10100	10000	100	229764	0	34325	11	0	116	229648	2	0	116	106	20204	229768	10000	0	1312	0	0	0	209451	1	55	10978	53	59	389190	291423	10000	10100	389128	389250	389128	389250	389253
20204	389127	2916	0	0	0	0	0	0	0	0	20004	0	130	1	0	0	70	0	389237	0	0	69278	558500	298924	259576	788773	697486	12746325	11723681	1	10000	0	49	386048	0	389252	389252	83528	59079	181293	1486258	794470	778664	794496	1557336	389250	389250	10002	1	20201	100	99	100	10000	10100	10000	100	229768	0	34323	3	0	85	229648	1	0	112	50	19998	229648	10000	0	1376	0	0	0	209452	1	55	10975	53	36	389067	291423	10000	10100	389251	389250	389128	389253	389128
20204	389128	2916	0	0	0	0	0	0	0	0	20004	0	128	1	0	0	113	0	389234	61	0	69280	558500	298924	259576	788770	697486	12744605	11717689	1	10000	0	49	386169	0	389252	389127	83464	59078	181323	1486283	794474	778665	794497	1557334	389126	389127	10001	1	20201	100	99	100	10000	10100	10000	100	229758	0	29541	8	0	111	229648	3	0	111	104	20001	229759	10000	0	1648	0	0	0	209452	1	55	10978	53	59	389192	291426	10000	10100	389250	389250	389253	389253	389128

1000 unrolls and 10 iterations

Result (median cycles for code): 38.9947

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	23	29	3a	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20026	389964	2921	1	1	1	0	0	0	19998	0	0	0	0	0	2	0	389932	0	0	70099	550200	290544	259656	760246	697566	12689354	11764738	1	10000	0	98	386856	0	389936	389947	70811	59892	188851	1457807	760812	759162	760814	1518318	389936	389936	10001	1	20021	10	9	10	10000	10010	10000	10	229756	0	34337	0	0	75	229728	2	0	29	12	20004	229852	10000	0	1472	0	0	0	200994	0	0	42	10977	1	0	40	42	389896	289801	0	9	10000	10010	389957	389945	389945	389957	389956
20024	389955	2921	2	0	0	2	0	0	19998	7	0	2	0	0	11	0	389940	0	4	70099	550216	290552	259664	760254	697574	12689810	11765061	0	10000	0	49	386875	0	389944	389944	70816	59906	188856	1457826	760820	759170	760817	1518338	389956	44	10001	1	20021	10	9	10	10000	10010	10000	10	229798	9	37288	18	0	0	229743	0	2	0	0	20011	229736	10000	7	1600	1	0	2	200994	3	0	42	10954	0	0	34	43	389887	289793	0	0	10000	10010	389948	389941	389937	389948	389948
20024	389937	2921	1	1	1	1	0	0	20010	0	75	0	0	0	3	0	389921	6	0	70088	550200	290544	259656	760241	697566	12689388	11764672	0	10000	0	49	386857	0	389936	389947	70811	59901	188867	1457928	760812	759163	760809	1518334	389936	389947	10001	1	20021	10	9	10	10000	10010	10000	10	229746	0	29921	2	0	1	229728	0	1	0	8	20013	229842	10000	0	1440	0	2	0	200996	0	0	42	10974	0	0	40	42	389888	289795	0	0	10000	10010	389938	389937	389948	389948	389949
20024	389948	2921	1	1	1	1	0	0	19998	0	0	0	0	0	52	0	389932	47	0	70100	550200	290544	259656	760238	697566	12689392	11764700	0	10000	0	49	383827	0	389948	389936	70809	59900	188847	1457808	760812	759164	760816	1518336	389948	389947	10001	1	20021	10	9	10	10000	10010	10000	10	229729	2	31394	0	0	0	229728	2	1	0	0	19998	229728	10000	0	1152	0	1	0	200994	0	0	42	10972	0	0	40	42	389876	289793	0	0	10000	10010	389949	389938	389949	389950	389949
20024	389936	2921	1	1	1	1	0	0	19998	0	32	0	0	0	44	0	389922	10	0	70099	550200	290544	259656	760242	697566	12689360	11764769	0	10000	0	49	386856	0	389938	389947	70816	59888	188861	1457810	760810	759160	760816	1518324	389947	389947	10001	1	20021	10	9	10	10000	10010	10000	10	229793	0	20356	0	0	8	229728	0	0	0	0	19998	229728	10000	0	1856	0	1	0	200994	0	0	42	10972	0	0	34	42	389876	289793	0	0	10000	10010	389937	389950	389953	389948	389982
20024	389947	2921	1	1	0	1	0	0	19998	0	34	0	0	0	17	0	389921	10	0	70090	550200	290544	259676	760242	697569	12689356	11764808	0	10000	0	49	386867	0	389936	389947	70816	59906	188856	1457805	760811	759166	760810	1518328	389947	389948	10001	1	20021	10	9	10	10000	10010	10000	10	229864	0	36913	8	0	141	229728	1	1	140	134	20001	229870	10000	0	1680	0	2	0	200994	0	0	43	10976	0	0	40	42	389888	289793	0	0	10000	10010	389940	389940	389949	389937	389948
20024	389938	2921	1	1	1	1	0	0	20016	0	82	1	0	0	41	0	389933	29	0	70099	550200	290544	259656	760240	697566	12689383	11764773	0	10000	0	49	386867	0	389936	389936	70811	59898	188903	1457842	760814	759167	760818	1518336	389936	389936	10001	1	20021	10	9	10	10000	10010	10000	10	229728	1	29922	0	0	2	229728	1	1	91	74	20001	229816	10000	0	1376	0	2	0	200994	0	0	36	10972	0	0	40	42	389906	289793	0	0	10000	10010	389939	389949	389937	389948	389937
20024	389947	2921	1	1	1	0	0	0	19998	0	105	0	0	0	33	60	389923	7	0	70088	550200	290544	259656	760245	697568	12689369	11764711	0	10000	0	49	386867	0	389948	389938	70816	59912	188862	1457811	760808	759167	760814	1518334	389948	389979	10001	1	20021	10	9	10	10000	10010	10000	10	229819	0	26977	0	0	4	229728	0	1	0	0	19998	229730	10000	0	1152	0	1	0	200994	0	0	42	10978	0	1	34	36	389887	289793	0	9	10000	10010	389949	389948	389937	389949	389939
20024	389936	2921	1	1	0	1	0	0	19998	0	126	1	0	0	59	0	389921	51	0	70088	550200	290544	259656	760241	697566	12689387	11764761	0	10000	0	49	386856	0	389948	389947	70811	59889	188899	1457810	760822	759205	760814	1518328	389938	389948	10001	1	20021	10	9	10	10000	10010	10000	10	229804	0	21091	7	0	79	229728	1	0	38	14	19998	229795	10000	0	1264	0	1	0	200994	0	0	36	10976	0	0	40	42	389888	289793	0	0	10000	10010	389937	389948	389937	389937	389937
20024	389947	2920	1	0	1	1	0	0	20037	0	75	0	0	0	0	0	389994	12	0	70119	550216	290592	259667	760348	697606	12689732	11764772	1	10000	0	49	386887	0	389947	389936	70811	59900	188857	1457810	760820	759171	760897	1518332	389948	389947	10001	1	20021	10	9	10	10000	10010	10000	10	229731	1	25139	7	0	94	229746	9	0	70	0	19998	229728	10000	0	1472	0	1	0	200994	0	0	42	10978	0	0	40	42	389887	289793	9	9	10000	10010	389937	389937	389939	389949	389937

Test 3: throughput

Code:

  stlxrh w0, w1, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 38.0108

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	22	23	24	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10205	380118	2847	1	0	0	20007	1	0	0	0	380167	0	70276	529272	10697	518575	10697	915715	54384	10461754	0	10000	0	49	377030	0	380368	380110	130429	59951	248975	926412	19100	938418	19106	1876836	380110	380110	10001	1	10201	100	99	100	10000	100	10000	100	458868	2	458866	0	0	458866	2	0	19998	458866	10000	0	10000	0	0	10	172638	1	132	11081	131	131	380043	1197	10000	100	380354	380111	380111	380111	380111
10204	380110	2847	0	0	4	20016	0	0	0	183	380095	0	70276	529272	10697	518575	10697	915715	54384	10461754	1	10000	0	49	377030	0	380110	380112	130429	59954	248974	926414	19100	938418	19100	1876836	380110	380110	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	0	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172639	1	131	11081	131	131	380043	1197	10000	100	380111	380111	380111	380111	380112
10204	380343	2847	0	0	0	19998	0	0	0	183	380097	0	70276	529272	10697	518575	10697	915715	55189	10461754	0	10000	0	49	377032	0	380110	380110	130429	59954	248978	926412	19100	938418	19100	1876836	380110	380112	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	0	0	458866	0	0	20009	458866	10000	0	10000	0	0	10	172638	1	131	11080	131	131	380043	1197	10000	100	380111	380111	380111	380111	380112
10204	380110	2848	0	0	0	19998	0	0	0	184	380095	0	70272	539431	10697	518575	10697	915687	54394	10463992	1	10000	0	49	377032	0	380110	380110	130429	59964	248978	926412	19100	938418	19100	1876836	380110	380110	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	54	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172641	1	130	11081	131	131	380043	1197	10000	100	380111	380174	380111	380111	380111
10204	380110	2847	0	0	0	19998	1	0	0	183	380096	0	70278	529272	10697	518581	10697	915715	54384	10461759	1	10000	0	49	377031	0	380124	380142	130429	59951	248982	926412	19100	938418	19100	1876836	380110	380110	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	0	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172653	1	131	11081	42	131	380044	1197	10000	100	380113	380111	380114	380111	380113
10205	380124	2847	0	0	0	19998	0	0	0	182	380095	0	70276	529272	10697	518575	10697	915715	54384	10461754	0	10000	0	49	377030	0	380111	380110	130429	59951	248974	926412	19100	938418	19100	1876836	380110	380110	10002	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	9	0	458866	4	0	19998	458866	10000	0	10000	0	0	10	172641	1	130	11070	131	131	380043	1197	10000	100	380111	380111	380111	380112	380113
10204	380110	2847	0	0	0	19998	0	0	0	33	380095	0	70276	529272	10697	518575	10697	915715	54384	10461805	1	10000	0	49	373973	0	380110	380110	130429	59961	248974	926413	19100	938418	19100	1876836	380110	380110	10001	1	10201	100	99	100	10000	100	10000	100	458874	0	458866	0	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172641	1	130	11068	131	131	380043	1197	10000	100	380111	380111	380111	380111	380111
10204	380112	2847	0	0	0	20004	0	0	0	183	380095	0	70276	529272	10697	518575	10697	915715	54384	10461754	1	10000	0	49	377030	0	380110	380110	130429	59951	248974	926414	19100	938418	19100	1876836	380110	380110	10001	1	10201	100	99	100	10000	100	10000	100	458868	0	458866	0	0	458866	0	2	19998	458866	10000	0	10000	0	0	10	172639	1	130	11081	131	131	380044	1197	10000	100	380111	380111	380126	380130	380111
10204	380110	2848	0	0	0	19998	0	0	0	182	380095	0	70276	529272	10697	518575	10697	915715	54384	10461754	0	10000	0	49	377030	0	380110	380110	130429	59961	248982	926414	19100	938511	19100	1876836	380112	380111	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	0	0	458866	0	0	20012	458866	10000	0	10000	0	0	10	172639	1	131	11079	131	131	380043	1197	10000	100	380111	380111	380111	380111	380111
10204	380110	2847	0	0	0	19998	0	0	0	182	380095	0	70276	529272	10697	518575	10697	915715	54384	10461754	1	10000	0	49	377030	0	380110	380110	130429	59961	249201	926463	19100	938418	19100	1876836	380110	380110	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	0	0	458866	0	0	19998	458866	10000	0	10000	0	0	10	172637	1	130	11081	131	131	380043	1197	10000	100	380114	380111	380111	380111	380113

1000 unrolls and 10 iterations

Result (median cycles for code): 38.0011

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10025	380019	2846	0	15	0	15	0	20007	14	1	0	2	380027	0	70269	519732	1067	518666	1067	915807	5424	10470561	1	10000	49	376939	0	380021	380019	138355	59939	249335	917156	1910	954235	1910	1908798	380019	380019	10011	1	10021	10	9	10	10000	10	10000	10	459194	14	458931	0	458975	0	1	20012	458958	10000	14	10000	1	2	0	169769	73	11080	54	71	379952	117	10000	10	380020	380020	380020	380020	380020
10024	380019	2847	1	16	1	16	0	20007	14	0	0	2	380006	4	70267	519730	1068	518664	1067	915806	5424	10470532	1	10000	49	376941	0	380019	380201	138356	59952	249352	916874	1910	953884	1910	1907752	380019	380019	10001	1	10021	10	9	10	10000	10	10000	10	458972	15	458958	0	458971	0	0	20012	458957	10000	14	10000	1	0	0	169680	71	11069	72	75	379952	117	10000	10	380020	380020	380020	380020	380020
10024	380019	2846	1	16	1	16	0	19998	14	0	0	2	380004	2	70267	519737	1067	518663	1067	915807	5424	10470533	1	10000	49	376939	0	380019	380019	138354	59955	249337	916874	1910	953876	1910	1907750	380019	380073	10001	1	10021	10	9	10	10000	10	10000	10	458972	14	458957	0	458972	0	0	20012	458958	10000	14	10000	1	0	0	169680	73	11064	71	75	379952	117	10000	10	380020	380021	380020	380020	380020
10024	380019	2846	1	14	0	16	1	19998	14	0	0	2	380004	0	70267	519729	1067	518666	1067	915807	5424	10470528	1	10000	49	376939	0	380019	380019	138355	59955	249346	916874	1910	953876	1910	1907750	380019	380019	10001	1	10021	10	9	10	10000	10	10000	10	458973	15	458958	1	458971	0	1	20028	458958	10000	14	10000	1	1	0	169678	74	11080	73	72	379952	117	10000	10	380020	380020	380020	380020	380109
10024	380019	2847	1	16	1	15	1	20010	15	1	0	2	380004	0	70267	519730	1067	518667	1067	915807	5424	10470515	1	10000	49	376939	0	380019	380019	138355	59939	249335	916877	1910	953875	1910	1907756	380019	380019	10001	1	10021	10	9	10	10000	10	10000	10	458973	15	458958	0	458970	0	0	20025	458957	10000	14	10000	1	0	0	169678	70	11078	72	71	379952	117	10000	10	380020	380020	380020	380020	380020
10024	380019	2847	1	16	0	16	0	19998	0	0	0	2	379996	0	70267	519732	1067	518665	1067	915805	5424	10470154	1	10000	49	376931	0	380047	380011	138348	59940	249329	916872	1910	953876	1910	1907756	380011	380012	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169676	70	11069	69	69	379944	117	10000	10	380013	380012	380012	380012	380012
10024	380011	2846	0	16	0	14	0	19998	0	0	0	2	379997	0	70267	519732	1067	518665	1067	915805	5424	10470139	1	10000	49	376931	0	380011	380094	138348	59942	249330	916872	1910	953877	1910	1907754	380011	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169684	69	11065	71	71	379945	117	10000	10	380012	380012	380012	380012	380013
10024	380011	2847	0	15	0	15	0	20110	0	1	0	1	379996	0	70267	519732	1067	518665	1067	915805	5424	10470143	1	10000	49	376931	0	380011	380011	138348	59949	249327	916872	1910	953875	1910	1907750	380011	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	458956	0	0	19998	458956	10000	0	10000	0	0	0	169680	71	11080	71	73	379944	117	10000	10	380012	380012	380012	380016	380012
10024	380011	2846	0	16	0	16	0	19998	0	1	0	2	379996	0	70269	519732	1067	518677	1067	915805	5424	10470128	1	10000	49	376931	0	380011	380011	138348	59939	249327	916872	1910	953874	1910	1907752	380011	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458960	0	458956	0	0	20017	458956	10000	0	10000	0	0	0	169678	54	11080	73	69	379960	117	10000	10	380012	380012	380012	380012	380018
10024	380012	2847	0	17	0	16	0	19998	0	1	0	2	379996	0	70267	519732	1067	518665	1067	915805	5424	10470154	1	10000	98	376935	0	380012	380011	138348	59941	249330	916872	1910	953874	1910	1907752	380011	380011	10001	1	10021	10	9	10	10000	10	10000	10	458956	0	458956	0	458956	0	0	19998	458960	10000	0	10000	0	0	0	169678	71	11080	71	71	379944	117	10000	10	380012	380012	380012	380012	380013

STLXRH

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations