Firestorm: AUTIZB measurements

Code:

  autizb x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	71	9	346	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	147	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	1	85	1	2	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	132	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	3	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	1	85	1	1	6805	1000	1000	7030	7030	7030	7030	7030
1004	7029	71	180	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1028	1000	1000	7029	870	1	1	1001	1000	0	3	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	12	103	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	6	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	498	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  autizb x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	617	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808427	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	726	2	79	1	1	69817	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	2	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	621	0	0	0	0	0	0	0	276	59824	25	10203	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10458	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	1	3758	59770	151	10223	10226	10346	1808427	0	49	67811	0	70029	70851	68713	96	69258	10622	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	3	0	0	710	1	79	1	1	69796	10100	0	10100	70069	70307	70187	70071	70030
10204	70029	620	0	0	0	0	0	0	0	547	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	621	0	0	0	0	0	0	1	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	1	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	621	0	0	0	0	12	0	0	89	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	3	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	656	0	0	0	0	0	0	0	5792	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	6	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	617	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	612	0	0	0	0	12	0	0	61	59824	46	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	7	68674	10200	10200	10200	70069	912	2	1	10201	100	99	10100	0	0	0	0	0	3	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70070	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	617	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	1744	1	1	10021	10	9	10010	0	0	0	0	640	3	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	652	0	0	0	0	0	804	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	9	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	621	0	0	0	27	0	82	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	1	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	626	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	7358	640	2	95	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	622	1	0	0	12	0	1844	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	15	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	9	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	621	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	623	0	0	0	18	0	89	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	1	0	0	7490	640	2	79	3	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	640	2	79	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030

Test 3: throughput

Count: 8

Code:

  autizb x0
  autizb x1
  autizb x2
  autizb x3
  autizb x4
  autizb x5
  autizb x6
  autizb x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80041	643	0	0	0	0	15	0	56	110	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	1	0	0	5110	3	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	744	0	1	0	0	0	0	77	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	1	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	1562	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	1	0	0	5110	2	17	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	605	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	5110	2	25	2	0	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	1	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	40	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ab	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80040	696	0	0	0	0	0	264	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	13	25	11	5	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	5	25	6	11	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	746	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	4	25	5	12	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	750	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80072	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	5	25	4	10	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	701	0	0	0	0	0	1434	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	9	25	9	5	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	0	0	0	5020	3	25	4	12	80024	80010	80010	80081	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	0	0	0	5020	6	25	10	4	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	12	25	12	5	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	700	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	5	33	10	4	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	57	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	2	0	5020	5	25	6	11	80024	80010	80010	80036	80036	80036	80036	80036

AUTIZB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations