Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ROR (register, 32-bit)

Test 1: uops

Code:

  ror w0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004103570061862251000100010001691611035103572838681000100020001035411110011000000073341229371000100010361036103610361036
1004103580061862251000100010001691611035103572838681000100020001035411110011000000073241229371000100010361036103610361036
1004103580061862251000100010001691611035103572838681000100020001035411110011000000073241229371000100010361036103610361036
1004103580061862251000100010001691611035103572838681000100020001035411110011000000073241229371000100010361036103610361036
1004103580061862251000100010001691611035103572838681000100020001035411110011000000073241229371000100010361036103610361036
10041035800618622510001000100016916110351035728386810001000200010354111100110002000073241229371000100010361036103610361036
1004103570061862251000100010001691611035103572838681000100020001035411110011000000073241229371000100010361036103610361036
1004103570061862251000100010001691611035103572838681000100020001035411110011000000073241229371000100010361036103610361036
1004103580061862251000100010001691611035103572838681000100020001035411110011000000073241229371000100010361036103610361036
10041035706661862251000100010001691611035103572838681000100020001035411110011000000073241229371000100010361036103610361036

Test 2: Latency 1->2

Code:

  ror w0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357506198772510100101001011787686496955100351003586077873510117102402028010035411110201100991001010010011172001600996510000101001003610036100361003610036
10204100357506198772510100101001011787686496955100351003586077873410117102402028010035411110201100991001010010000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575061987725101001010010100886644969551003510035858038722101001020020200100354111102011009910010100100000710137111000810000101001003610036100361003610036
10204100357506198772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
1020410035753156198772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664496955100351003585803872210100102002020010035411110201100991001010010000071013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024100357506198632510010100101001088784149695501003510035860203874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
10024100357506198632510010100101001088784149695501003510035860203874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
10024100357506198632510010100101001088784149695501003510035860203874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
10024100357506198632510010100101001088784149695501003510035860203874010010100202002010035411110021109101001010000064024122994010000100101003610129100361003610036
10024100357506198632510010100101001088784149695501003510035860203877110010100202002010035411110021109101001010000064034122994010000100101003610036100361003610036
10024100357506198632510010100101001088784149695501003510035860203874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
10024100357506198632510010100101001088784149695501003510035860203874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
10024100357506198632510010100101001088784149695501003510035860203874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
10024100357506198632510010100101001088784149695501003510035860203874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036
10024100357506198632510010100101001088784149695501003510035860203874010010100202002010035411110021109101001010000064024122994010000100101003610036100361003610036

Test 3: Latency 1->3

Code:

  ror w0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03181e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357500103987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010071013711994110000101001003610036100361003610036
1020410035750061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010071013711994110000101001003610036100361003610036
1020410035750061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010071013711994110000101001003610036100361003610036
1020410035750061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010071013711994110000101001003610036100361003610036
1020410035750061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010071013711994110000101001003610036100361003610036
1020410035750082987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010071013711994110000101001003610036100361003610036
1020410035760061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010071013711994110000101001003610036100361003610036
1020410035750084987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010071013711994110000101001003610036100361003610036
1020410035750061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010071013711994110000101001003610036100361003610036
1020410035750061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010071013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575006198632510010100101001088784049695501003510035860238740100101002020020100354111100211091010010100064064155994010000100101003610036100361003610036
1002410035750041698632510010100101001088784049695501003510035860238740100101002020020100354111100211091010010100064054165994010000100101003610036100361003610036
1002410035750661986325100101001010010887840496955010035100358602387401001010020200201003541111002110910100101010064054165994010000100101003610036100361003610036
100241003575006198632510010100101001088784049695501003510035860238740100101002020020100354111100211091010010100064064165994010000100101003610036100361003610036
1002410035750010598632510010100101001088784049695501003510035860238740100101002020020100354111100211091010010103064064156994010000100101003610036100361003610036
100241003575006198632510010100101001088784049695501003510035860238740100101002020020100354111100211091010010101064064156994010000100101003610036100361003610036
1002410035750026398632510010100101001088784049695501003510035860238740100101002020020100354111100211091010010100064064166994010000100101003610036100361003610036
100241003576006198632510010100101001088784049695501003510035860238740100101002020020100354111100211091010010100064044156994010000100101003610036100361003610036
100241003575006198632510010100101001088784049695501003510035860238740100101002020020100354111100211091010010100064064165994010000100101003610036100361003610036
100241003575006198632510010100101001088784049695501003510035860238740100101002020020100354111100211091010010100064064166994010000100101003610036100361003610036

Test 4: throughput

Count: 8

Code:

  ror w0, w8, w9
  ror w1, w8, w9
  ror w2, w8, w9
  ror w3, w8, w9
  ror w4, w8, w9
  ror w5, w8, w9
  ror w6, w8, w9
  ror w7, w8, w9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1673

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802041341710005127801368013680148400710149103101339013390332663336801488026416032813390391180201100991008010010001115119016001338780036801001339113391133911339113391
802041339010102827801368013680148400710049103101339013390332663336801488026416032813390391180201100991008010010001115119016001338780036801001339113391133911339113391
802041339010002827801368013680148400710149103101339013390332663336801488026416032813390391180201100991008010010001115119116001338780036801001339113391133911339113391
802041339010009327801368013680148400710149103101339013390332663336801488026416032813390391180201100991008010010001115119016001338780036801001339113391133911339113391
80204133901001382825801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010000005110119111338380000801001338713387133871338713387
802041338610003525801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010000005110119111338380000801001338713387133871338713387
802041338610003525801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010010005110119111338380000801001338713387133871338713387
8020413386101513525801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010000005110119111338380000801001338713387133871338713387
80204133861002673525801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010000005110119111338380000801001338713387133871338713387
80204133861002073525801008010080100400500049103061338613386332333341801008020016020013386391180201100991008010010000005110119111338380000801001338713387133871338713387

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)d9daddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024133861005625800108001080010400050149102911337113371333033348800108002016002013371391180021109108001010000502021980311336880000800101337213372133721337213372
800241337110035258001080010800104000501491029113371133713330333488001080020160020133713911800211091080010100005020119100111336880000800101337213372133721337213372
800241337110058258001080010800104000501491029113371133713330333488001080020160020133713911800211091080010100005020219120331336880000800101337213372133721337213372
80024133711005825800108001080010400050149102911337113371333033348800108002016002013371391180021109108001010200502021980221336880000800101337213372133721337213372
800241337110035258001080010800104000500491029113371133713330333488001080020160020133713911800211091080010101005020119100111336880000800101337213372133721337213372
80024133711003525800108001080010400050149102911337113371333033348800108002016002013371391180021109108001010000502021980111336880000800101337213372133721337213372
8002413371100744258001080010800104000500491029113371133713330333488001080020160020133713911800211091080010100005020119100321336880000800101337213372133721337213372
80024133711003525800108001080010400050049102911337113371333033348800108002016002013371391180021109108001010000502011981321336880000800101337213372133721337213372
80024133711003525800108001080010400050049102911337113371333033348800108002016002013371391180021109108001010000502021980111336880000800101337213372133721337213372
800241337110035258001080010800104000500491029113371133713330333488001080020160020133713911800211091080010100005020119100211336880000800101337213372133721337213372