Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ORR (register, asr, 64-bit)

Test 1: uops

Code:

  orr x0, x0, x1, asr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10042035150061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035150061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035150061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035150061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203515013261100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035150061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351500611000173525200020001000325701203520351575318421000100020002035421110011000036731671117812000100020362036203620362036
10042035160061100017352520002000100032570120352035157531842100010002000203542111001100006731671117812000100020362036203620362036
100420351500611000173525200020001000325701203520351575318421000100020002035421110011000278731671117812000100020362036203620362036
10042035151061100017352520002000100032570120352035157531842100010002000203542111001100000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  orr x0, x0, x1, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020420035150008210000198032520100201001010018534200491695520035200351842931870010100102002020020035421110201100991001010010000000071000159111979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534200491695520035200351842931870010100102002020020035421110201100991001010010000000071000159111979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534200491695520035200351842931870010100102002020020035421110201100991001010010000000071000159111979120000101002003620036200362003620036
10204200351500017010000198032520100201001010018534200491695520035200351842931870010100102002020020035421110201100991001010010000000071000159111979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534200491695520035200351842931870010100102002020020035421110201100991001010010000000071000159111979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534200491695520035200351842931870010100102002020020035421110201100991001010010000000071000159111979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534210491695520035200351842931870010100102002020020035421110201100991001010010000000071000159111979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534200491695520035200351842931870010100102002020020035421110201100991001010010000000071000159111979120000101002003620036200362003620036
1020420035150106110000198032520100201251010018534210491695520035200351842931870010100102002020020035421110201100991001010010000000071000159111979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534200491695520035200351842931870010100102002020020035421110201100991001010010000000071000159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002420035150000061100001974325200102001010010187041049169552003520035184513187181001010020203462003542111002110910100101000000640263221979220000100102003620036200362003620036
1002420035150000061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000009640263221979220000100102003620036200362003620036
1002420035150000061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000000640263221979220000100102003620036200362003620036
1002420035150000061100001974325200102001010010185310149169552003520035184513187181001010020200202003542111002110910100101000000640263221979220000100102003620036200362003620036
1002420035150000061100001974325200102001010010185310149169552003520035184513187181001010020200202003542111002110910100101002126640263251979220000100102003620036200362003620036
1002420035150000061100001974325200102001010010185310149169552003520035184513187181015810020200202003542111002110910100101000303640263221982620000100102003620036200362003620036
10024200351500000103100001974325200102001010010185310149169552003520035184513187181001010020200202003542111002110910100101000000640263221979220000100102003620036200362003620036
10024200351500000103100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000000640263221979220000100102003620036200362003620036
10024200351500012061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000000640363221986520000100102003620036200362003620036
1002420035150000061100001974325200102001010010185310149169552003520035184513187181001010020200202003542111002110910100101000000640263221979220000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  orr x0, x1, x0, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)0e1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204200351500006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
10204200351500006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
10204200351500006110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
10204200351500006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
10204200351500006110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
10204200351500006110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
10204200351500006110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
10204200351500006110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
10204200351500006110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
10204200351500006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)0309191e3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351500000611000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640363221979220000100102003620036200362003620036
100242007215000001031000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640375221979220000100102003620036200362003620036
100242003515000120611000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
10024200351500000611000019755252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640363221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  orr x0, x8, x9, asr #17
  orr x1, x8, x9, asr #17
  orr x2, x8, x9, asr #17
  orr x3, x8, x9, asr #17
  orr x4, x8, x9, asr #17
  orr x5, x8, x9, asr #17
  orr x6, x8, x9, asr #17
  orr x7, x8, x9, asr #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)191e3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020426767201100100002880031261462716018216018280262161906149236520267322673216651816661802628037616055226732391180201100991008010010000000011151291161126729160082801002673326733267332673326733
8020426732200100100002880031261462816018216018280262161906149236520267322673216651816661802628037616055226788391180201100991008010010000000011151291161126729160082801002673326732267332673326733
8020426732200100100002880031261462816018216018280262161906149236520267322673216651816661802628037616055226732391180201100991008010010000000011151291161126729160082801002673326733267332673326733
8020426732200100100002880031261462816018216018280262161906049236520267322673216651816661802628037616055226732391180201100991008010010000000011151291161126729160082801002673326733267332673326733
8020426732200100100002880031261462816018216018280262164318149236450267252672516615316677801008020016020026725391180201100991008010010000000000051102222226717160000801002672626726267262672626726
8020426725200000000006180000260942516010016010080100164318149236450267252672516615316677801008020016020026725391180201100991008010010000000000051102222226717160000801002672626726267262672626726
8020426725200000000008280000260942516010016010080100164318049236450267252672516615316677801008020016020026725391180201100991008010010000000000051102222226717160000801002672626726267262672626726
8020426725200000000006180000260942516010016010080100164318149236450267252672516615316677801008020016020026725391180201100991008010010000000000051822222226717160000801002672626726267262672626726
8020426725200000000300010380000260942516010016010080100164318149236450267252672516615316677801008020016020026725391180201100991008010010000000000051102222226717160000801002672626726267262672626726
8020426725200000000016180000260942516010016010080100164318049236450267252672516615316677801008020016020026725391180201100991008010010000000000051102222226717160198801002672626726267262672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)031e3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)c2cfd2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)eaeb? int retires (ef)f5f6f7f8fd
800242673520000618000021280251600101600108001016314200492363126711267111662331668580010800201600202671139118002110910800101000005020002220222670416000000800102671226712267122671226712
8002426711200006180000212802516001016001080010163142004923631267112671116623316685800108002016002026770391180021109108001010000050200022202226704160000013800102671226712267122671226712
800242671120000618000021280251600101600108001016314200492363126711267111662331668580010800201600202671139118002110910800101022005020002220222670416000000800102671226712267122671226712
800242671120000618000021280251600101600108001016314200492363126711267111662331668580010800201600202671139118002110910800101000005020002220222670416000000800102671226712267122671226712
800242671120000618000021280251600101600108001016314200492363126711267111662331668580010800201600202671139118002110910800101000005020002220222670416000000800102671226712267122671226712
800242671120000618000021280251600101600108001016314200492363126711267111662331668580010800201600202671139118002110910800101000005020002220222670416000000800102671226712267122671226712
800242671120000618000021280251600101600108001016314200492363126711267111662331668580010800201600202671139118002110910800101000005020002220222670416000000800102671226712267122671226712
800242671120000618000021280251600101600108001016314201492363126711267111662331668580010800201600202671139118002110910800101000045020002220222670416000000800102671226712267122671226712
800242671120000618000021280251600101600108001016314201492363126711267111662331668580010800201600202671139118002110910800101000005020002220222670416000000800102677026712267122671226712
80024267112000017048000021280251600101600108001016314200492363126711267111662331668580010800201600202671139118002110910800101000005020002170222670416000000800102671226712267122671226712