Firestorm: PRFM (register, PLIL2STRM) measurements

Code:

  prfm plil2strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1625	12	33	15	32	2429	1615	885	25	1000	1000	1000	70153	1573	1618	1306	3	1471	1000	1000	1000	1574	1607	1	1	1001	265	2239	2264	3246	0	2431	2241	1000	73	1	16	1	1	1510	1000	1606	1610	1620	1639	1641
1004	1619	12	32	16	30	2440	1599	900	25	1000	1000	1000	70912	1626	1612	1302	3	1446	1000	1000	1000	1591	1597	1	1	1001	262	2267	2260	3249	0	2417	2268	1000	73	1	16	1	1	1550	1000	1596	1614	1578	1610	1580
1004	1618	12	31	17	31	2411	1606	893	25	1000	1000	1000	69008	1593	1599	1349	3	1462	1000	1000	1000	1585	1594	1	1	1001	263	2255	2249	3239	0	2430	2268	1000	73	1	16	1	1	1507	1000	1591	1623	1602	1639	1562
1004	1615	12	32	16	32	2578	1539	899	25	1000	1000	1000	69922	1634	1614	1285	3	1459	1000	1000	1000	1577	1588	1	1	1001	248	2227	2233	3242	0	2452	2245	1000	73	1	16	1	1	1501	1000	1585	1614	1621	1626	1577
1004	1600	12	32	15	32	2431	1617	905	25	1000	1000	1000	69877	1571	1584	1306	3	1490	1000	1000	1000	1604	1575	1	1	1001	256	2262	2239	3240	0	2459	2249	1000	73	1	16	1	1	1477	1000	1587	1619	1598	1621	1616
1004	1614	12	32	17	32	2415	1592	907	25	1000	1000	1000	70112	1595	1615	1303	3	1431	1000	1000	1000	1573	1578	1	1	1001	252	2254	2288	3276	0	2428	2272	1000	73	1	16	1	1	1495	1000	1636	1629	1635	1629	1638
1004	1639	12	32	15	33	2444	1575	858	25	1000	1000	1000	69454	1607	1625	1311	3	1471	1000	1000	1000	1573	1589	1	1	1001	241	2269	2256	3247	0	2441	2249	1000	73	1	16	1	1	1477	1000	1604	1587	1595	1604	1610
1004	1620	12	30	17	32	2427	1566	891	25	1000	1000	1000	68797	1556	1603	1321	3	1434	1000	1000	1000	1607	1586	1	1	1001	242	2261	2232	3244	0	2417	2278	1000	73	1	16	1	1	1508	1000	1635	1620	1570	1616	1578
1004	1630	12	32	16	30	2434	1597	874	25	1000	1000	1000	68137	1610	1564	1310	3	1461	1000	1000	1000	1600	1559	1	1	1001	237	2260	2254	3231	0	2407	2244	1000	73	1	16	1	1	1480	1000	1620	1639	1629	1620	1603
1004	1619	12	30	16	32	2445	1615	875	25	1000	1000	1000	70514	1567	1618	1327	3	1459	1000	1000	1000	1597	1591	1	1	1001	267	2243	2228	3251	0	2422	2245	1000	73	1	16	1	1	1521	1000	1622	1605	1640	1616	1602

Test 2: throughput

Code:

  prfm plil2strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5663

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15663	117	363	195	368	0	0	24878	15699	9654	25	20226	10235	10000	10100	10000	130764	727484	34	49	12531	15613	15575	12810	3	13099	20100	10200	10000	10200	10000	15503	148	1	1	20201	100	99	2249	100	10100	100	23057	22989	32803	0	24522	22986	10000	1310	1	16	1	1	15574	10111	10000	10100	15687	15730	15621	15741	15603
20204	15618	117	369	194	368	0	0	24765	15665	9630	25	20202	10208	10000	10100	10000	130913	735490	35	49	12496	15612	15705	12854	3	13132	20100	10200	10000	10200	10000	15570	156	1	1	20201	100	99	2322	100	10100	100	23100	22946	33053	0	24557	22740	10000	1310	1	16	1	1	15509	10123	10000	10100	15589	15709	15639	15659	15635
20204	15825	119	361	197	369	0	0	24987	15740	9665	25	20202	10196	10000	10100	10000	131897	735217	28	49	12661	15567	15552	12864	3	12957	20100	10200	10000	10200	10000	15625	150	1	1	20201	100	99	2402	100	10100	100	23082	22971	33151	0	24593	23102	10000	1310	1	16	1	1	15421	10075	10000	10100	15661	15694	15650	15671	15633
20204	15680	117	363	200	363	0	0	24542	15574	9788	25	20220	10190	10000	10100	10000	130783	732206	37	49	12436	15718	15588	12973	3	13156	20100	10200	10000	10200	10000	15590	155	1	1	20201	100	99	2261	100	10100	100	23195	22948	33130	0	24781	23046	10000	1310	1	16	1	1	15614	10108	10000	10100	15603	15630	15656	15656	15523
20204	15650	117	365	190	368	0	0	24717	15693	9633	25	20238	10208	10000	10100	10000	131991	729158	30	49	12588	15506	15722	12872	3	13053	20100	10200	10000	10200	10000	15580	148	1	1	20201	100	99	2337	100	10100	100	22855	23142	32902	0	24734	23172	10000	1310	1	16	1	1	15486	10111	10000	10100	15731	15721	15601	15800	15606
20204	15574	117	370	194	369	0	0	24768	15602	9714	25	20211	10211	10000	10100	10000	131881	731273	43	49	12505	15828	15688	12853	3	13074	20100	10200	10000	10200	10000	15559	141	1	1	20201	100	99	2217	100	10100	100	22968	22998	32937	0	24858	22914	10000	1310	1	17	1	1	15636	10135	10000	10100	15617	15580	15653	15779	15739
20204	15649	117	366	193	357	0	0	24577	15677	9776	25	20208	10199	10000	10100	10000	130987	728518	35	49	12673	15660	15734	12867	3	13161	20100	10200	10000	10200	10000	15679	158	1	1	20201	100	99	2400	100	10100	100	23143	22906	33027	0	24540	22946	10000	1310	1	16	1	1	15454	10111	10000	10100	15557	15623	15685	15518	15755
20204	15698	117	364	191	360	0	0	24604	15591	9626	25	20232	10214	10000	10100	10000	130780	737079	38	49	12379	15671	15829	12953	3	13026	20100	10200	10000	10200	10000	15555	154	1	1	20201	100	99	2293	100	10100	100	23128	22954	33004	0	24633	22913	10000	1310	1	16	1	1	15569	10129	10000	10100	15647	15624	15591	15680	15677
20204	15746	117	370	193	360	0	0	25028	15706	9672	25	20208	10214	10000	10100	10000	131260	733990	30	49	12658	15531	15659	12830	3	13203	20100	10200	10000	10200	10000	15625	155	1	1	20201	100	99	2330	100	10100	100	22857	22893	33070	0	24738	23067	10000	1310	1	16	1	1	15475	10126	10000	10100	15744	15765	15642	15685	15753
20204	15680	116	363	196	365	0	0	24621	15568	9743	25	20187	10225	10000	10100	10000	131801	732797	34	49	12393	15564	15625	12896	3	13004	20100	10200	10000	10200	10000	15604	158	1	1	20201	100	99	2421	100	10100	100	23447	22752	32975	0	24786	23260	10000	1310	1	16	1	1	15512	10090	10000	10100	15677	15647	15595	15719	15581

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5595

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15577	117	361	197	364	24674	15483	9587	25	20151	10130	10000	10010	10000	130207	728550	0	40	49	12525	15541	15510	13069	3	12995	20010	10020	10000	10020	10000	15644	150	1	1	20021	10	9	2193	10	10010	10	22986	22858	33020	0	0	24545	23028	10000	1270	4	16	1	1	15459	10117	10000	10010	15607	15484	15590	15573	15591
20024	15590	117	362	191	363	24728	15602	9715	25	20118	10166	10000	10010	10000	133275	725610	0	41	49	12623	15659	15675	12898	3	13105	20010	10020	10000	10020	10000	15672	148	1	1	20021	10	9	2247	10	10010	10	23185	22967	33012	0	0	24559	23242	10000	1270	1	16	1	1	15444	10159	10000	10010	15674	15610	15541	15654	15700
20024	15803	117	361	191	365	24673	15632	9742	25	20160	10157	10000	10010	10000	131582	727310	0	44	49	12470	15597	15522	13019	3	13045	20010	10020	10000	10020	10000	15508	149	1	1	20021	10	9	2209	10	10010	10	22876	23096	32958	0	0	24506	22897	10000	1270	1	15	1	1	15348	10108	10000	10010	15471	15597	15579	15606	15655
20024	15589	117	359	192	360	24838	15587	9613	25	20175	10142	10000	10010	10000	132791	737561	0	45	49	12504	15593	15742	13138	3	13049	20010	10020	10000	10020	10000	15720	151	1	1	20021	10	9	2362	10	10010	10	22763	22809	33415	0	0	24677	23073	10000	1270	1	16	1	1	15557	10138	10000	10010	15776	15492	15753	15515	15599
20024	15630	117	356	187	366	24671	15667	9677	25	20139	10157	10000	10010	10000	132731	734997	0	34	49	12478	15640	15606	12863	3	13048	20010	10020	10000	10020	10000	15648	150	1	1	20021	10	9	2171	10	10010	10	23070	22919	33204	0	0	24553	23026	10000	1270	1	16	1	1	15391	10144	10000	10010	15557	15716	15643	15688	15607
20024	15482	116	367	197	359	24743	15460	9775	25	20142	10157	10000	10010	10000	132767	735709	0	45	49	12513	15623	15471	13052	3	13019	20010	10020	10000	10020	10000	15554	150	1	1	20021	10	9	2170	10	10010	10	22894	23003	33008	0	0	24764	23079	10000	1270	1	16	1	1	15427	10165	10000	10010	15552	15651	15652	15835	15563
20024	15666	117	364	192	357	24920	15710	9649	25	20109	10127	10000	10010	10000	131944	736446	0	43	49	12510	15564	15620	12962	3	12974	20010	10020	10000	10020	10000	15549	149	1	1	20021	10	9	2310	10	10010	10	22920	22950	33012	0	0	24760	22956	10000	1270	1	16	3	2	15442	10114	10000	10010	15507	15620	15637	15556	15636
20024	15607	116	362	193	357	25027	15595	9671	25	20148	10142	10000	10010	10000	133457	734023	0	49	49	12419	15641	15635	12892	3	13058	20010	10020	10000	10020	10000	15490	151	1	1	20021	10	9	2308	10	10010	10	22911	23088	33066	0	0	24771	22958	10000	1270	1	16	1	1	15543	10117	10000	10010	15651	15682	15778	15571	15532
20024	15588	117	362	191	366	25110	15523	9516	25	20172	10154	10000	10010	10000	132141	730888	0	39	49	12554	15549	15702	12853	3	13016	20010	10020	10000	10020	10000	15450	151	1	1	20021	10	9	2211	10	10010	10	23041	22999	32983	0	0	24698	23117	10000	1270	1	15	1	1	15607	10132	10000	10010	15685	15725	15504	15654	15649
20024	15667	116	357	190	358	25004	15570	9681	25	20157	10142	10000	10010	10000	132078	730092	1	51	49	12437	15697	15604	13039	3	12981	20010	10020	10000	10020	10000	15570	152	1	1	20021	10	9	2262	10	10010	10	22905	23044	32943	0	0	24837	22987	10000	1270	1	16	2	2	15471	10129	10000	10010	15599	15586	15677	15676	15538

Test 3: throughput

Code:

  prfm plil2strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5440

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15499	116	353	188	359	24758	0	15452	9541	25	10100	100	10000	100	10000	500	720612	49	12362	15414	15448	13936	6	14266	10100	200	10000	200	10000	15417	12219	1	1	10201	100	99	2549	100	100	100	23034	22908	33005	0	24771	22932	10000	0	1	1	1	722	2	24	2	2	15334	0	10000	100	15483	15399	15480	15397	15448
10204	15378	115	348	186	355	24733	1	15372	9466	43	10100	100	10000	100	10000	500	718764	49	12377	15374	15415	13868	6	14172	10100	200	10000	200	10000	15441	12294	1	1	10201	100	99	2474	100	100	100	22894	22934	32948	0	24637	22932	10000	0	1	1	1	722	2	24	2	2	15388	0	10000	100	15380	15407	15405	15406	15399
10204	15413	116	366	188	351	24716	1	15411	9393	25	10100	100	10000	100	10000	500	719661	49	12390	15401	15482	13959	6	14163	10100	200	10000	200	10000	15415	12214	1	1	10201	100	99	2507	100	100	100	22971	22978	32903	0	24773	22988	10000	0	1	1	1	722	2	24	2	2	15319	0	10000	100	15339	15463	15484	15339	15421
10204	15385	115	352	182	342	24795	1	15505	9427	25	10100	100	10000	100	10000	500	724572	49	12367	15453	15449	14066	6	14172	10100	200	10000	200	10000	15401	12219	1	1	10201	100	99	2447	100	100	100	22926	23003	33052	0	24737	22926	10000	0	1	1	1	722	2	24	2	2	15262	0	10000	100	15382	15417	15405	15406	15380
10204	15413	116	350	187	350	24767	1	15411	9393	25	10100	100	10000	100	10000	500	719661	49	12324	15466	15378	13990	6	14078	10100	200	10000	200	10000	15373	12191	1	1	10201	100	99	2441	100	100	100	22908	22987	33049	0	24754	22908	10000	0	1	1	1	722	2	24	2	2	15379	0	10000	100	15400	15414	15399	15450	15462
10204	15440	116	359	184	351	24821	1	15458	9419	25	10100	100	10000	100	10000	500	725254	49	12458	15432	15461	13902	6	14208	10100	200	10000	200	10000	15439	12208	1	1	10201	100	99	2491	100	100	100	23010	22889	32835	0	24791	23010	10000	0	1	1	1	722	2	24	2	2	15346	0	10000	100	15571	15437	15356	15427	15484
10204	15462	115	351	190	352	24718	1	15450	9519	25	10100	100	10000	100	10000	500	724082	49	12366	15414	15405	13915	44	14057	10100	200	10000	200	10000	15420	12172	1	1	10201	100	99	2425	100	100	100	22945	22785	32996	0	24778	23026	10000	0	1	1	1	722	2	24	2	2	15297	1	10000	100	15423	15466	15476	15429	15413
10204	15442	115	343	185	351	24709	1	15452	9541	25	10100	100	10000	100	10000	500	719921	49	12336	15328	15525	13984	6	14178	10100	200	10000	200	10000	15369	12166	1	1	10201	100	99	2443	100	100	100	22989	22917	32901	0	24837	22989	10000	0	1	1	1	722	2	24	2	2	15368	0	10000	100	15487	15478	15491	15382	15468
10204	15354	115	352	192	352	24812	1	15391	9472	25	10100	100	10000	100	10000	500	723089	49	12406	15408	15550	13934	6	14068	10100	200	10000	200	10000	15356	12193	1	1	10201	100	99	2415	100	100	100	22940	22994	32932	0	24786	22902	10000	0	1	1	1	722	2	24	2	2	15319	0	10000	100	15339	15463	15484	15339	15421
10204	15385	115	352	182	342	24795	1	15505	9427	25	10100	100	10000	100	10000	500	724572	49	12389	15450	15355	13957	6	14109	10100	200	10000	200	10000	15381	12156	1	1	10201	100	99	2498	100	100	100	22901	22988	32977	0	24852	23004	10000	0	1	1	1	723	2	24	2	2	15333	0	10000	100	15509	15483	15436	15445	15411

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5561

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15512	116	299	147	296	24001	15534	9641	25	10010	10	10000	10	10000	50	726718	0	49	12532	15627	15465	14097	3	14336	10010	20	10000	20	10000	15518	15563	1	1	10021	10	9	2698	10	10	10	22322	22271	32328	1	24038	22334	10000	640	5	16	3	3	15395	10000	10	15568	15564	15571	15530	15564
10024	15646	117	295	148	292	24001	15607	9525	25	10010	10	10000	10	10000	50	727829	1	49	12462	15503	15546	14089	3	14323	10010	20	10000	20	10000	15564	15542	1	1	10021	10	9	2682	10	10	10	22280	22271	32284	0	23932	22275	10000	640	5	16	5	5	15501	10000	10	15536	15571	15530	15511	15624
10024	15579	117	298	148	292	23987	15452	9631	25	10010	10	10000	10	10000	50	728497	0	49	12495	15548	15553	14203	3	14388	10010	20	10000	20	10000	15530	15449	1	1	10021	10	9	2667	10	10	10	22319	22292	32305	0	24007	22238	10000	640	5	16	5	5	15360	10000	10	15580	15480	15582	15628	15533
10024	15568	117	301	147	294	24039	15510	9605	25	10010	10	10000	10	10000	50	727897	0	49	12441	15731	15630	14167	3	14333	10010	20	10000	20	10000	15458	15544	1	1	10021	10	9	2662	10	10	10	22197	22306	32319	0	23929	22404	10000	640	5	16	5	4	15400	10000	10	15609	15475	15512	15636	15598
10024	15572	116	295	146	294	23999	15560	9642	25	10010	10	10000	10	10000	50	728679	0	49	12559	15592	15653	14175	3	14321	10010	20	10000	20	10000	15459	15527	1	1	10021	10	9	2624	10	10	10	22299	22283	32368	0	24028	22271	10000	640	5	16	5	5	15406	10000	10	15529	15554	15567	15471	15595
10024	15643	117	296	147	296	23972	15611	9615	25	10010	10	10000	10	10000	50	726671	0	49	12516	15506	15521	14075	3	14390	10010	20	10000	20	10000	15509	15508	1	1	10021	10	9	2655	10	10	10	22265	22247	32342	0	24025	22261	10000	640	5	16	4	5	15361	10000	10	15609	15579	15557	15592	15555
10024	15580	117	294	146	293	23998	15562	9743	25	10010	10	10000	10	10000	50	725959	0	49	12503	15550	15585	14155	3	14313	10010	20	10000	20	10000	15555	15464	1	1	10021	10	9	2699	10	10	10	22242	22312	32272	0	24022	22287	10000	640	5	16	5	4	15416	10000	10	15588	15502	15629	15569	15539
10024	15602	116	295	149	295	24000	15447	9533	25	10010	10	10000	10	10000	50	724986	1	49	12562	15568	15711	14118	3	14361	10010	20	10000	20	10000	15520	15495	1	1	10021	10	9	2717	10	10	10	22256	22264	32319	0	23919	22242	10000	640	5	16	4	5	15436	10000	10	15607	15612	15607	15634	15568
10024	15552	116	296	149	295	24024	15598	9591	25	10010	10	10000	10	10000	50	730583	0	49	12498	15598	15613	14189	3	14260	10010	20	10000	20	10000	15494	15544	1	1	10021	10	9	2656	10	10	10	22341	22352	32281	0	24024	22312	10000	640	5	16	4	5	15467	10000	10	15513	15509	15446	15524	15526
10024	15650	116	298	149	298	24003	15602	9635	25	10010	10	10000	10	10000	50	731131	0	49	12436	15577	15572	14074	3	14280	10010	20	10000	20	10000	15535	15529	1	1	10021	10	9	2668	10	10	10	22267	22221	32229	0	23987	22269	10000	640	5	16	5	4	15441	10000	10	15448	15579	15586	15432	15554

PRFM (register, PLIL2STRM)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations