Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CCMN (immediate, 32-bit)

Test 1: uops

Code:

  ccmn w1, #3, #0, hi
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
100410358061917251000100010006225010351035805388210001000200010351041110011000100007312711990100010361036103610361036
100410357061917251000100010006225010351035805388210001000200010351041110011000100007312711990100010361036103610361036
100410357061917251000100010006225010351035805388210001000200010351041110011000100007312711990100010361036103610361036
1004103580156917251000100010006225010351035805388210001000200010351041110011000100007312711990100010361036103610361036
100410357061917251000100010006225010351035805388210001000200010351041110011000100007312711990100010361036103610361036
100410358061917251000100010006225010351035805388210001000200010351041110011000100007312711990100010361036103610361036
100410357061917251000100010006225010351035805388210001000200010351041110011000100007312711990100010361036103610361036
100410357061917251000100010006225010351035805388210001000200010351041110011000100007312711990100010361036103610361036
100410357061917251000100010006225010351035805388210001000200010351041110011000100007312711990100010361036103610361036
100410358061917251000100010006225010351035805388210001000200010351041110011000100007312711990100010361036103610361036

Test 2: Latency 2->1

Chain cycles: 1

Code:

  ccmn w1, #3, #0, hi
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204200351500611993025201002010020112129723304916955200352003517425617487201122022430236200351041120201100991002010020100001111318162001120000101002003620036200362003620036
20204200351500611993025201002010020112129723314916955200352003517425617487201122022430236200351041120201100991002010020100001111318162001120000101002003620036200362003620036
20204200351500611993025201002010020112129723314916955200352003517425617487201122022430236200351041120201100991002010020100001111318162001120000101002003620036200362003620036
2020420035150204611993032201002010020112129723314916955200352003517425617487201122022430236200351041120201100991002010020100131111318162001120000101002003620036200362003620036
2020420035150247261993025201002010020112129723314916955200352003517425617487201122022430236200351041120201100991002010020100001111318162001120000101002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425617487201122022430236200351041120201100991002010020100001111318162001120000101002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425617487201122022430236200351041120201100991002010020100001111318162001120000101002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425617487201122022430236200351041120201100991002010020100001111318162001120000101002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425617487201122022430236200351041120201100991002010020100001111318162001120000101002003620036200362003620036
202042003515003361993025201002010020112129723314916955200352003517425617487201122022430236200351041120201100991002010020100001111318162001120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024200351503361199182520010200102001012972470049169552003520035174283175042001020020300202003510411200211091020010200101270127111999520000100102003620036200362003620036
2002420035150061199182520010200102001012972470049169552003520035174283175042001020020300202003510411200211091020010200101270127111999520000100102003620036200362003620036
2002420035150061199182520010200102001012972470049169552003520035174283175042001020020300202003510411200211091020010200101270227111999520000100102003620036200362003620036
200252003515041761199182520010200102001012972470049169552003520035174283175042001020020300202003510411200211091020010200101270127121999520000100102003620036200362003620036
20024200351501261199182520010200102001012972470049169552003520035174283175042001020117300202003510411200211091020010200101270127111999520000100102003620036200362003620036
2002420035150061199182520010200102001012972470049169552003520035174283175042001020020300202003510411200211091020010200101270227211999520000100102003620036200362003620036
2002420035150082199182520010200102001012972470049169552003520035174283175042001020020300202003510411200211091020010200101270127121999520000100102003620036200362003620036
200242003515012361199182520010200102001012972470049169552003520035174283175042001020020300202003510411200211091020010200101270127121999520000100102003620036200362003620036
2002420035150061199182520010200102001012972470049169552003520035174283175042001020020300202003510411200211091020010200101270127111999520000100102003620036200362003620036
2002420035150061199182520010200102001012972470049169552003520035174283175042001020020300202003510411200211091020010200101270127121999520000100102003620036200362003620036

Test 3: Latency 2->2

Code:

  ccmn w0, #3, #0, hi
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)9fl1d tlb miss (a1)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020410035750006199272510200102001021064771204969561003510035867378736102101022420248100351101110201100991010010000001117191610010101001001003610036100361003610036
1020410035750006199272510200102001021064771204969561003510035867378736102101022420248100351101110201100991010010000001117191610010101001001003610036100361003610036
1020410035750006199272510200102001021064771204969551003510035867378736102101022420248100351101110201100991010010000001117191610010101001001003610036100361003610036
1020410035750006199272510200102001021064771204969551003510035867378736102101022420248100351101110201100991010010000031117191610010101001001003610036100361003610036
1020410035750006199272510200102001021064771204969551003510035867378736102101022420248100351101110201100991010010000001117191610010101001001003610036100361003610036
1020410035750006199272510200102001021064771204969561003510035867378736102101022420248100351101110201100991010010000001117191610010101001001003610036100361003610036
1020410035750006199272510200102001021064771204969551003510035867378736102101022420248100351101110201100991010010000001117191610010101001001003610036100361003610036
1020410035750006199272510200102001021064771204969551003510035867378736102101022420248100351101110201100991010010000001117191610010101001001003610036100361003610036
1020410035750006199272510200102001021064771204969561003510035867378736102101022420248100351101110201100991010010000001117181610010101001001003610036100361003610036
1020410035760006199272510200102001021064771204969551003510035867378736102101022420248100351101110201100991010010000001117191610010101001001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)0309191e3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575003006199182510020100201002064729614969561003510035867838754100201002020020100351041110021109100101000000064032732999310010101003610036100361003610036
10024100357500006199182510020100201002064729614969551003510035867838754100201002020020100351041110021109100101000000064022722999310010101003610036100361003610036
10024100357600006199182510020100201002064729614969551003510035867838754100201002020020100351041110021109100101000000064022722999310010101003610036100361003610036
10024100357500006199182510020100201002064729614969551003510035867838754100201002020020100351041110021109100101000000069122722999310010101003610036100361003610036
10024100357500006199182510020100201002064729604969551003510035867838754100201002020020100351041110021109100101000000064022722999310010101003610036100361003610036
100241003575009006199182510020100201002064729604969551003510035867838754100201002020020100351041110021109100101000000064022722999310010101003610036100361003610036
10024100357500006199182510020100201002064729604969551003510035867838754100201002020020100351041110021109100101000000064022722999310010101003610036100361003610036
10024100357500006199182510020100201002064729604969551003510035867838754100201002020020100351041110021109100101000000064022722999310010101003610036100361003610036
100241003575001806199182510020100201002064729604969551003510035867838754100201002020020100351041110021109100101000000364022722999310010101003610036100361003610036
10024100357500006199182510020100201002064729604969551003510035867838754100201002020020100351041110021109100101000000064022722999310010101003610036100361003610036

Test 4: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, #3, #0, hi
  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)eb? int retires (ef)f5f6f7f8fd
1602045343440000028271601201601201601281063738049503285340853408333476333571601281602401602405340866111602011009910016010080100000111101190160005340516002001005340953409534095340953409
1602045340840000028271601201601201601281063738049503285340853408333476333571601281602401602405340866111602011009910016010080100000111101190160005340516002001005340953409534095340953409
1602045340840000028271601201601201601281063738049503285340853408333476333571601281602401602405344266111602011009910016010080100000111101190160005340516002001005340953409534095340953409
16020453408400000282716012016012016012810630680495032853408534083334763335716012816024016024053408661116020110099100160100801000001111011901600053405160020111005340953409534095340953409
1602045340840000033271601201601201601281063738049503285340853408333476333571601281602401602405340866111602011009910016010080100000111101190160005340516002001005340953409534095340953409
1602045340840000028271601201601201601281063738049503285340853408333476333571601281602401602405340866111602011009910016010080100000111101190160005340516002001005340953409534095340953409
1602045340840000028271601201601201601281063738049503285340853408333476333571601281602401602405340866111602011009910016010080100000111101190160005340516002001005340953409534095340953409
16020453408400000815271601201601201601281063738049503285340853408333476333801601281602401602405340866111602011009910016010080100000111101190160005340516002001005340953409534095340953409
1602045340840000028271601201601201601281063738049503285340853408333476333571601281602401602405340866111602011009910016010080100000111101193160005340516002001005340953409534095340953409
1602045340840000028271601201601201601281063738049503285340853408333476333571601281602401602405340866111602011009910016010080100000111101190160005340516002001005340953409534095340953409

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? int retires (ef)f5f6f7f8fd
1600245339140000000001504325160010160010160296102938811549502945337453374333313333511600101601681600205337466111600211091016001080010000000010022821131921149533701600001510105337553375533755337553375
1600245337439901000003302332516001016001016001010293881154950294533745337433331333351160010160020160020533746611160021109101600108001000010901002282131921135533701600001510105337553375533755337553375
1600245337440000000002104325160010160010160010102938811549502945337453374333313333511600101600201600205337466111600211091016001080010000000010022841819211512533701600001510105337553375533755337553375
160024533744010000000480432516001016001016001010293881154950294533745337433331333351160010160020160020533746611160021109101600108001000010187101002282151921149533701600003010105337553375533755337553375
160024533744000010000004925160010160010160010102938811549502945337453374333313333511600101600201600205337466111600211091016001080010000003010022111151942253533701600001518105337553375533755337553564
160024533744000000000270492516001016001016001010293880154950294533745356433331333351160010160020160020533746611160021109101600108001000000001002484255132288533701600003119105337553375533755337553375
1600245337440000001004804925160010160010160010102938811549502945337453374333313333511600101600201600205337466111600211091016001080010000100010024113251941239533701600001518105337553375533755337553375
1600245337439900000002102132516001016001016001010293881154950294533745337433331333351160010160020160020533746611160021109101600108001000000001002483251942293533701600001510105342153375533755337553375
160024533744000010000008302516001016001016001010293881154950294533745356333331333351160010160020160020533746611160021109101600108001000010001002282191921174533701600001510105337553375533755337553375
160024533744000000000001634716001016001016001010293880154950341533745337433331333351160082160020160020533746621160021109101600108001000010001002483131942135533701600003118105337553375533755337553375

Test 5: throughput

Count: 4

Code:

  fcmp s0, s0
  ccmn w0, #3, #0, hi
  ccmn w0, #3, #0, hi
  ccmn w0, #3, #0, hi
  ccmn w0, #3, #0, hi
  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3354

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
5020413458101414028255012240112100104014310013575127800970133951341613416613724567711050156402511001380302200261341613416115020110099100401001000040100000011132202160013413400121001348513417134171341713417
50204134161010028255012240112100104014310013575127800970133951341613416613924677711050156402511001380302200261341613416115020110099100401001000040100012011132210160013412400121001341713417134171341713417
50204134151000028255012240112100104014310013575127800970133951341613416613724567711050156402511001380302200261341613416115020110099100401001000040100000011132211160013413400121001341713417134171341713416
50204134161000028255012240112100104014310013575127800970133951341613416613724567711050156402511001380302200261341613416115020110099100401001000040100000011132210160013413400121001341713417134171341713417
50204134161000028255012240112100104014310013575127800970133951341613416613924677711050156402511001380302200261341613416115020110099100401001000040100000011132210160013413400121001341713417134171341713417
502041341610012028255012240112100104014310013575127800970133951341513416613724567711050156402511001380302200261341613416115020110099100401001000040100000011132210160013413400121001341713417134171341713417
50204134161010028255012240112100104014310013575127800970133951341613416613924677711050156402511001380302200261341613416115020110099100401001000040100000011132210160013413400121001348213417134171341713417
5020413416100120282550122401861001040143100135751278009701339513416134165935245611717950156402511001380302200261341613416115020110099100401001000040100200011132210160013413400121001341713417134171341713417
50204134161010028255012240112100104014310013575127800970133951341613416613724677711050156402511001380302200261341613416115020110099100401001000040100000011132210160013413400121001341713417134171341713417
50204134161000028255012240112100104014310013575127800970133951341613416613724567711050156402511001380302200261341613416115020110099100401001000040100000011132210160013413400121001341713417134171341713417

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
50024134051010001204502550010400101000040010100005734568000011335313382133825575379537109500104002010000800202000013382133821150021109104001010000400100000031400119111337940000101338313383133831338313383
5002413382103000004502550010400101000040010100005734568000011335313382133825575378437109500104002010000800202000013382133821150021109104001010000400100000031400119111337940000101338313383133831338313383
5002413382101000004502550010400101000040010100005734568000001335313382133825577378437109500104002010000800202000013382133821150021109104001010000400100000031400119111337940000101338313383133831338313383
5002413382100000904502550010400101000040010100005734568000001335313382133825575378437109500104002010000800202000013382133821150021109104001010000400100000031400119111337940000101338313383133831338313383
50024133821000000045025500104001010000400101000057345680000013353133821338255753795127109500104002010000800202004813382133821150021109104001010000400100000031400119111337940000101338313383133831338313383
5002413382100000004502550010400101000040010100005734568000011335313382133825575379537109500104002010000800202000013382133821150021109104001010000400100200331400119111337940000101338313383133831338313383
5002413382101000004502550010400101000040010100005734568000001335313382133825575379537109500104002010000800202000013382133821150021109104001010000400100000031400119111337940000101338313383133831338313383
5002413382100000004502550010400101000040010100005734568000001335313382133825575378437109500104002010000800202000013382133821150021109104001010000400100000031400119111337940000101338313383133831338313383
5002413382100000004502550010400101000040010100005734568000001335313382133825577378437109500104002010000800202000013382133821150021109104001010000400100000031400119111337940000101338313383133831338313383
5002413382100000004502550010400101000040010100005734568019201335313382133825577378437109500104002010000800202000013382133821150021109104001010000400100000031400119111337940000101338313383133831338313383