Firestorm: PACIB measurements

Code:

  pacib x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	66	0	399	89	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	0	103	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	0	103	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	0	103	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	89	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  pacib x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	568	0	0	0	0	0	12	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	710	2	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	650	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10202	100	99	10100	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	623	0	0	0	0	0	0	0	0	726	59824	25	10200	10200	10200	1808330	0	49	67067	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	0	0	441	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	0	61	59824	25	10200	10204	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70060	70030
10204	70029	622	0	0	0	0	0	0	0	0	89	59824	25	10200	10200	10258	1808330	0	49	66949	70029	70029	68480	3	68674	10290	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	2	1	0	3	0	710	1	280	1	1	70422	10173	10100	71012	70855	71011	70966	70108
10204	70029	618	0	1	0	12	0	2112	0	0	173	59824	87	10227	10263	10200	1810081	0	49	66949	70029	70029	68480	3	68674	10200	10243	20200	70068	912	1	1	10201	100	99	10100	0	4	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	656	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70068	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	2	0	2	1	2	42248	2	1047	1	295	1	2	70496	10179	10100	70231	70230	70030	70030	70030
10204	70069	622	0	0	0	3	0	24	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70108	68480	3	68725	10200	10200	20200	70029	912	2	1	10201	100	99	10100	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	619	0	0	0	0	0	0	144	0	0	510	59824	25	10020	10020	10048	1807527	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70068	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	3	79	2	2	69805	10010	10010	70030	70108	70030	70030	70030
10024	70029	656	0	0	0	0	0	0	0	0	1	449	59824	25	10023	10020	10020	1807430	1	49	66988	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	2	0	0	1955	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70068	620	0	0	0	0	0	1	132	0	0	1138	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68514	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70068
10024	70029	620	0	0	0	0	0	1	9	88	0	61	59815	25	10020	10020	10020	1807430	0	49	66949	70029	70069	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	2	0	0	0	640	3	79	2	2	69805	10013	10010	70070	70030	70030	70055	70030
10024	70029	663	0	0	0	0	1	0	0	0	0	321	59824	25	10020	10020	10020	1807430	1	49	66988	70029	70029	68502	3	68696	10020	10185	20020	70069	870	1	1	10021	10	9	10010	0	0	0	0	0	0	2	0	646	2	87	2	2	69805	10010	10010	70030	70055	70030	70030	70030
10024	70069	655	0	0	0	0	0	0	0	88	0	503	59788	111	10032	10032	10115	1807818	0	49	67028	70188	70189	68502	3	68749	10020	10020	20104	70186	870	4	1	10021	10	9	10010	0	0	2	1	0	0	0	0	640	2	79	2	3	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	623	0	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10048	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	1	0	0	0	0	640	2	79	2	2	69805	10013	10010	70030	70030	70030	70069	70030
10024	70029	620	0	1	0	0	1	1	0	0	0	726	59824	25	10020	10023	10048	1807527	0	49	66949	70029	70029	68502	3	68696	10020	10060	20020	70029	870	2	1	10021	10	9	10010	0	2	0	0	4	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70069	70069
10024	70029	616	0	1	0	0	0	0	12	0	0	159	59824	25	10023	10020	10020	1807430	0	49	66987	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70070	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	9	88	0	145	59824	46	10023	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68723	10020	10020	20020	70069	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70069	70030	70030	70109	70030

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  pacib x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	80029	697	0	0	0	0	0	213	0	2787	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	3	0	1910	3	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	699	0	0	0	0	0	537	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	3	2	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	699	0	0	0	0	0	270	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	1	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	699	0	0	0	0	1	309	0	103	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80070	700	0	0	0	0	0	468	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	2	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	700	0	0	0	0	0	3	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	2	0	0	0	0	1910	1	72	1	2	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	699	0	0	0	0	0	537	0	944	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	3	0	1910	1	96	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	700	0	0	0	22	17	3759	2112	14510	69652	427	20333	20328	21785	4952521	0	49	78024	80777	81035	76084	88	76654	21608	20200	40200	80029	144	1	1	30201	100	99	30100	2	0	2	2	38033	0	2268	1	288	1	2	80538	20250	30100	81203	81286	80975	81292	81218
30204	81098	708	0	0	0	2	11	2040	880	61	69799	25	20200	20200	20200	4942601	0	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	699	0	0	0	0	0	63	0	726	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	1940	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
30024	80029	700	0	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	1890	4	72	3	7	79803	20010	0	30010	80055	80030	80030	80030	80030
30024	80029	745	0	0	0	0	0	0	0	0	0	89	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	1890	3	72	3	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	0	132	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	1	0	0	0	1890	4	72	3	7	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	703	0	0	0	0	0	0	12	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	12	0	1890	3	72	3	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	700	0	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	1890	3	72	3	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	703	0	0	0	0	0	0	0	0	0	388	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	1890	6	72	3	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	705	0	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	3	0	1890	7	72	7	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	703	0	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	1890	4	72	3	7	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	11	76209	20020	20020	40020	80029	144	3	1	30021	10	9	30010	0	0	1	0	0	0	1890	4	72	7	4	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	698	0	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	1890	7	72	3	3	79803	20010	0	30010	80030	80030	80030	80030	80030

Test 4: throughput

Count: 8

Code:

  pacib x0, x8
  pacib x1, x8
  pacib x2, x8
  pacib x3, x8
  pacib x4, x8
  pacib x5, x8
  pacib x6, x8
  pacib x7, x8

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80204	80062	643	0	0	0	0	0	0	0	0	77	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	3	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	645	0	0	0	0	0	0	12	0	77	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	12	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80229	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	5110	2	25	2	2	80058	80100	0	80100	80082	80129	80036	80036	80036
80204	80035	701	0	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	3	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	77136	80219	80035	69966	3	69984	80200	80200	160312	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	699	0	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	3	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	0	0	105	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80229	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	0	0	91	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80080	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	0	0	77	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80040	697	0	0	0	0	0	0	21	0	0	700	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	2	1	80021	10	9	80010	0	0	0	1	0	0	0	5020	0	7	25	0	0	13	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80081	700	0	0	0	0	0	0	0	0	0	822	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	160088	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	5020	3	2	25	0	0	4	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	750	0	0	0	0	0	0	0	0	1	834	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	7	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	0	0	5020	0	4	25	0	0	4	3	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	697	0	0	0	0	0	0	12	0	0	510	25	80020	80020	80020	400100	1	49	76955	80035	80080	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	5020	0	4	25	0	0	4	4	80024	80010	80010	80036	80072	80047	80036	80036
80024	80035	696	0	1	0	0	0	0	0	0	0	318	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	5020	0	2	25	0	0	5	5	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	0	0	0	77	25	80020	80020	80020	400100	1	49	77000	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	5020	0	4	25	0	0	4	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	0	0	88	0	106	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	2	1	80021	10	9	80010	0	0	0	0	2	6	0	5020	0	2	25	0	0	4	5	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	0	0	0	63	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	5020	0	5	25	0	0	4	5	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	2	3	0	5020	0	4	25	0	0	4	2	80024	80010	80010	80036	80080	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80080	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	2	2	1	1	0	9538	0	5320	0	8	225	0	0	7	13	80670	80493	80010	81075	81211	80943	81302	81126

PACIB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations