Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADDS (uxtb, 32-bit)

Test 1: uops

Code:

  adds w0, w0, w1, uxtb
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004203515027810001862252000200010001262352035203517293186610001000200020354111100110000732432219202000100020362036203620362036
100420351506110001862252000200010001262352035203517293186610001000200020354111100110000732432219202000100020362036203620362036
1004203515015610001862252000200010001262352035203517293186610001000200020354111100110000732432219202000100020362036203620362036
100420351506110001862252000200010001262352035203517293186610001000200020354111100110000732432219202000100020362036203620362036
1004203515035610001862252000200010001262352035203517293186610001000200020354111100110000732432219202000100020362036203620362036
100420351606110001862252000200010001262352035203517293186610001000200020354111100110000732432219202000100020362036203620362036
100420351506110001862252000200010001262352035203517293186610001000200020354111100110000732432219202000100020362036203620362036
100420351506110001862252000200010001262352035203517293186610001000200020354111100110000732432219202000100020362036203620362036
100420351506110001862252000200010001262352035203517293186610001000200020354111100110000732432219202000100020362036203620362036
1004203515336110001862252000200010001262352035203517293186610001000200020354111100110000732432219202000100020362036203620362036

Test 2: Latency 1->2

Code:

  adds w0, w0, w1, uxtb
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9facc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020420035150186110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100007100239221992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100007100239221992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100007100239221992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100007100239221992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100007100239221992220000101002008220036200362003620036
10204200351502016110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100007100239221992220000101002003620036200362003620036
1020420035150072610000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100007100239221992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100007100239221992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100007100239221992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051214916955200352003518581318720101001020020200200354111102011009910010100100307100239221992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515006110000198624820056200101001013052294916955200352003518615318740100101002020020200354111100211091010010100200640341221996420000100102003620036200362003620036
100242003515006110000198622520010200101001013052294916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
1002420035150910310000198622520010200101001013052294916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
10024200351502710310000198622520010200101001013052294916955200352003518603318740100101002020020200354111100211091010010101030640241221993020000100102003620036200362003620036
100242003515006110000198622520010200101001013052294916955200352017618650318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
10024200351492946110000198622520010200101001013052294916955200352003518603318740100101002020020200354111100211091010010100036640241221993020000100102003620036200362003620036
1002420035150216110000198622520010200101001013052294916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
100242003515006110000198622520010200101001013052294916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
100242003515006110000198622520010200101001013052294916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
100242003515006110000198622520010200101001013052294916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  adds w0, w1, w0, uxtb
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515087611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
10204200351500611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
102042003514912611000019862252010020125101761305121491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
10204200351500611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
10204200351500611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
10204200351500611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
102042003515030611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
10204200351500611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
102042003515006311000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
10204200351500611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351500611000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101006400141221993020000100102003620036200362003620036
10024200351500841000019862252001020010100901305229149169552003520035186033187401001010020200202003541111002110910100101006400241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101006400241221993020000100102003620036200362003620036
100242003515015611000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101006400241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101006400241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101006400241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101006400241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101006400241221993020000100102003620036200362003620036
100242003515015611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101006400241221993020000100102003620036200362003620036
100242003515012611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101006400241221993020000100102003620036200362003620036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  adds w0, w1, w2, uxtb
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03091e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202043003522400061100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101000000111131911602998330000201003003630130300363003630036
202043003522500061100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101000062111131901602998330000201003003630036300363003630036
20204300352250001261000029899453010030100202621956240049269553003530035274021027486201072022430236300358511202011009910020100101000000111132001602998230000201003003630036300363003630036
202043003522500061100002989925301003010020107195624004926955300353003527391827485201072022430236300358511202011009910020100101000132111132001602998330000201003003630036300363003630036
2020430035225000943100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101000000111132001602998230000201003003630036300363003630036
202043003522500061100002989925301003010020107195624004926955300353003527391827486201072022430236300358511202011009910020100101002100111131902412998230000201003003630036300363003630036
2020430081225113217661100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101000000111131901602998230000201003003630036300363003630036
202043003522500061100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101000000111131901602998230000201003003630036300363003630036
2020430035225000103100002989925301003010020107195624004926955300353003527391827485201072022430236300358511202011009910020100101000002111131901602998230000201003003630036300363012730036
202043003522506061100002989925301003010020107195624004926955300353003527391827485201072022430236300358511202011009910020100101000000111132001602998230000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)0309l2 tlb miss data (0b)181e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024300352250008106110000298912530010300102001019562890149269553003530035273913274982001020020300203003585112002110910200101001000001270133112995930000200103003630036300363003630036
2002430035225000006110000298912530010300102001019562890149269553003530035273913274982001020020300203003585112002110910200101001000001270133112995930000200103003630036300363003630036
2002430035225000006110000298912530010300102001019562890149269553003530035273913274982001020020300203003585112002110910200101001000001270133112995930000200103003630036300363003630036
2002430035225000006110000298912530010300102001019562890149269553003530035273913274982001020020300203003585112002110910200101001010001270133112995930000200103003630036300363003630036
2002430035225000006110000298912530010300102001019562890149269553003530035273913274982001020020300203003585112002110910200101001000001270133112995930000200103003630036300363003630036
2002430035225000006110000298912530010300102001019562890149269553003530035273913274982001020020300203003585112002110910200101001010001270133112995930000200103003630036300363003630036
2002430035225000006110000298912530010300102023919562890149269553003530035273913274982001020020300203003585112002110910200101001000001270133112995930000200103003630036300363003630036
2002430035225000006110000298912530010300102001019562890149269553003530035273913274982001020020300203003585112002110910200101001000001270233112998830000200103003630036300363003630036
2002430035225000006110000298912530010300102001019562890149269553003530035273913274982001020020300203003585112002110910200101001000001270133112995930000200103003630036300363003630036
2002430035224000006110000298912530010300102001019562890149269553003530035273913274982001020020300203003585112002110910200101001000001270133112995930000200103003630036300363003630036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  adds w0, w1, w2, uxtb
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202043003522500000006110000298992530100301002010719562400492695530035300352739182748520107202243023630035851120201100991002010010100001030111131901602998330000201003003630036300363003630036
202043003522500100006110000298992530100301002010719562401492695530035300352739182748520107202243023630035851120201100991002010010100002000111132001602998330000201003003630036300363003630036
202043003522400000006110000298992530100301002010719562401492695530035300352739172748520107202243023630035851120201100991002010010100000000111131901602998230000201003003630036300363003630036
202043003522500000006110000298992530100301002010719562400492695530035300352739172748520107202243023630035851120201100991002010010100000000111131901602998230000201003003630036300363003630036
202043003522500000006110000298992530100301002010719562401492695530035300352739172748620107202243023630035851120201100991002010010100001000111131901602998330000201003003630036300363003630036
202043003522500000006110000298992530100301002010719562400492695530035300352739172748620107202243023630035851120201100991002010010100001030111132001602998330000201003003630036300363003630036
202043003522400000006110000298992530100301002010719562401492695530035300352739182748620107202243023630035851120201100991002010010100000000111131901602998330000201003003630036300363003630036
202043003522400000006110000298992530100301002010719562400492695530035300352739182748520107202243023630035851120201100991002010010100000200111132001603001730000201003003630036300363003630036
202043003522500000006110000298992530100301002010719562401492695530035300352739172748520107202243023630035851120201100991002010010100001000111131901602998230000201003003630036300363003630036
202043003522500000006110000298992530100301002010719562401492695530035300352739172748620107202243023630035851120201100991002010010100000000111131901602998230000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522506710000298912530010300102001019562891492695530035300352739132749820010201083002030035851120021109102001010010000501272533692995930000200103003630036300363003630036
200243003522506110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010000301272433782995930000200103003630036300363003630036
200243003522506110000298912530010300102008619562891492695530035300352739132749820010200203002030035851120021109102001010010000001270533992995930000200103003630036300363003630036
200243003523306110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010000031272533682995930000200103003630036300363003630036
200243003522506110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010000001270833692995930000200103003630036300363003630036
200243003522506110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010000001272733952995930000200103003630036300363003630036
2002430035225061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100100000012701033892995930000200103003630036300363003630036
2002430035225061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100100000012721033962995930000200103003630036300363003630036
200243003522506110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010000001272933982995930000200103003630036300363003630036
2002430035225010310000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010000001270733592995930000200103003630036300363003630036

Test 6: throughput

Count: 8

Code:

  adds w0, w8, w9, uxtb
  adds w1, w8, w9, uxtb
  adds w2, w8, w9, uxtb
  adds w3, w8, w9, uxtb
  adds w4, w8, w9, uxtb
  adds w5, w8, w9, uxtb
  adds w6, w8, w9, uxtb
  adds w7, w8, w9, uxtb
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204534494000091680000487412516010016010080100344000504950330534105341043298302434336080100802001602005341039118020110099100801001000392051101241153390160000801005341153469534695341153411
8020453410400102128000048741251601001601008010034400050495033053410534104329830243433608010080200160200534103911802011009910080100100000051101241153390160000801005341153411534115341153411
80204534104000011768000048741251601001601008010034400051495033053410534104329829093433608010080200160200534103911802011009910080100100004051101241153390160000801005341153411534115341153411
80204534104000122508000048741251601001601918030334409731495033053410534104331429093433608010080200160200534103931802011009910080100100030051101241153390160000801005341153411534115341153411
8020453410400004668000048741251601001601008010034400050495033053410534104329830243433608010080200160200534103911802011009910080100100130051101241153390160000801005341153411534115341153411
80204534104000013928000048741251601001601008010034400050495033053410534104329829093433608010080200160200534103911802011009910080100100000051101241153390160000801005341153411534115341153411
8020453410400002318000048741251601001601008010034400050495033053410534104329830243433608010080200160200534103911802011009910080100100000051101241153390160000801005341153411534115341153411
80204534104000121498000048741251601001601008010034400050495033053410534104329829093433608010080200160200534103911802011009910080100100000051100241153390160000801005341153411534115341153411
8020553410399001458000048741251601001601008010034400050495033053410534104329830243433608010080200160200534103911802011009910080100100000051101241153390160000801005341153411534115341153411
8020453410400002088000048741251601001601008010034400050495033053410534104329829093433608010080200160200534103911802011009910080100100000051101241153390160000801005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)031e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024534014000002988000047946251600101600108001034381300149503005338053380432903251343352800108002016002053380391180021109108001010000502072405653360160000800105338153381533815338153381
80024533803990001708000047946251600101600108001034381300149503005338053380432902936343352800108002016002053380391180021109108001010000502052408553360160000800105338153381533815338153381
800245338040000036180000479462516010216010180010343906201495030053380536094329032512143352800108013216002053380391180021109108001010000502052405653360160000800105338153381533815338153381
80024533804000002368000047946251600101600108001034381300149503005338053380432903251343352800108002016002053380391180021109108001010100502072405753360160000800105338153381533815338153381
80024533803990003748000047946251600101600108001034381300149503005338053380432903251343352800108002016002053380391180021109108001010100502072408853360160090800105338153381535535360953381
8002453380399165108042048000047946251600101600108001034381301149503005338053380432902936343352800108002016002053380391180021109108001010003502062406553360160000800105338153381533815338153381
80024533803990002108000047946251600101600108001034381300149503005338053380432902936343352800108002016002053380391180021109108001010122748502062408753360160000800105338153381533815338153381
80024533804000002138000047946251600101600108001034381300149503005338053380432903251343352800108002016002053380391180021109108001010000502062405653360160000800105338153381533815338153381
80024533804000001708000047946251600101600108001034381300149503005338053380432903251343352800108002016002053380391180021109108001010000502062418853360160000800105338153381533815338153381
80024533803990001708000047946251600101600108001034381300149503005338053380432902749343352800108002016002053380391180021109108001010000502062407853360160000800105338153381533815338153381