Firestorm: ADDS (uxtb, 32-bit) measurements

Code:

  adds w0, w0, w1, uxtb

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	15	0	278	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	73	2	43	2	2	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	73	2	43	2	2	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	156	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	73	2	43	2	2	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	73	2	43	2	2	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	356	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	73	2	43	2	2	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	73	2	43	2	2	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	73	2	43	2	2	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	73	2	43	2	2	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	73	2	43	2	2	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	33	61	1000	1862	25	2000	2000	1000	126235	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	73	2	43	2	2	1920	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  adds w0, w0, w1, uxtb

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	18	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	0	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	0	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	0	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	0	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	0	2	39	2	2	19922	20000	10100	20082	20036	20036	20036	20036
10204	20035	150	201	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	0	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	726	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	0	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	0	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	0	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	3	0	710	0	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	61	10000	19862	48	20056	20010	10010	1305229	49	16955	20035	20035	18615	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	2	0	0	640	3	41	2	2	19964	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	9	103	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	27	103	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	1	0	3	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20176	18650	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	149	294	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	3	6	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	21	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 1->3

Code:

  adds w0, w1, w0, uxtb

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	87	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	149	12	61	10000	19862	25	20100	20125	10176	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	30	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	631	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	640	0	1	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	84	10000	19862	25	20010	20010	10090	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	640	0	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	640	0	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	15	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	640	0	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	640	0	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	640	0	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	640	0	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	640	0	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	15	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	640	0	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	12	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	640	0	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  adds w0, w1, w2, uxtb
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30035	224	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1319	1	16	0	29983	30000	20100	30036	30130	30036	30036	30036
20204	30035	225	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	6	2	1	1	1	1319	0	16	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	126	10000	29899	45	30100	30100	20262	1956240	0	49	26955	30035	30035	27402	10	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1320	0	16	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	1	3	2	1	1	1	1320	0	16	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	943	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1320	0	16	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	2	1	0	0	1	1	1	1319	0	24	1	29982	30000	20100	30036	30036	30036	30036	30036
20204	30081	225	1	132	176	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1319	0	16	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1319	0	16	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	103	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	2	1	1	1	1319	0	16	0	29982	30000	20100	30036	30036	30036	30127	30036
20204	30035	225	0	6	0	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1320	0	16	0	29982	30000	20100	30036	30036	30036	30036	30036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30035	225	0	0	0	81	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	1	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	1	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	61	10000	29891	25	30010	30010	20239	1956289	0	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	2	33	1	1	29988	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	224	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  adds w0, w1, w2, uxtb
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30035	225	0	0	0	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	1	0	3	0	1	1	1	1319	0	16	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	1	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	2	0	0	0	1	1	1	1320	0	16	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	224	0	0	0	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	1	0	0	0	1	1	1	1319	0	16	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	1	0	3	0	1	1	1	1320	0	16	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	224	0	0	0	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	224	0	0	0	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	0	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	2	0	0	1	1	1	1320	0	16	0	30017	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	1	0	0	0	1	1	1	1319	0	16	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	0	16	0	29982	30000	20100	30036	30036	30036	30036	30036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30035	225	0	67	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20108	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	5	0	1272	5	33	6	9	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	3	0	1272	4	33	7	8	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20086	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	5	33	9	9	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	233	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	3	1272	5	33	6	8	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	8	33	6	9	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1272	7	33	9	5	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	10	33	8	9	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1272	10	33	9	6	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1272	9	33	9	8	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	103	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	7	33	5	9	29959	30000	20010	30036	30036	30036	30036	30036

Test 6: throughput

Count: 8

Code:

  adds w0, w8, w9, uxtb
  adds w1, w8, w9, uxtb
  adds w2, w8, w9, uxtb
  adds w3, w8, w9, uxtb
  adds w4, w8, w9, uxtb
  adds w5, w8, w9, uxtb
  adds w6, w8, w9, uxtb
  adds w7, w8, w9, uxtb

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	53449	400	0	0	916	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	39	2	0	5110	1	24	1	1	53390	160000	80100	53411	53469	53469	53411	53411
80204	53410	400	1	0	212	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	1176	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	4	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	12	250	80000	48741	25	160100	160191	80303	3440973	1	49	50330	53410	53410	43314	2909	3	43360	80100	80200	160200	53410	39	3	1	80201	100	99	100	80100	100	0	3	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	466	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	1	3	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	1392	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	231	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	12	149	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	0	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80205	53410	399	0	0	145	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	208	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	53401	400	0	0	0	298	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	7	24	0	5	6	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	170	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	5	24	0	8	5	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	361	80000	47946	25	160102	160101	80010	3439062	0	1	49	50300	53380	53609	43290	3251	21	43352	80010	80132	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	5	24	0	5	6	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	236	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	1	0	0	5020	7	24	0	5	7	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	374	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	1	0	0	5020	7	24	0	8	8	53360	160090	80010	53381	53381	53553	53609	53381
80024	53380	399	165	108	0	4204	80000	47946	25	160010	160010	80010	3438130	1	1	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	3	5020	6	24	0	6	5	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	210	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	12	2	748	5020	6	24	0	8	7	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	213	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	6	24	0	5	6	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	170	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	6	24	1	8	8	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	170	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	2749	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	5020	6	24	0	7	8	53360	160000	80010	53381	53381	53381	53381	53381

ADDS (uxtb, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations