Firestorm: STRH (register, sxtw) measurements

Code:

  strh w0, [x6, w7, sxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	551	4	1	1	0	0	14	0	1	537	16	15	0	25	1000	1000	1000	22908	561	559	363	3	410	1000	1000	3000	559	552	1	1	1001	1000	1000	1015	14	0	0	2	1014	0	1	18	1002	16	0	14	0	73	1	16	1	1	544	1000	554	553	551	562	559
1004	558	4	1	1	1	0	21	0	1	545	16	16	5	25	1000	1000	1000	22836	557	547	360	3	411	1000	1000	3000	548	553	1	1	1001	1000	1000	1016	15	36	0	0	1016	0	0	14	1002	14	36	14	1	73	1	16	1	1	544	1000	560	560	553	548	551
1004	561	5	1	1	0	0	19	0	1	533	16	16	2	25	1000	1000	1000	22692	559	547	370	3	405	1000	1000	3000	558	547	1	1	1001	1000	1000	1015	15	36	0	1	1016	0	1	16	1002	16	36	14	2	73	1	16	1	1	555	1000	559	548	548	559	553
1004	551	4	1	1	0	0	21	0	1	535	16	16	5	25	1000	1000	1000	23197	559	550	360	3	418	1000	1000	3000	558	547	1	1	1001	1000	1000	1015	14	0	0	0	1016	0	1	14	1002	16	36	14	1	73	1	16	1	1	556	1000	561	560	560	560	548
1004	552	4	1	0	1	0	21	1	1	532	16	16	2	25	1000	1000	1000	22719	547	547	371	3	418	1000	1000	3000	558	552	1	1	1001	1000	1000	1014	16	36	0	1	1016	0	0	19	1002	14	36	14	2	73	1	16	1	1	544	1000	553	548	548	559	558
1004	559	4	1	1	0	6	19	0	1	544	0	16	0	25	1000	1000	1000	23220	559	547	371	3	419	1000	1000	3000	558	551	1	1	1001	1000	1000	1015	14	36	0	1	1016	0	1	14	1002	16	36	14	1	73	1	16	1	1	544	1000	561	560	559	548	548
1004	552	4	1	1	1	0	19	0	1	544	16	16	2	25	1000	1000	1000	22718	558	547	372	3	405	1000	1000	3000	559	552	1	1	1001	1000	1000	1014	16	36	0	1	1016	0	0	14	1000	14	35	14	0	73	1	16	1	1	556	1000	548	550	559	549	559
1004	547	5	1	1	1	0	19	1	1	545	0	16	3	25	1000	1000	1000	22693	558	551	372	3	408	1000	1000	3000	559	552	1	1	1001	1000	1000	1015	15	36	0	0	1014	0	1	14	1002	16	0	14	2	73	1	16	1	1	544	1000	559	559	553	553	553
1004	560	4	1	1	1	0	14	0	1	532	16	16	5	25	1000	1000	1000	23247	547	550	372	3	418	1000	1000	3000	559	547	1	1	1001	1000	1000	1016	15	36	0	2	1014	0	0	15	1002	14	36	14	1	73	1	16	1	1	547	1000	553	554	552	548	562
1004	547	4	1	1	1	0	14	1	1	536	16	0	1	25	1000	1000	1000	23246	558	551	372	3	407	1000	1000	3000	559	552	1	1	1001	1000	1000	1014	16	0	0	2	1016	0	0	16	1002	16	0	14	0	73	1	16	1	1	549	1000	560	548	553	553	552

Count: 8

Code:

  strh w0, [x6, w7, sxtw]
  strh w0, [x6, w7, sxtw]
  strh w0, [x6, w7, sxtw]
  strh w0, [x6, w7, sxtw]
  strh w0, [x6, w7, sxtw]
  strh w0, [x6, w7, sxtw]
  strh w0, [x6, w7, sxtw]
  strh w0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40047	300	0	1	0	1	1	0	0	0	14	0	0	0	1	40039	16	16	2	25	80100	100	80000	100	80006	500	1839718	1	49	36972	40054	40047	29971	7	29999	80106	200	80016	200	240048	40054	32000	1	1	80201	100	99	100	80000	100	80000	100	80014	15	44	0	0	80016	0	1	921	80002	14	44	14	1	1	1	1	5118	0	16	0	2	40048	0	80000	100	40048	40055	40064	40048	40056
80204	40047	299	0	1	0	1	0	0	0	0	14	1	0	0	1	40037	0	16	1	25	80100	100	80000	100	80006	500	1840035	1	49	36967	40052	40047	29970	7	30006	80107	200	80016	200	240048	40051	32006	1	1	80201	100	99	100	80000	100	80000	100	80016	15	44	0	0	80016	1	1	17	80002	14	44	14	1	1	1	1	5118	0	16	0	0	40044	0	80000	100	40055	40048	40055	40048	40055
80204	40047	300	0	1	1	1	1	0	0	0	17	0	0	0	1	40037	16	16	1	25	80100	100	80000	100	80006	500	1842737	1	49	36972	40054	40052	29982	7	29999	80107	200	80016	200	240048	40047	32000	1	1	80201	100	99	100	80000	100	80000	100	80015	15	43	0	0	80016	1	2	16	80000	16	44	14	1	1	1	1	5118	0	16	0	0	40044	0	80000	100	40191	40335	40053	40055	40053
80204	40047	299	0	1	1	1	1	0	0	0	19	1	0	0	1	40039	0	16	2	25	80100	100	80000	100	80012	500	1839992	0	49	36974	40052	40053	29962	62	29994	80112	200	80022	200	240066	40051	32007	1	1	80201	100	99	100	80000	100	80000	100	80015	15	0	0	1	80016	3	0	21	80002	14	44	14	0	2	2	2	5128	1	23	1	1	40051	0	80000	100	40048	40055	40048	40056	40053
80204	40054	300	0	1	0	0	1	0	0	0	19	0	0	0	1	40037	16	16	4	25	80100	100	80000	100	80013	500	1839992	1	49	36984	40054	40047	29964	10	29987	80112	200	80022	200	240066	40047	32017	1	1	80201	100	99	100	80000	100	80000	100	80014	15	44	0	0	80016	0	0	19	80002	16	43	14	0	2	2	2	5128	1	23	2	1	40051	0	80000	100	40053	40048	40054	40055	40053
80204	40054	300	0	1	1	0	1	0	0	0	15	1	0	0	1	40039	16	16	6	25	80220	100	80000	100	80012	500	1839992	1	49	36974	40603	40054	29964	10	30004	80112	200	80022	200	240066	40054	32000	1	1	80201	100	99	100	80000	100	80000	100	80015	14	44	0	1	80016	1	1	16	80002	16	44	14	0	2	2	2	5128	1	23	1	1	40051	0	80000	100	40054	40048	40055	40065	40053
80204	40054	300	0	1	1	1	1	0	0	0	17	0	0	0	1	40037	16	16	2	25	80100	100	80000	100	80012	500	1839897	0	49	36974	40054	40047	29957	10	29994	80112	200	80022	200	240066	40047	32007	1	1	80201	100	99	100	80000	100	80000	100	80015	15	44	0	0	80016	1	1	18	80000	14	44	14	0	2	2	2	5128	1	23	1	1	40044	0	80000	100	40055	40048	40064	40055	40048
80204	40047	300	0	1	0	1	1	0	0	0	20	1	0	0	1	40039	16	16	1	25	80100	100	80000	100	80000	500	1839835	1	49	36968	40054	40047	29956	6	29998	80100	200	80000	200	241089	40054	32001	1	1	80201	100	99	100	80000	100	80000	100	80015	15	44	0	1	80014	1	1	20	80002	16	44	14	2	1	1	1	5120	2	24	2	4	40060	0	80000	100	40048	40053	40056	40048	40055
80204	40047	300	0	1	1	0	1	0	0	0	18	1	0	0	1	40036	0	0	1	25	80100	100	80000	100	80000	500	1849165	1	49	36967	40047	40054	29956	6	29993	80100	200	80000	200	240000	40054	40326	1	1	80201	100	99	100	80000	100	80000	100	80016	14	44	0	0	80016	0	1	17	80002	16	44	14	1	1	1	1	5120	2	24	2	2	40044	0	80000	100	40048	40055	40053	40055	40053
80204	40054	300	0	1	0	0	0	0	0	0	14	1	0	0	1	40048	0	0	2	25	80100	100	80000	100	80000	500	1839930	1	49	36984	40054	40054	29956	6	29998	80100	200	80000	200	240000	40054	32007	1	1	80201	100	99	100	80000	100	80000	100	80014	16	0	0	0	80014	0	0	14	80002	16	0	14	2	1	1	1	5191	2	24	2	2	40044	0	80000	100	40048	40055	40055	40064	40048

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40054	300	1	1	0	0	0	0	18	1	0	0	1	40037	16	16	0	25	80010	10	80000	10	80000	50	1839956	0	1	49	36974	40054	40054	29990	3	30027	80010	20	80000	20	240000	40052	40053	1	1	80021	10	9	10	80000	10	80000	10	80015	15	43	0	1	80014	0	2	17	80002	14	44	14	1	0	5020	16	16	12	12	40051	80000	10	40053	40055	40052	40048	40052
80024	40063	300	1	0	0	1	0	6	18	1	0	0	1	40038	16	16	7	25	80010	10	80000	10	80000	50	1839934	0	1	49	36974	40054	40054	29989	3	30032	80010	20	80000	20	240000	40052	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	14	0	0	0	80016	0	0	17	80002	16	0	14	1	0	5020	13	16	12	13	40044	80000	10	40055	40048	40055	40048	40055
80024	40047	300	1	1	1	1	0	0	18	1	0	0	1	40039	16	16	2	25	80010	10	80000	10	80000	50	1840487	0	1	49	36974	40047	40054	29989	3	30032	80128	20	80000	20	240000	40054	40064	1	1	80021	10	9	10	80000	10	80000	10	80015	15	44	0	2	80014	0	0	20	80000	16	44	14	2	0	5020	13	16	13	13	40051	80000	10	40053	40055	40054	40055	40054
80024	40052	300	1	1	1	1	0	0	21	1	0	0	1	40039	16	16	1	25	80010	10	80000	10	80000	50	1840028	0	1	49	36972	40052	40047	29987	3	30034	80010	20	80000	20	240000	40054	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	14	44	0	1	80016	0	1	16	80002	16	44	14	0	0	5020	12	16	13	12	40050	80000	10	40048	40055	40049	40055	40064
80024	40054	300	1	0	1	0	0	0	14	1	0	0	1	40039	16	16	5	25	80010	10	80000	10	80000	50	1840004	0	1	49	36972	40054	40052	29987	3	30034	80010	20	80000	20	240000	40054	40054	1	1	80021	10	9	10	80000	10	80000	10	80016	16	44	0	2	80016	0	0	14	80002	16	44	14	1	0	5020	12	16	12	12	40050	80000	10	40055	40048	40064	40055	40064
80024	40054	300	1	0	1	1	0	6	19	1	0	0	1	40037	16	0	4	25	80010	10	80000	10	80000	50	1839956	0	1	49	36983	40054	40048	29998	3	30034	80010	20	80000	20	240000	40054	40054	1	1	80021	10	9	10	80000	10	80000	10	80016	16	44	0	3	80016	0	1	16	80002	16	44	14	1	0	5020	12	16	13	12	40051	80000	10	40053	40048	40055	40064	40055
80024	40052	300	1	1	1	1	0	0	17	1	0	0	1	40048	16	16	0	25	80010	10	80000	10	80000	50	1839934	0	1	49	37529	40054	40054	29982	3	30032	80010	20	80000	20	240000	40052	40054	1	1	80021	10	9	10	80000	10	80000	10	80016	15	44	0	0	80016	0	0	20	80002	14	44	14	2	0	5020	12	16	13	13	40044	80000	10	40055	40052	40055	40048	40048
80024	40054	300	1	0	1	1	0	0	18	1	0	0	1	40039	0	16	2	25	80010	10	80000	10	80000	50	1840052	0	1	49	36973	40052	40053	29989	3	30044	80010	20	80000	20	240000	40064	40051	1	1	80021	10	9	10	80000	10	80000	10	80015	16	44	0	1	80016	0	2	18	80002	16	44	14	0	0	5020	14	16	13	11	40051	80000	10	40048	40055	40048	40055	40054
80024	40052	300	1	1	1	1	0	0	15	0	0	0	1	40039	16	16	2	25	80010	10	80000	10	80000	50	1839956	0	1	49	36974	40054	40054	29990	3	30033	80010	20	80000	20	240000	40053	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	16	44	0	1	80016	0	0	17	80002	16	44	14	1	0	5020	14	16	12	13	40051	80000	10	40055	40064	40055	40053	40055
80024	40047	300	1	1	1	1	0	0	17	1	0	0	0	40036	0	0	0	25	80010	10	80000	10	80000	50	1840004	0	1	49	36971	40064	40047	29987	3	30034	80010	20	80000	20	240000	40054	40054	1	1	80021	10	9	10	80000	10	80000	10	80014	14	44	0	1	80014	0	1	17	80000	16	44	14	0	0	5020	12	16	14	14	40051	80000	10	40055	40048	40053	40055	40053

STRH (register, sxtw)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations