Firestorm: MADD (32-bit) measurements

Code:

  madd w0, w0, w1, w2

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	3033	23	0	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	73	1	16	1	2	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	3	0	73	1	16	1	2	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	73	1	16	1	2	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	73	1	16	1	2	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	3	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	73	1	16	1	2	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	73	1	16	1	2	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	73	1	16	1	2	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	0	61	1922	25	1000	1000	1000	81440	1	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	73	1	16	1	2	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	82	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	2	0	73	1	16	1	2	2939	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	3	61	1922	25	1000	1000	1000	81440	0	40	3033	3033	2760	3	2891	1000	1000	3000	3033	380	1	1	1001	1000	0	0	0	73	1	16	1	2	2939	1000	1000	3034	3034	3034	3034	3034

Test 2: Latency 1->2

Code:

  madd w0, w0, w1, w2

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	225	480	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	183	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30346	30075	374	3	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30062	224	321	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	519	61	19922	25	10100	10100	10100	828940	1	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	744	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	411	61	19922	25	10100	10100	10138	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	393	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30077	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	432	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	96	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	402	61	19922	25	10100	10100	10100	828940	0	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30075	374	1	1	10201	100	99	100	10100	100	4	2	2	0	1060	710	1	16	1	2	29939	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	225	0	82	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	4	16	4	4	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	4	16	4	3	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	4	16	4	3	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	5	16	4	3	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	4	16	4	3	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	12	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10080	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	4	16	3	4	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	4	16	4	4	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	3	16	3	4	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	3	16	4	3	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	4	16	4	3	29939	10000	10010	30034	30034	30034	30034	30034

Test 3: Latency 1->3

Code:

  madd w0, w1, w0, w2

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	225	0	0	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	710	2	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	4	30	0	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28625	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	0	0	0	0	0	61	19922	25	10100	10100	10100	828940	49	26953	30033	30033	28610	3	28741	10100	10200	30200	30033	374	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	710	1	16	1	1	29939	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	1	1	1	0	0	0	2548	19790	263	10193	10212	10457	830178	49	27387	30509	30512	28771	44	29058	10498	10742	31804	30511	374	12	1	10201	100	99	100	10100	100	0	0	2	0	12010	4	0	873	1	106	2	1	30324	10112	10100	30511	30557	30509	30418	30555
10204	30544	228	1	1	11	12	1821	1056	0	3539	19790	155	10208	10211	10553	830181	49	27468	30557	30586	28787	57	29060	10527	10788	31510	30591	374	13	1	10201	100	99	100	10100	100	0	2	0	1	9178	2	0	852	3	81	2	3	30276	10113	10100	30554	30594	30428	30551	30553
10204	30558	229	0	0	12	7	1584	968	1	3545	19790	305	10227	10219	10529	830411	49	27478	30601	30378	28786	28	29062	10524	10710	32093	30336	374	13	1	10201	100	99	100	10100	100	4	2	3	0	12450	2	0	879	1	112	3	2	30323	10096	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	640	4	16	4	4	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	1	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	640	4	17	3	4	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	640	4	16	4	4	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	4	4	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	640	4	16	4	4	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	4	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	640	4	16	4	4	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	4	3	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	4	4	29939	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	19922	25	10010	10010	10010	828490	0	49	26953	30033	30033	28632	3	28763	10010	10020	30020	30033	380	1	1	10021	10	9	10	10010	10	0	0	0	0	640	4	16	4	3	29939	10000	10010	30034	30034	30034	30034	30034

Test 4: Latency 1->4

Code:

  madd w0, w1, w2, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10037	75	12	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	76	0	238	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	1	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	15	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	264	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10085	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	3	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	3	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	6	48	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038
10204	10037	75	0	618	25	10100	10100	10100	70498	0	49	6957	10037	10037	8714	3	8745	10100	10200	30200	10037	162	1	1	10201	100	99	100	10100	100	0	0	710	1	16	1	1	10033	10000	10100	10038	10038	10038	10038	10038

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10037	76	0	0	0	0	48	25	10010	10010	10010	70048	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	48	25	10010	10010	10010	70048	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	48	25	10056	10010	10010	70048	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	3	3	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	48	25	10010	10010	10010	70048	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	3	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	48	25	10010	10010	10010	70048	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	76	0	0	0	0	48	25	10010	10010	10010	70048	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	48	25	10010	10010	10010	70048	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	48	25	10010	10010	10010	70048	49	6957	10037	10037	8792	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	11	3	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	48	25	10010	10010	10010	70048	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	1	3	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038
10024	10037	75	0	0	0	0	48	25	10010	10010	10010	70048	49	6957	10037	10037	8736	3	8767	10010	10020	30020	10037	164	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	16	2	2	10033	10000	10010	10038	10038	10038	10038	10038

Test 5: throughput

Count: 8

Code:

  madd w0, w8, w9, w9
  madd w1, w8, w9, w9
  madd w2, w8, w9, w9
  madd w3, w8, w9, w9
  madd w4, w8, w9, w9
  madd w5, w8, w9, w9
  madd w6, w8, w9, w9
  madd w7, w8, w9, w9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80036	599	0	0	0	0	0	105	0	46	25	80100	80100	80100	400500	0	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	3	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	0	0	0	0	46	25	80100	80100	80100	400500	0	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	0	0	0	0	46	25	80100	80100	80100	400500	0	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	3	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	0	0	0	0	46	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	3	69993	80100	80240	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	0	0	0	0	0	46	25	80100	80100	80100	400500	0	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	1	16	1	1	80031	80021	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	0	0	36	0	46	25	80100	80100	80100	400500	0	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	1	16	1	1	80071	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	0	0	0	0	46	25	80100	80100	80100	400607	1	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	1	16	1	1	80071	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	0	0	0	0	0	46	25	80100	80100	80100	400500	0	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	0	0	0	0	46	25	80100	80100	80100	400500	0	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	0	0	0	0	0	67	25	80100	80100	80100	400500	1	49	76955	0	80035	80035	69964	3	69993	80100	80200	240200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	0	9	0	0	5110	1	16	1	1	80031	80000	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80035	599	1	0	1	0	0	0	0	0	1	49	25	80010	80010	80010	400157	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5022	0	0	15	16	0	15	15	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	1	0	1	0	0	0	0	0	1	49	25	80010	80010	80010	400050	0	1	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	189	0	0	5023	0	0	14	16	0	10	16	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	1	0	1	0	0	0	0	0	1	49	25	80010	80010	80010	400050	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5022	0	0	16	16	0	13	15	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	1	0	1	0	0	0	9	0	1	49	25	80010	80010	80010	400050	0	1	49	76955	80035	80035	69986	7	70048	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	59	0	0	0	0	5022	0	0	15	16	0	12	10	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	1	0	1	0	0	0	0	0	1	220	25	80010	80010	80010	400050	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5022	0	0	13	16	0	14	11	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	1	0	1	0	0	0	0	0	1	49	25	80010	80010	80010	400050	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5022	0	0	14	16	0	13	12	80032	80000	80010	80036	80036	80036	80036	80036
80024	80074	600	1	0	1	0	0	0	0	0	1	714	25	80010	80010	80010	400050	0	1	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5022	0	0	13	16	0	14	9	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	1	0	1	0	0	0	0	0	1	714	25	80010	80010	80010	400050	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5023	0	0	15	16	0	11	9	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	1	0	1	0	0	0	0	0	2	49	25	80010	80010	80010	400050	0	1	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5022	0	0	15	16	0	16	10	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	1	0	1	0	0	0	0	0	2	49	25	80010	80010	80010	400050	0	0	49	76955	80035	80035	69986	3	70015	80010	80020	240020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5023	0	0	14	16	0	15	14	80032	80000	80010	80036	80036	80036	80036	80036

MADD (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations