Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STADDB

Test 1: uops

Code:

  staddb w0, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 70 nops): 3.000

Issues: 3.005

Integer unit issues: 1.004

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)0e0f1e1f2223243a3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f6061696a6d6emap rewind (75)map stall (76)dispatch uop (78)79map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d1d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
73005341332552110100100710005303338722203330011002200110002000109471686400049309373382434151310300011000200020004000339972679117100110001000020024311003100100420001122211511410668080053544522413936114444114249331991004190751695217720200010003401034066340883396034003
73004340462550101100100911005326339122207630051001200010002000109801683030049310323378134026310300001000200020004000339862676117100110001000020024201004100100320023122211493010625180203550452410736044436104538329881002190971666217519200010003395834111340513409934002
7300434056254010100010051000528833879219953005100420001000200010976168916004930959338373407431030000100020002000400033979267711710011000100002003302100410010132000312221150011060707996356548242103603445294437329791004189701651417617200010003413334156340813408134138
7300434070255110110010081000527433862221063002100220001000200010921168331004930965338283411131030000100020002000400033976267011710011000100002003322100610010232001310222148861064507966361745241953582444653845329831002189941680817589200010003403834062341133407134020
73004340012561101100100210005311338752204530011003200110002000109761690120049309563388234046310300011000200020004000340402640117100110001000020044201005100100220004100211489810628079603554452420635234445134641329201005192551675017683200010003404934008341033409334054
7300434110256010000010051000530934016219923002100220001000200010978168240004927615338133400731030000100020002000400033991266111710011000100002004322100410010232000111222150231050607932355846241333574444094636329701002188511659117571200010003415734032341693413234088
73004340312550101000100011005297338872203230051004200010002000110061690031049309793378034125310300001000200020004000340342669117100110001000020053201001100102320002100221502810773080043555412414535374447104637329621005191921678817574200010003403634042340253398233994
73004340712551101000100610005360338792202630051005200010002000110001692340049309643380634112310300011000200020004000339522661117100110001000020033021004100101320022122201503610659080663591512407035984445145340330781005190761685417694200010003408634092340793413834073
73004340572540100100100410005274339032209230021002200010002000110111697930049310193378934046310300001000200020004000339922650117100110001000020042221006100101720014122221511410681079923576402414535584441104443329231004190571669817760200010003400134045340473406734058
73004340852550101010100410005399338922215030051005200010002000110071690400049309423380534046310300001000200020004000339072644117100110001000120044221004100101320032122221503410616079953583462417235544444104849328971005190701663017648200010003402034053340223410234070

Test 2: throughput

Code:

  staddb w0, [x6]
  add x6, x6, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0071

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2022233a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9e9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
40206300752251030000034209231011030050414142012954254037520414200002010020000912241141302602534926985300723006524820325033401002020020000302004000030075611120201100991001000010100100000010020052199947010058100111243106720078123125119817013101171130068203399920000201003007230072300723007230072
40204300712252202000034331421101028300561671928129692540429204432000020100200009122471412824026049269913006830071248143250284010020200200003020040000300716711202011009910010000101001000000100200411619542010059100141029186820053140124614116013101161130078203469920000201003007230072300723007230072
4020430058225202200003409163810150300561911814129192540386203982000020100200009124051412832124349269783005530071248163250294010020200200003020040000300716411202011009910010000101001000000100200451913567010085100133338306220056136146920217213101161130068203689920000201003007230072300723007230072
4020430071225220000003440135210180300563522014129482540409203952000020100200009123831412795124749269913006830071248143250284010020200200003020040000300716511202011009910010000101001000000100200471915180010080100201355124720080136155815117013101161130084203410920000201003007230072300723005930072
40204300712252222000033921423102420300502241516129312540416204352000020100200009125851412445026249269953007530075248183250334010020200200003020040000300756111202011009910010000101001000000100200334197800100461001502842438200681277411723013101161130068203049920000201003007230072300723007230072
4020430071225202200003425152010200300562911212129362540432204682000020100200009123841412791023249269913006830071248133250294010020200200003020040000300716511202011009910010000101001000000100200611717262010078100124352189020072141155012517213101161130068203050920000201003007230072300723007230072
402043007122522221000341014291015030056272111412929254046020454200002010020000912394141269512554926991300683005824814325029401002020020000302004000030071641120201100991001000010100100000010020035172049401007410016422808020079238134810016413101171130068203140920000201003007630072300723007230072
4020430071225200000003413172910200300562141913129542540655204872000020100200009125781412764126049269913006830071248163250284010020200200003020040000300716511202011009910010000101001000000100200371625152010075100153234225620067122124417417213101171130068203349920000201003007230072300723007230072
4020430071225222200003434124610160300563451413129212540446204462000020100200009128231412752126749269913007130071248143250294010020200200003020040000300716511202011009910010000101001000000100200492024862010073100161326205420029141145812716413101161130068202839920000201003007230059300723007230072
4020430071225202200003403142220150300562331814129272540420204412000020100200009124311412810024949269913007130071248143250284010020200200003020040000300716711202011009910010000101001000000100200362116560010093100161325126320050140124213017213101161130068203219920000201003005930072300723007230072

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0075

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f181e1f202223293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
40026300712251111000339745510025443006032142181288325403642033520000200102000091219414125560023749269953007230075248433250324001020020200003002040000300756111200211091010000100101000010200490176741005810014214583320053029254167000127061601230068203579920000200103007630076300763007630076
40024300752250000100340325110241403006030227231291325403082029120000200102000091160314128950024149269953007230075248423250554001020020200003002040000300756111200211091010000100101000010200390225801007110003212264320052135456135000127031702230072202836620000200103007630076300763005330076
400243007522600000003449521000192430060331121312940254037920422200002001020000911635141282200232492699130209300712483632505140010200202000030020400003007165112002110910100001001010000102003714209561009710019114516582008621912701831401127031612230083203379620000200103007630076300763007630070
40024300752250000000337313110092030060274181512939254035220315200002001020000911918141277600234492699130071300712483832505140010200202000030020400003007165112002110910100001001010000102006414181661007410019424224732007514312782801400127011603330068203439920000200103007230072300723007230072
4002430071225111000034141533100200300600125121290625403362035420000200102000091182314128270022349269913006830071248353250514001020020200003002040000300716511200211091010000100101000010200501517471100841003721240108200663529512291410127021601130068203259920000200103007230072300723007230072
400243007122510110003390112510018030060371132012866254032920321200002001020000912051141291700234492699130068300712483732505140010200202000030020400003007167112002110910100001001010000102003701966610079100043163464220047121452196000127011601230072203109620000200103007630066300763007630076
40024300752250000000340444000021030050294171312946254033320337200002001020000911865141192900238492699530075300752484132505540010200202000030020400003007561112002110910100001001010000102003601485410128100130138364520039132450194000127031502230072203126620000200103007630076300763007630076
400243007522500000003410239100114030060494131912939254037120351200002001020000912000141300100251492698530075300752481832505540010200202000030020400003007562112002110910100001001010000102003401645410050100022156303920059126354118000127031602230072203316620000200103007630066300763007630076
4002430065226000000034104381002203003736216171290925403432032220000200102000091190714128940023149269853006530075248433250554001020020200003002040000300755711200211091010000100101000010200450204741006310006413466020079133446177000127021602230082202706620000200103007630076300763007630053
400243007522500000003385365100183630060342192512937254036120325200002001020000911457141295400232492699530072300522484132505540010200202000030020400003007561112002110910100001001010000102002801407710073100064148145220048027382150000127021601230062203320620000200103007630076301753007630076

Test 3: throughput

Code:

  staddb w0, [x6]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.2386

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
302051117818251010000203111510210210461617848572542809207972062910100200004338755487442702384910209610657510610910179813987503010010911052102032000520206400091016774771110201100990100100001001000001002002627354518847100150210096303029125152534240111716480160010143220196520132000010100103678105090106211104275102387
3020410454278210100002002014102103469901883604254074020415208881010020000408144947275961127499979510511210596910127369685730100124510321020320005202064000910077746111102011009901001000010010000010020026243153206521001401104903125611217142727250111716230160010403916214780132000010100105439104869104286104431104346
302041014897721110000206211610110332591718840972540733196872071710100200004669298493134001824910155310288710217297747698007301009241273102002000020200400009932850111102011009901001000010010000010020025260431967010015011074430842939815253626011172251224221029011720713130200001010098071100311101964102207103227
3020410361978011000002110715103105325717168669425409942179520351101002000043920974885594013849965141027161028449618369706930100122812161020020000202004000095986572111020110099010010000100100000100200202230341806010014001003830724905314233425111172224225229957744183071302000010100999799950597509100468103217
30204103621782111000018078150021007637015831892540011200812041610100200004306304482188501834994017976669799395578694264301001213734102002000020200400001022894931110201100990100100001001000001002002628354924355100160211048297591009414002301117222522422104652719976131320000101009997199312100052102989104895
30204986757221110000200171401296759001681936254078219997208401010020000435002049311170126499722610319110356210159869960130100823858102002000020200400001049184921110201100990100100001001000001002002422274218123100150190182996814065152630232111722462252296518181885813132000010100100799101574100771100485104041
30204105231784111000020263150121031839141678777254315319504206241010020000415988647950300245491023561028861027799850869830130100888589102002000020200400001051739201110201100990100100001001000001002002726333918616100150297512930994071523342221117222422422956902519472013200001010010142610012599051100124103138
3020410649778711100001895215003100309413158023425411251968020789101002000040611504713592014949957341014381005409775169827030100112378710200200002020040000101385518111020110099010010000100100000100200252432441959610016001148331124102281523023111172247225241024562720080131320000101001000399857998076100302100720
30204101822769111000020047150121011560171785281253981421177201231010020000491292550224130125499908910416210409710265269882030100146714651020020000202004000010155947811102011009901001000010010000010020022223646194021001570984129263976415283525111172247224221045049207651302000010100103655105381105241107108102751
3020410254476711100001911814014105693901882006254054319969206551010020000448223549208630207491001491047921043519907469475630100170916441020020000202004000010378249511102011009901001000010010000010020023233442185921001402947328814980915290251111722452252210463328206261313200001010010000599627970399566996452

1000 unrolls and 10 iterations

Result (median cycles for code): 11.1696

retire uop (01)cycle (02)03mmu table walk data (08)090e0f181e1f2223243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)branch mispred nonspec (cb)cfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
300261119318370000022322110001118083151491980254712025535200661001020000550828253305250101349108724111740111912107461310786730010293410020200002002040000111793531111002110924340101000010100000102000031002226910001001396933901144880253106401831622111293124333062000010010111934111882111855111536111820
300241114978350010021913161000111356201491752254501626116200181001020000545553153130450112849108629111555111611107416310799530010268100202000020020400001116765241110021109265061010000101000001020092272802442710001001489032670149691252706402121622111372225324602000010010111780111965111820112040111790
30024111910837001102339811000111770214092051254391624816200091001020000548682653318880110949108553111602111693107125310799430010283410020200002002040000111503412111002110925647101000010100000102000027260241381000100131763326214457102706401321622111432125351662000010010111397111548111610111695111510
3002411181583700000248511500001116053141392079254474025337201311001020000548437353375290100549108488111779111687107325310769330010301410020200002002040226111581522111002110928219101000010100000102000031002339210001001249132775139041262706401721622111304425728002000010010111677111675111589111956111677
3002411193183700000225121000011145500091496254475026442200441001020000546327453231680110649108648111890111799107432310785530010293310020200002002040000111665535111002110923369101000010100000102000031002422610000001268632181113901027064018216221114114240956102000010010111709111839111757111796111745
300241115688350000024974161001111539215159159825434932571620030100102000054750275315884010004910869311143811157510737631077813001029371002020000200204000011144249621100211092337610100001010000010200002726023059100010011431346491540610006400216221112482236081062000010010111960111840111718111772111768
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