Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DSB (ISH)

Test 1: uops

Code:

  dsb ish

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4151schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)inst barrier (9c)st unit uop (a7)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
100417032127017017015801100010001000600004913952148591703231689010001000170321703211100110001000073216111683810001703317033170331703317033
100417032128017017015801100010001000600004913952148591703231689010001000170321703211100110001000073116111683810001703317033170331703317033
100417032127017017015801100010001000600004913952148591703231689010001000170321703211100110001000073116111683810001703317033170731703317033
100417032127017017015801100010001000600004913952148591707931689010001000170321703211100110001000073116111683810001703317033170331703317033
100417032128017017015801100010001000600004913952148591703231689010001000170321703211100110001000073116111683810001703317033170331703317033
100417032128017017015801100010001000600014913952148591703231689010001000170321703211100110001000073116111683810001703317033170331703317033
100417032127017017015801100010001000600004913952148591703231689010001000170321703211100110001000073116111683810001703317033170331703317033
100417032128017017015801100010001000600004913952148591703231689010001000170321703211100110001000073116111683810001703317033170331703317033
100417032127017017015801100010001000600004913952148591703231689010001000170321703211100110001000073116111683810001703317033170331703317033
100417032128017017015801100010001000600004913952148591703231689010001000170321703211100110001000073116111683810001703317033170331703317033

Test 2: throughput

Code:

  dsb ish

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 17.0032

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4b51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fst unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
1020417003212740000017001711597001010010010000100100005005980014916695201509391700323168740101002001000020017003213591911102011009910010010000100100000000071011611169838010000100170033170033170033170033170033
1020417003212740000017001711597001010010010000100100005005980014916695201509351700323168740101002001000020017003213591911102011009910010010000100100000000071011611169838010000100170033170033170033170033170033
1020417003212730000017001701597001010010010000100100005005980014916695201509351700323168740101002001000020017003213591911102011009910010010000100100000000071011611169838010000100170033170055170033170033170033
1020417003212740006017001701597001010010010000100100005005980014916695201509351700323168757101002001000020017003213591911102011009910010010000100100000000071011611169838010000100170033170033170033170033170033
10204170032127400036017001701597001010010010000100100005005980014916695201509351700323168740101002001000020017003213591911102011009910010010000100100000000071011611169838010000100170033170033170033170033170033
1020417003212730000017001701597001010010010000100100005005980014916695201509351700323168740101002001000020017003213591911102011009910010010000100100000000071011611169838010000100170033170033170033170033170033
1020417003212730000017001701597001010010010000100100005005980014916695201509351700323168740101002001000020017003213591911102011009910010010000100100000004010093296141707502310000100171197171336171324171100171409
102041710341284134304335230417145301602941045612410419121103586156446514916878801528011716861351699541054020610414214170870170974231102011009910010010000100100000000071011611169838010000100170033170033170033170033170033
1020417003212730000017001701597001010010010000100100005005980014916695201509351700323168740101002001000020017003213591911102011009910010010000100100000000071001611169838010000100170033170033170033170033170033
1020417003212740000017001701597001010010010000100100005005980014916695201509351700323168740101002001000020017003213591911102011009910010010000100100000000071011611169838010000100170033170033170033170033170033

1000 unrolls and 10 iterations

Result (median cycles for code): 17.0032

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3a3f4151schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
10024170032127400001700170159786100101010000101000050599804916695214997717003231687621001020100002017003217005511100211091010100001001000000006405166616983801000010170033170033170033170033170033
10024170032127300001700170159786100101010000101000050599804916695215000417003231687621001020100002017003217003211100211091010100001001000000006406165516983801000010170033170033170033170033170033
10024170032127300001700170159716100101010013101000050599804916695215006717003231687621001020100002017003217003211100211091010100001001000000006405166616983801000010170033170033170033170033170033
10024170032127300001700170159786100101010000101000050599804916695214995717003231687621001020100002017003217003211100211091010100001001000000006405165516983801000010170033170033170033170033170033
10024170032127300001700170159786100101010000101000050599804916695214998517003231687621001020100002017003217003211100211091010100001001000000006406256616983801000010170033170033170033170033170033
10024170032127400001700170159786100101010000101000050599804916695214996317003291687621001020100002017003217003211100211091010100001001000000006406166516983801000010170033170033170033170033170033
10024170032127400001700170159786100101010000101000050599804916695214995717003231687621001020100002017003217003211100211091010100001001000000006405166516983801000010170033170033170033170033170033
10024170055127400001700170159786100101010000101000050599804916695214999117003231687621001020100002017003217003211100211091010100001001000000006405166516983801000010170033170033170033170033170033
10024170032127400001700170159786100101010000101000050599804916695215001517003231687621001020100002017003217003211100211091010100001001000000006406166516983801000010170033170033170033170033170033
10024170032127300001700170159786100101010000101000050599804916695214997817003231687621001020100002017003217003211100211091010100001001000000006406164616983801000010170033170033170033170033170033