Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

TST (register, lsr, 64-bit)

Test 1: uops

Code:

  tst x0, x1, lsr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)033f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
10047095611000304252000200010004087717097094982535611000100020007097811100110001073122116842000710710710710710
10047095611000304252000200010004087717097094982135611000100020007097811100110000073122116842000710710710710710
10047095611000304252000200010004087707097094982135611000100020007097811100110004073122116842000710710710710710
10047095611000304252000200010004087707097094982535611000100020007097811100110000073122116842000710710710710710
10047095611000304252000200010004087707097094982135611000100020007097811100110000073122116842000710710710710710
10047095611000304252000200010004087707097094982135611000100020007097811100110000073122116842000710710710710710
10047096611000304252000200010004087707097094982535611000100020007097811100110000073122116842000710710710710710
10047095611000304252000200010004087707097094982135611000100020007097811100110000073122116842000710710710710710
10047095611000304252000200010004087707097094982535611000100020007097811100110000073122116842000710710710710710
10047095611000304252000200010004087707097094982535611000100020007097811100110000073122116842000710710710710710

Test 2: Latency 3->1

Chain cycles: 1

Code:

  tst x0, x1, lsr #17
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)0318191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035225000023910000298992530100301002010719562401492695503003530035273916274872010720224302363003514511202011009910020100101000011113180116112998130000101003003630036300363003630036
202043003522500006110000298992530100301002010719562401492695503003530035273916274872010720224302363003514511202011009910020100101000011113180216112998130000101003003630036300363003630036
2020430035225003012610000298992530100301002010719562401492695503003530035273916274872010720224302363003514511202011009910020100101000011113180116212998130000101003003630036300363003630036
202043003522400006110000298992530100301002010719562401492695503003530035273916274872010720224302363003514511202011009910020100101000011113180116112998130000101003003630036300363003630036
202043003522500006110000298992530100301002010719562401492695503003530035273916274872010720224302363003514511202011009910020100101000011113180116112998130000101003003630036300363003630036
202043003522500006110000298992530100301002010719562401492695503003530035273916274872010720224302363003514511202011009910020100101000011113180116112998130000101003003630036300363003630036
202043003522500006110000298992530100301002010719562401492695503003530035273916274872010720224302363003514511202011009910020100101000011113180116112998130000101003003630036300363003630036
202043003522500006110000298992530100301002010719562401492695503003530035273916274872010720224302363003514511202011009910020100101000011113180116212998130000101003003630036300363003630036
202043003522500006110000298992530100301002010719562401492695503003530035273916274872010720224302363003514511202011009910020100101000011113180116112998130000101003003630036300363003630036
202043003522500006110000298992530100301002010719562401492695503003530035273916274872010720224302363003514511202011009910020100101000011113180116112998130000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)a9cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522508410000298912530010300102001019562890049269553003530035273913274982001020020300203003514511200211091020010100100001270233112995830000100103003630036300363003630036
2002430035225010710000298912530010300102001019562890149269553003530035273913274982001020020300203003514511200211091020010100100121270133112995830000100103003630036300363003630036
2002430035225014910000298912530010300102001019562890049269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
2002430035225016610000298912530010300102001019562890149269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
2002430035225020810000298912530010300102001019562890149269553003530035273913274982001020020300203003514511200211091020010100100101270133112995830000100103003630036300363003630036
200243003522408410000298912530010300102001019562890049269553003530035273913274982001020020300203003514511200211091020010100100011270233112995830000100103003630036300363003630036
2002430035225040010000298912530010300102001019562890149269553003530035273913274982001020020300203003514511200211091020010100100001270133212995830000100103003630036300363003630036
200243003522508410000298912530010300102001019562890049269553003530035273913274982001020020300203003514511200211091020010100100001270333112995830000100103003630036300363003630036
200243003522508410000298912530010300102001019562890049269553003530035273913274982001020020300203003514511200211091020010100100001270233112995830000100103003630036300363003630036
200243003522408410000298912530010300102001019562890149269553003530035273913275312001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  tst x0, x1, lsr #17
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204300352250000000611000029893253010030100201001956908492695503003530035273693274782010020200302003003514511202011009910020100101000000000013101131222995430000101003003630036300363003630036
20204300352240000000611000029893253010030100201001956198492695503003530035273693274782010020200302003003514511202011009910020100101000000000013101231222995430000101003003630036300363003630036
20204300352250000000611000029893253010030100201001956198492695503003530035273693274782010020200302003003514511202011009910020100101000000000013101231222995430000101003003630036300363003630036
202043003522500000006110000298932530100301002010019561984926955030035300352736932747820100202003020030035145112020110099100201001010000020210013101231222995430000101003003630036300363003630036
2020430035225000000061100002989325301003010020100195619849269550300353003527369327478201002020030200300351451120201100991002010010100000001470013101231222995430000101003003630036300363003630036
202043003522500000006110000298932530100301002010019561984926955030035300352736932747820100202003020030035145112020110099100201001010000000450013101231222995430000101003003630036300363003630036
20204300352250000000611000029893253010030100201001956198492695503003530035273693274782010020200302003003514511202011009910020100101000000000013101231322995430000101003003630036300363003630036
20204300352250000000611000029893253010030100201001956198492695503003530035273693274782010020200302003003514511202011009910020100101000000000013101331222995430000101003003630036300363003630036
202043003522500006001031000029897253010030100201001956198492695503003530035273693274782010020200302003003514511202011009910020100101000000000013101331222995430000101003003630036300363003630036
20204300352250000000611000029893253010030100201001956198492695503003530035273693274782010020200302003003514511202011009910020100101000000000013101231322995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024300352250001811000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
20024300352320003361000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
200243003522500016631000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100102001270133112995830000100103003630036300363003630036
2002430035225000841000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
2002430035224000611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270133212995830000100103003630036300363003630036
20024300352250001891000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
2002430035225000821000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
20024300352250001031000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
2002430035225000841000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
2002430035225000841000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036

Test 4: throughput

Count: 8

Code:

  tst x0, x1, lsr #17
  tst x0, x1, lsr #17
  tst x0, x1, lsr #17
  tst x0, x1, lsr #17
  tst x0, x1, lsr #17
  tst x0, x1, lsr #17
  tst x0, x1, lsr #17
  tst x0, x1, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802045345740006180000487412516010016010080100344000504950330053410534104329820633433608010080200160200534107811802011009910080100100000000511042422533921600001005341153411534115341153411
802045341040006180000487412516010016010080100344000504950330053410534104329820503433608010080200160200534107811802011009910080100100000000511022422533921600001005341153411534115341153411
802055341040006180000487412516010016010080100344000514950330053410534104329820633433608010080200160200534107811802011009910080100100000000511022422533921600001005341153411534115341153411
802045341040006180000487412516010016010080100344100314950330053410534104329820633433608010080200160200534107811802011009910080100100000000511022422533921600001005341153411534115341153411
802045341040006180000487412516010016010080100344000504950330053410534104329820503433608010080200160200534107811802011009910080100100000000511022422533921600001005341153411534115341153411
802045341040006180000487412516010016010080100344000504950330053410534104329820503433608010080200160200534107811802011009910080100100000000511022422533921600001005341153411534115341153411
802045341040006180000487412516010016010080100344000504950330053410534104329820633433608010080200160200534107811802011009910080100100000000511022422533921600001005341153411534115341153411
80204534104000618000048741251601001601008010034400051495033005341053410432982063343360801008020016020053410781180201100991008010010000023400511022422533921600001005341153411534115341153411
802045341040007268000048741251601001601008010034400051495033005341053410432982050343360801008020016020053410781180201100991008010010000023100511022422533921600001005341153411534115341153411
802045341040006180000487412516010016010080100344000504950330053410534104329820633433608010080200160200534107811802011009910080100100000000511022422533921600001005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800245338339900072680000479462516001016001080010343813014950300533805338043290256234335280010800201600205338078118002110910800101000005020012401153359160000105338153381533815338153381
80024533804000006180000479462516001016001080010343813014950300533805338043290270734335280010800201600205338078118002110910800101000005020012401153359160000105338153381533815338153381
80024533803990006180000479462516001016001080010343813004950300533805338043290270734335280010800201604285338078118002110910800101000005020012401153359160000105338153381533815338153381
800245338039900019180000479462516001016001080010343813004950300533805338043290256234335280010800201600205338078118002110910800101000005020012401153359160000105338153381533815338153381
80024533804000006180000479462516001016001080010343813004950300533805338043290256234335280010800201600205338078118002110910800101000005020012401153359160000105338153381533815338153381
800245338039900072680000479462516001016001080010343813004950300533805338043290270734335280010800201600205338078118002110910800101000005020012401153359160000105338153381533815338153381
80024533804000006180000479462516001016001080010343813004950300533805338043290256234335280010800201600205338078118002110910800101000005020012401153359160000105338153381533815338153381
800245338040000072680000479462516001016001080010343813004950300533805338043290270734335280010800201600205338078118002110910800101000005020012401153359160000105338153381533815338153381
800245338040000021080000479462516001016001080010343813004950300533805338043290270734335280010800201600205338078118002110910800101000005020012401153359160000105338153381533815338153381
80024533804000006180000479462516001016001080010343813004950300533805338043290270734335280010800201600205338078118002110910800101000005020012401153359160000105338153381533815338153381