Firestorm: CBZ (taken) measurements

Code:

  cbz x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	3842	5	0	35	25	1000	1000	1000	5000	0	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	5	21	3	3	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	3	21	4	3	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	3	21	3	3	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	3	21	3	3	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	3	21	3	3	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	3	21	3	3	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	3	21	3	3	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	3	21	3	3	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	3	21	3	3	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	1	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	3	21	3	3	532	536	536	536	536	536

Count: 8

Code:

  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4

Initialization

  mov x0, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0098

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80959	605	10	0	11	0	0	0	21	0	12	167	27	80105	80105	80107	400530	49	77694	80780	80776	6	10	80107	80207	80207	80788	64742	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	1	1	1	80759	434	703	309	336	80777	0	100	80787	80785	80781	80779	80781
80204	80774	605	9	0	9	0	0	0	0	0	12	811	27	80105	80105	80107	400530	49	77704	80782	80774	6	10	80107	80207	80207	80788	64744	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	1	1	1	80753	317	653	305	321	80775	0	100	80795	80799	80791	80791	80783
80204	80784	605	11	0	9	0	0	0	0	0	12	145	27	80105	80105	80107	400530	49	77700	80780	80780	6	10	80107	80207	80207	80784	64732	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	1	1	1	80763	324	653	306	324	80781	0	100	80787	80793	80787	80787	80787
80204	80786	605	9	0	9	0	0	0	0	0	12	145	27	80105	80105	80107	400530	49	77704	80782	80784	6	10	80107	80207	80207	80782	64738	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	1	1	1	80757	323	659	307	320	80791	0	100	80787	80787	80789	80789	80785
80204	80780	605	9	0	9	0	0	0	0	0	12	145	27	80105	80105	80107	400530	49	77704	80778	80774	6	10	80107	80207	80207	80804	64738	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	1	1	1	80761	322	675	305	319	80777	0	100	80807	80795	80801	80789	80791
80204	80804	605	10	0	9	0	0	0	0	0	12	170	27	80105	80105	80107	400530	49	77708	80792	80790	6	10	80107	80207	80207	80782	64746	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	1	1	1	80757	320	667	303	319	80779	0	100	80793	80789	80785	80787	81217
80204	80782	605	9	0	9	0	0	0	0	0	12	146	27	80105	80105	80107	400530	49	77704	80782	80784	6	26	80107	80207	80207	80782	64744	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	1	1	1	80771	326	669	310	331	80789	0	100	80783	80781	80787	80779	80783
80204	80774	605	9	0	9	0	0	0	0	0	12	145	27	80105	80105	80107	400530	49	77698	80780	80782	6	10	80107	80207	80207	80786	64736	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	1	1	1	80765	324	661	305	320	80779	0	100	80795	80785	80783	80783	80785
80204	80784	605	9	0	9	0	0	0	0	0	13	145	27	80105	80105	80107	400530	49	77716	80814	80784	6	10	80107	80207	80207	80780	81166	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	1	1	1	80765	322	661	308	320	80797	0	100	80791	80795	80787	80789	80791
80204	80788	605	9	0	9	0	0	0	0	0	12	145	27	80105	80105	80107	400530	49	77696	80774	80776	6	10	80107	80207	80207	80786	64736	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	1	1	1	80763	323	651	307	321	80777	0	100	80789	80789	80787	80787	80783

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	0f	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	239996	1799	0	0	0	0	0	0	0	0	2	6746	28	80011	80011	80012	400269	0	49	236962	0	240044	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240017	0	80003	160020	0	79990	80004	240041	0	0	10	240045	240051	240045	240045	240043
80024	240044	1798	2	0	5	0	0	0	0	0	2	65	28	80011	80011	80012	400058	0	49	236964	0	240044	240044	32	10	80012	80022	80022	240044	240042	1	1	80021	80010	80009	10	10	10	0	0	171	1	1	1	240021	0	80002	160016	0	79990	80003	240041	0	0	10	240043	240108	240045	240045	240045
80024	240044	1798	4	0	5	0	0	0	0	0	2	65	28	80011	80011	80012	400058	0	49	236964	0	240042	240044	6	10	80107	80022	80022	240042	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240021	0	80002	160016	0	79989	80002	240039	0	0	10	240045	240045	240045	240045	240045
80024	240044	1798	5	0	5	0	0	0	0	0	2	65	28	80011	80011	80012	400148	0	49	236964	0	240044	240044	6	10	80012	80073	80022	240042	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240021	0	80002	160016	0	79988	80003	240041	0	0	10	240045	240045	240045	240045	239946
80024	240044	1798	5	0	5	0	0	0	6	0	2	65	28	80011	80011	80012	400058	0	49	236964	0	240042	240044	6	10	80012	80022	80054	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240021	0	80002	160016	0	79995	80003	240043	0	0	10	240049	240049	240045	240047	240049
80025	240048	1798	0	0	0	0	0	0	0	0	2	80	28	80011	80011	80012	400058	0	49	236964	0	240044	240044	6	10	80053	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240021	4	80002	160014	0	79989	80003	240041	0	0	10	240043	240045	240045	240045	240045
80024	240044	1798	5	0	2	0	0	0	0	0	2	1118	28	80011	80011	80012	400058	0	49	236962	0	240044	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240021	0	80002	160014	0	79989	80003	240039	0	0	10	240045	240045	240045	240043	240045
80024	240044	1798	5	0	5	0	0	0	0	0	2	1160	28	80011	80011	80012	400058	0	49	236964	0	240044	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240021	0	80002	160016	0	79990	80003	240041	0	0	10	240045	240045	240043	240045	240043
80024	240044	1798	5	0	5	0	0	0	0	0	2	1118	28	80011	80011	80012	400058	0	49	236964	0	240042	240044	6	10	80012	80022	80022	240044	239916	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240019	0	80002	160016	0	79988	80003	240041	0	0	10	240045	240045	240043	240045	240043
80024	240044	1798	5	0	5	0	0	0	0	0	1	1181	28	80011	80011	80012	400058	0	49	236964	0	240044	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240021	0	80000	160016	0	79988	80003	240039	0	0	10	240043	240045	240045	239946	240043

CBZ (taken)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations