Firestorm: STRB (unsigned offset) measurements

Code:

  strb w0, [x6, #8]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	3	0	3	1	527	16	16	0	25	1000	1000	1000	22856	1	542	542	355	3	398	1000	1000	2000	549	542	1	1	1001	1000	1000	1000	34	1000	0	11	1002	2	34	73	2	16	2	2	539	1000	543	543	550	551	550
1004	542	4	0	3	0	527	16	0	3	25	1000	1000	1000	22808	0	540	540	355	3	400	1000	1000	2000	542	550	1	1	1001	1000	1000	1000	34	1002	0	21	1002	2	0	73	2	16	2	2	547	1000	543	543	543	541	543
1004	542	4	0	3	1	535	16	0	0	25	1000	1000	1000	22352	0	550	542	362	3	398	1000	1000	2000	549	542	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	34	73	2	16	2	2	546	1000	543	543	543	543	541
1004	542	4	0	0	1	527	0	16	0	25	1000	1000	1000	22424	0	540	550	353	3	408	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	1002	0	2	1000	2	0	73	2	16	2	2	539	1000	551	541	551	550	543
1004	542	4	3	6	1	527	0	0	0	25	1000	1000	1000	22352	0	550	542	353	3	400	1000	1000	2146	540	542	1	1	1001	1000	1000	1000	0	1002	0	0	1002	2	34	73	2	16	2	2	548	1000	541	543	543	543	541
1004	540	4	0	0	1	527	16	16	0	25	1000	1000	1000	22808	0	540	542	362	3	400	1000	1000	2000	540	540	1	1	1001	1000	1000	1000	34	1002	0	0	1002	2	34	73	2	16	2	2	539	1000	543	541	543	541	541
1004	542	4	0	9	1	535	16	16	0	25	1000	1000	1000	22760	0	540	542	355	3	398	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	34	1002	0	0	1002	2	0	73	2	16	2	2	537	1000	543	541	543	552	541
1004	540	4	0	3	1	525	0	16	0	25	1000	1000	1000	22808	0	540	542	364	3	400	1000	1000	2000	540	542	1	1	1001	1000	1000	1000	34	1002	0	0	1002	0	0	73	2	16	2	2	537	1000	550	551	552	541	541
1004	542	4	0	3	1	525	16	0	0	25	1000	1000	1000	22424	0	542	540	353	3	400	1000	1000	2000	542	550	1	1	1001	1000	1000	1000	34	1002	0	5	1002	2	34	73	2	16	2	2	539	1000	541	543	543	543	543
1004	542	3	0	3	1	527	0	16	0	25	1000	1000	1000	22352	0	542	542	355	3	400	1000	1000	2000	542	550	1	1	1001	1000	1000	1000	34	1002	1	2	1002	2	34	73	2	16	2	2	539	1000	552	551	550	543	541

Count: 8

Code:

  strb w0, [x6, #8]
  strb w0, [x6, #8]
  strb w0, [x6, #8]
  strb w0, [x6, #8]
  strb w0, [x6, #8]
  strb w0, [x6, #8]
  strb w0, [x6, #8]
  strb w0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40051	300	0	0	0	0	40027	16	16	2	25	80100	100	80000	100	80000	500	1839352	49	36962	40040	40042	29955	3	29998	80100	200	80000	200	160000	40042	32003	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80000	1	0	80002	2	0	0	5110	1	16	1	1	40039	80000	100	40041	40460	40043	40043	40043
80204	40050	300	0	3	1	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839352	49	36962	40042	40040	29955	3	29998	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	11	80002	0	34	0	5110	1	16	1	1	40039	80000	100	40051	40041	40051	40043	40043
80204	40042	300	0	3	1	0	40036	16	16	0	25	80100	100	80000	100	80000	500	1839352	49	36970	40040	40042	29955	3	30008	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80002	0	0	80002	2	34	0	5110	1	16	1	1	40048	80000	100	40043	40041	40043	40041	40043
80204	40040	300	0	3	1	0	40027	16	16	0	25	80100	100	80000	100	80121	500	1839856	49	36960	40042	40042	29955	3	30000	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	0	80002	0	34	0	5110	1	16	1	1	40039	80000	100	40043	40041	40043	40050	40041
80204	40050	300	0	3	1	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839424	49	36962	40040	40042	29955	3	30007	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80000	0	2	80002	2	34	0	5110	1	16	1	1	40037	80000	100	40043	40043	40043	40041	40043
80204	40040	300	0	3	0	0	40025	16	0	0	25	80100	100	80000	100	80000	500	1839352	49	36962	40042	40040	29955	3	29998	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	2	80002	2	34	0	5110	1	16	1	1	40047	80000	100	40043	40043	40043	40043	40043
80204	40050	300	0	0	1	0	40025	16	16	0	25	80100	101	80000	100	80000	500	1839424	49	36962	40042	40040	29955	3	29998	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80000	0	0	80002	2	34	0	5110	1	16	1	1	40047	80000	100	40043	40041	40043	40041	40041
80204	40040	300	0	0	1	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839352	49	36960	40042	40042	29953	3	30009	80100	200	80000	200	160000	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80002	0	0	80002	2	34	0	5110	1	16	1	1	40039	80000	100	40052	40043	40051	40043	40041
80204	40040	300	0	3	1	0	40036	16	16	0	25	80100	100	80000	100	80000	500	1839352	49	36960	40042	40049	29955	3	30000	80246	200	80000	200	160000	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80002	0	2	80002	0	34	0	5110	1	16	1	1	40037	80000	100	40043	40043	40043	40043	40043
80204	40042	300	0	3	0	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839424	49	36962	40049	40042	29955	3	30000	80100	200	80000	200	160000	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	80000	0	0	80002	2	0	0	5110	1	16	1	1	40037	80000	100	40043	40043	40041	40050	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40040	300	0	0	0	1	40027	16	0	0	25	80010	10	80000	10	80000	50	1839424	1	49	36962	40040	40040	29975	3	30020	80010	20	80000	20	160000	40040	40049	1	1	80021	10	9	10	80000	10	80000	10	80000	34	0	80002	1	0	80002	2	34	5020	15	16	12	12	40039	0	80000	10	40041	40041	40041	40041	40043
80024	40040	300	0	0	9	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	49	36960	40040	40040	29977	3	30030	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	0	80002	0	5	80000	2	34	5020	7	16	12	12	40037	0	80000	10	40182	40051	40043	40041	40043
80024	40040	300	0	0	0	1	40035	0	16	0	25	80010	10	80000	10	80000	50	1839424	1	49	36971	40042	40042	29975	3	30022	80010	20	80000	20	160000	40040	40050	1	1	80021	10	9	10	80000	10	80000	10	80000	34	0	80002	0	0	80002	2	0	5020	14	16	11	13	40046	0	80000	10	40043	40050	40041	40041	40043
80024	40040	300	0	0	9	0	40027	16	16	0	25	80010	10	80000	12	80000	50	1839352	1	49	36962	40040	40042	29975	3	30020	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80002	0	0	80000	2	34	5020	8	16	9	10	40039	0	80000	10	40043	40041	40043	40052	40043
80024	40040	300	0	0	0	1	40035	16	0	0	25	80010	10	80000	10	80000	50	1839808	1	49	36969	40042	40050	29984	3	30022	80010	20	80000	20	160000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80000	0	0	80002	0	34	5020	14	16	11	7	40039	0	80000	10	40041	40052	40043	40051	40043
80024	40051	300	0	0	3	0	40027	0	0	0	25	80010	10	80000	10	80000	50	1839352	1	49	36962	40042	40042	29977	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	0	80002	0	2	80002	0	34	5020	11	16	13	11	40039	0	80000	10	40041	40041	40050	40043	40041
80024	40042	300	0	0	3	1	40034	0	0	0	25	80010	10	80000	10	80000	50	1839424	1	49	36962	40042	40042	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	0	80002	0	2	80002	2	34	5020	8	16	12	13	40047	0	80000	10	40182	40043	40043	40043	40043
80024	40042	300	0	0	3	1	40175	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	49	36960	40042	40042	29977	3	30031	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80000	0	2	80002	2	34	5020	10	16	10	11	40039	0	80000	10	40043	40043	40043	40043	40041
80024	40042	299	0	0	6	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839856	0	49	36960	40040	40042	29985	3	30020	80010	20	80000	20	160000	40051	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80002	0	0	80002	2	0	5020	8	16	11	13	40039	0	80000	10	40043	40041	40052	40043	40041
80024	40042	300	0	0	3	1	40034	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	49	36962	40040	40040	29977	3	30020	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	0	80002	0	2	80000	0	34	5020	11	16	12	13	40037	0	80000	10	40043	40041	40043	40041	40041

STRB (unsigned offset)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations