Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CCMN (register, 32-bit)

Test 1: uops

Code:

  ccmn w0, w1, #0, hi
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
1004103581006191725100010001000622500103510358053882100010003000103510411100110001000037332733990100010361036103610361036
1004103570006191725100010001000622501103510358053882100010003000103510411100110001000007332733990100010361036103610361036
1004103580006191725100010001000622501103510358053882100010003000103510411100110001000007332733990100010361036103610361036
1004103580006191725100010001000622501103510358053882100010003000103510411100110001000007332733990100010361036103610361036
1004103570006191725100010001000622501103510358053882100010003000103510411100110001000007332733990100010361036103610361036
1004103580006191725100010001000622500103510358053882100010003000103510411100110001000007332733990100010361036103610361036
1004103580006191725100010001000622501103510358053882100010003000103510411100110001000007332733990100010361036103610361036
1004103570006191725100010001000622500103510358053882100010003000103510411100110001000007332733990100010361036103610361036
1004103570006191725100010001000622500103510358053882100010003000103510411100110001000007332733990100010361036103610361036
1004103580006191725100010001000622501103510358053882100010003000103510411100110001000007332733990100010361036103610361036

Test 2: Latency 3->1

Chain cycles: 1

Code:

  ccmn w0, w1, #0, hi
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03181e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202042003515000611992625201002010020100129715049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036
202042003515000611992625201002010020100129715049169552003520035174063174812010020200403942003510411202011009910020100201000013101228221999220000101002003620036200362003620036
202042003515000611992625201002010020100129715049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036
202042003514900611992625201002010020100129715049169552003520035174063174812010020200402002003510411202011009910020100201001013101228221999220000101002003620036200362003620036
202042003515000611992625201002010020100129715049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036
202042003515000611992625201002010020100129715049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036
202042003515000611992625201002010020100129715049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036
202042003515000611992625201002010020100129715049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036
202042003515000611992625201002010020100129715049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036
202042003515000611992625201002010020100129715049169552003520035174063174812010020200402002003510411202011009910020100201000013101228221999220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024200351506611991825200102001020010129724714916955200352003517428317504200102002040020200351041120021109102001020010001270127111999520000100102003620036200362003620036
20024200351500991991825200102001020010129724704916955200352003517428317504200102002040020200351041120021109102001020010001270127111999520000100102003620036200362003620036
20024200351500611991825200102001020010129724714916955200352003517428317504200102002040020200351041120021109102001020010001270127111999520000100102003620036200362003620036
20024200351500611991825200102001020010129724704916955201692003517428317504200102002040020200351041120021109102001020010001270127111999520000100102003620036200362003620036
20024200351500611991825200102001020010129724714916955200352003517428317504200102002040020200351041120021109102001020010001270127111999520000100102003620036200362003620036
200242003515012611991825200102001020010129724704916955200352003517428317504200102002040020200351041120021109102001020010001270127111999520000100102003620036200362003620036
20024200351500611991825200102001020010129724704916955200352003517428317504200102002040020200351041120021109102001020010001270127111999520000100102003620036200362003620036
20024200351500611991825200102001020010129724704916955200352003517428317504200102002040020200351041120021109102001020010201270127111999520000100102003620036200362003620036
20024200351500611991825200102001020010129724704916955200352003517428317504200102002040020200351041120021109102001020010001270127121999520000100102003620036200362003620036
200242003515007261991825200102001020010129724714916955200352003517428317504200102002040020200351041120021109102001020010001270127111999520000100102003620036200362003620036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  ccmn w0, w1, #0, hi
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9faccfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202042003515048611992625201002010020100129715014916955200352003517406317481201002020040200200351041120201100991002010020100013101228221999220000101002003620036200362003620036
2020420035150465611992625201002010020100129715014916955200352003517406317481201002020040200200351041120201100991002010020100013101228221999220000101002003620036200362003620036
202042003514915611992625201002013520100129715014916955200352003517406317481201002029740393200351041120201100991002010020100013101228221999220029101002003620036200362003620036
202042003515101561992625201002010020100129715014916955200352003517406317481201002020040200200351041120201100991002010020100013101228221999220000101002003620036200362003620036
20204200351500611992625201002010020100129715014916955200352003517406317481201002020040200200351041120201100991002010020100013101228221999220000101002003620036200362003620036
202042003515006119926252010020100201001297150149169552003520035174063174812010020200402002003510411202011009910020100201002413101228221999220000101002003620036200362003620036
20204200351500611992625201002010020100129715014916955200352003517406317481201002020040200200351041120201100991002010020100013101228221999220000101002003620036200362003620036
2020420035150294611992625201002010020100129715014916955200352003517406317481201002020040200200351041120201100991002010020100013101228221999220000101002003620036200362003620036
20204200351502735361992625201002010020100129715014916955200352003517406317481201002020040200200351041120201100991002010020100013101228221999220000101002003620036200362003620036
20204200351500611992625201002010020100129715014916955200352003517406317481201002020040200200351041120201100991002010020100013101228221999220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024200351500000000061199182520010200102001012972471491695520035200351742831750420010200204002020035104112002110910200102001000050001270127111999520000100102003620036200362003620036
20024200351500000000061199182520010200102001012972471491695520035200351742831750420010200204002020035104112002110910200102001000000301270127111999520000100102003620036200362003620036
20024200351500000000061199182520010200102001012972471491695520035200351742831750420010200204002020035104112002110910200102001000000301270127111999520000100102003620036200362003620036
20024200351500000000061199182520010200102001012972471491695520035200351742831750420010200204002020035104112002110910200102001000000301270127111999520000100102003620036200362003620036
20024200351500000000061199182520010200102001012972471491695520035200351742831750420010200204002020035104112002110910200102001000000001270127111999520000100102003620036200362003620036
20024200351500000000061199182520010200102001012972471491695520035200351742831750420010200204002020035104112002110910200102001000000001270127111999520000100102003620036200362003620036
20024200351500000000061199182520010200102001012972471491695520035200351742831750420010200204002020035104112002110910200102001000000001270127111999520000100102003620036200362003620036
20024200351500000000061199182520010200102001012972471491695520066200351742831750420010200204002020035104112002110910200102001000000301270127111999520000100102003620036200362003620036
20024200351500000000061199182520010200102001012972471491695520035200351742831750420010200204002020035104112002110910200102001000000001270127111999520000100102003620036200362003620036
20024200351500000000061199182520010200102001012972471491695520035201261742831750420010200204002020035104112002110910200102001000000001270127111999520000100102003620036200362003620036

Test 4: Latency 3->3

Code:

  ccmn w0, w1, #0, hi
  mov x0, 1
  mov x1, 2

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357500012008619920251020010200102006476521496955100351003586563873210200102003020010035110111020110099101001000000000000710127119990101001001003610036100361003610036
102041003575003000619920251020010200102006476521496955100351003586563873210200102003076810035110111020110099101001000000000000710127119990101001001003610036100361003610036
102041003575000000619920251020010200102846476521496955100351003586563873210200102003020010035110111020110099101001000000000000710127119990101001001003610036100361003610036
102041003575000000619920251020010200102006476521496955100351003586563873210200102003020010035110111020110099101001000000000000710127119990101001001003610036100361003610036
10204100357500000010559920251020010200102006476521496955100351003586563873210200102003020010035110111020110099101001000000000000710127119990101001001003610036100361003610036
10204100357500000011179920251020010200102006476521496955100351003586563873210200102003020010035110111020110099101001000000000000710127119990101001001003610036100361003610036
1020410035750000001689920251020010200102006476521496955100351003586563873210200102003020010035110111020110099101001000000000000710127119990101001001003610036100361003610036
1020410035750000001689920251020010200102006476521496955100351003586563873210200102003020010035110111020110099101001000000000000710127119990101001001003610036100361003610036
102041003575000000619920251020010200102006482801496955100351003586563873210200102003020010035110111020110099101001000000000000710127119990101001001003610036100361003610036
10204100357500000010689920251020010200102006476521496955100351003586563873210200102003020010035110111020110099101001000000000000710127119990101001001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024100357600000010399182510020100201002064729649695510035100358678387541002010020300201003510411100211091001010000000064042744999310010101003610036100361003610036
100241003575000000328991825100201002010020647296496955100351003586783875410020100203002010035104111002110910010100003200064042753999310010101003610036100361008110036
100241003578000008832499182510020100201002064729649695510035100358678387541002010020300201003510411100211091001010000000064042754999310010101003610036100361003610082
10024100797800000014999182510020100201002064729649695510035100358678387541002010020300201003510411100211091001010000000064032743999310010101003610036100361003610036
10024100357500000053299182510020100201002064729649695510035100358678387541002010020300201003510411100211091001010000000064042753999310010101003610036100361003610036
1002410035750000006199182510020100201002064729649695510035100358678387541002010020300201003510411100211091001010000000064032754999310010101003610036100361003610036
1002410035750000006199182510020100201002064729649695510035100358678387541002010020300201003510411100211091001010000000064042734999310054101003610036100361003610036
10024100357500000019199182510020100201002064729649695510035100358678387541002010020300201003510411100211091001010000000064042744999310010101003610036100361003610036
1002410035750000008499182510020100201002064729649695510035100358678387541002010020300201003510411100211091001010000000064042755999310010101003610036100361003610036
1002410035750000006199182510020100201002064729649695510035100358678387541002010020300201003510411100211091001010000000064032734999310010101003610036100361003610036

Test 5: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1602055342940021374616010016010016010010635880495032453404534043333903333591601001602002402005340466111602011009910016010080100001011021911534001600001005340553405534055340553405
1602045340440007022516010016010016010010635880495032453404534043333903333591601001602002402005340466111602011009910016010080100001011011911534001600001005340553405534055340553405
160204534044000372516010016010016010010635881495032453404534043333903333591601001602002402005340466111602011009910016010080100001011011911534401600001005340553405534055340553405
16020453404400667022516010016010016010010635880495032453404534043333903333591601001602002402005340466111602011009910016010080100001011011911534001600001005340553405534055340553405
160204534044000372516010016010016010010635881495032453404534043333903333591601001602002402005340466111602011009910016010080100001011011911534001600001005340553405534055340553405
160204534044000372516010016010016010010635880495032453404534043333903333591601001602002402005340466111602011009910016010080100001011011911534001600001005340553405534055340553405
160204534044000372516010016010016010010635880495032453404534043333903333591601001602002402005340466111602011009910016010080100001011011911534001600001005340553405534055340553405
160204534044000372516010016010016010010635881495032453404534043333903333591601001602002402005340466111602011009910016010080100001011011911534001600001005340553405534055340553405
160204534044000372516010016010016010010635880495032453404534043333903333591601001602002402005340466111602011009910016010080100001011011911534001600001005340553405534055340553405
160204534044000372516010016010016010010635880495032453404534043333903333591601001602002402005340466111602011009910016010080100001011011911534001600001005340553405534055340553405

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)l2 tlb miss data (0b)191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f6061696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? int retires (ef)f5f6f7f8fd
160024533904001000004325160010160012160010102938821549502945337453374333310333351160010160020240020533746611160021109101600108001086031002381142191113636533701600002111105337553375533755337553406
160024533744000000307082516001016001016001010293881154950294533745337433331033335116001016002024002053374661116002110910160010800100031002386137193113738533701600002111105337553375533755337553390
16002453374400000000432516001016001016001010293882154950294533745337433331033335116001016002024002053374661116002110910160010800100061002485138191124037533701600002111105337553375533755337553375
160024533744000000004325160010160010160010102938811549502945337453374333310333351160010160020240020533746611160021109101600108001000310024115126191113827533701600002111105337553375533755337553375
1600245337440000000043251600101600101600101029388115495029453374533743333103333491600101600202400205337466111600211091016001080010001591002285139191113730533701600002111105337553375533755337553375
1600245337440000000043251600101600101600101029388115495034353374533743333103333511600101600202400205337466111600211091016001080010780121002285140191113924533701600002111105337553375533755337553375
16002453374399000000432516001016001016001010293881154950294533745337433331033335116001016002024002053374661116002110910160010800100031002385138191113837533701600002111105337553375533755337553375
16002453374400000000555132160149160218160084102938811549502945337453756333700333351160010160020240020534696641160021109101600108001088461002385139191113837533701600002111105337553375533755337553375
16002453374400000000432516001016001016001010293881154950294533745337433331033335116001016002024002053374661116002110910160010800100031002285141191113838533701600002111105337553375533755337553375
160024533744000000004325160010160078160010102938811549502945337453374333310333351160010160020240020533746611160021109101600108001000331002285143191113940533701600002111105337553375533755337553375

Test 6: throughput

Count: 4

Code:

  fcmp s0, s0
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3353

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
50204134881010000087025501004010010000401001000057475780000113385134141341461302467371195010040200100001202002000013414134141150201100991004010010000401001332103191113411400001001341513415134151341513415
502041341410000000520025501004010010000401001000057475780000113385134141341461302467371195010040200100001202002000013414134141150201100991004010010000401000032101191113411400001001341513415134151341513415
5020413414100000002108025501004010010000401001000057475780000013385134141341461282467371195010040200100001202002000013414134141150201100991004010010000401000032101191113411400001001341513415134151341513415
50204134141000000066025501004010010000401001000057475780000113385134141341461302467371195010040200100001202002000013414134141150201100991004010010000401000032101192113411400001001341513415134151341513415
502041341410100000520025501004010010000401001000057475780000113385134141341461302467371195010040200100001202002000013414134141150201100991004010010000401000032101191113411400001001341513415134151341513415
502041341410000000245025501004010010000401001000057475780000113385134141341461302467371195010040200100001202002000013414134141150201100991004010010000401000032101191113411400001001341513415134151341513415
50204134141010000045025501004010010000401001000057475780000013385134141341461282456371195010040200100001202002000013414134141150201100991004010010000401000032101191113411400001001341513415134151341513415
502041341410000000340025501004010010000401001000057475780000013385134141341461282456371195010040200100001202002000013414134141150201100991004010010000401000032101191113411400001001341513415134151341513415
5020413414100000001245025501004010010000401001000057475780000113385134141341461302467371195010040200100001202002000013414134141150201100991004010010000401001332101191113411400001001341513415134151341513415
50204134141010000045025501004010010000401001000057475780000113385134141341461302467371195010040200100001202002000013414134141150201100991004010010000401000032101191113411400001001341513415134151341513415

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
50024133831010004502550010400101000040010100005734568000001335313382133825577379537109500104002010000120020200001338213382115002110910400101000040010000003140419111337940000101338313383133831338313383
50024133821000004502550010400101000040010100005734568000001335313382133825577378437109500104002010000120020200001338213382115002110910400101000040010000003140119111337940000101338313383133831338313383
500241338210000071002550010400101000040010100005734568000001335313382133825575378437109500104002010000120020200001338213382115002110910400101000040010000003140119111337940000101338313383133831349813383
50024133821000004502550010400101000040010100005734568000001335313382133825577378437109500104002010000120020200001338213382115002110910400101000040010003303140119111337940000101338313383133831338313383
50024133821000004502550010400101000040010100005734568000001335313382133825575379537109500104002010000120020200001338213382115002110910400101000040010000003140119111337940000101338313383133831338313383
50024133821000004502550010400101000040010100005734568000001335313382133825577379537109500104002010000120020200001338213382115002110910400101000040010000003140119111337940000101338313383133831338313383
50024133821010004502550010400101000040010100005734568000001335313382133825575378437109500104002010000120020200001338213382115002110910400101000040010000003140119111337940000101338313383133831338313383
50024133821000004502550010400101000040010100005734568000001335313382133825577379537109500104002010000120020200001338213382115002110910400101000040010000003140119111337940000101338313383133831338313383
50024133821000004502550010400101000040010100005734568000001335313382133825575379537109500104002010000120020200001338213382115002110910400101000040010000603140119111337940000101338313383133831338313383
50024133821000004502550010400101000040010100005734568000001335313382133825577378437109500104002010000120020200001338213382115002110910400101000040010001003140119111337940000101338313383133831338313383