Firestorm: CCMN (register, 32-bit) measurements

Code:

  ccmn w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	f5	f6	f7	f8	fd
1004	1035	8	1	0	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	3	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036

Test 2: Latency 3->1

Chain cycles: 1

Code:

  ccmn w0, w1, #0, hi
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297150	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297150	49	16955	20035	20035	17406	3	17481	20100	20200	40394	20035	104	1	1	20201	100	99	100	20100	20100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297150	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	149	0	0	61	19926	25	20100	20100	20100	1297150	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	1	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297150	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297150	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297150	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297150	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297150	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297150	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	6	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	99	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20169	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	12	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	2	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	1270	1	27	1	2	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	726	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  ccmn w0, w1, #0, hi
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	48	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	465	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	149	15	61	19926	25	20100	20135	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20297	40393	20035	104	1	1	20201	100	99	100	20100	20100	0	1310	1	2	28	2	2	19992	20029	10100	20036	20036	20036	20036	20036
20204	20035	151	0	156	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	24	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	294	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	273	536	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	40200	20035	104	1	1	20201	100	99	100	20100	20100	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	0	5	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	0	0	0	3	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	0	0	0	3	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	0	0	0	3	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20066	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	0	0	0	3	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20126	17428	3	17504	20010	20020	40020	20035	104	1	1	20021	10	9	10	20010	20010	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036

Test 4: Latency 3->3

Code:

  ccmn w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	12	0	0	861	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	30200	10035	110	1	1	10201	100	99	10100	10000	0	0	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	3	0	0	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	30768	10035	110	1	1	10201	100	99	10100	10000	0	0	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	0	61	9920	25	10200	10200	10284	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	30200	10035	110	1	1	10201	100	99	10100	10000	0	0	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	0	61	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	30200	10035	110	1	1	10201	100	99	10100	10000	0	0	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	0	1055	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	30200	10035	110	1	1	10201	100	99	10100	10000	0	0	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	0	1117	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	30200	10035	110	1	1	10201	100	99	10100	10000	0	0	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	0	168	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	30200	10035	110	1	1	10201	100	99	10100	10000	0	0	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	0	168	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	30200	10035	110	1	1	10201	100	99	10100	10000	0	0	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	0	61	9920	25	10200	10200	10200	648280	1	49	6955	10035	10035	8656	3	8732	10200	10200	30200	10035	110	1	1	10201	100	99	10100	10000	0	0	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	0	1068	9920	25	10200	10200	10200	647652	1	49	6955	10035	10035	8656	3	8732	10200	10200	30200	10035	110	1	1	10201	100	99	10100	10000	0	0	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	76	0	0	0	0	0	0	103	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	104	1	1	10021	10	9	10010	10000	0	0	0	0	640	4	27	4	4	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	0	328	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	104	1	1	10021	10	9	10010	10000	32	0	0	0	640	4	27	5	3	9993	10010	10	10036	10036	10036	10081	10036
10024	10035	78	0	0	0	0	0	88	324	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	104	1	1	10021	10	9	10010	10000	0	0	0	0	640	4	27	5	4	9993	10010	10	10036	10036	10036	10036	10082
10024	10079	78	0	0	0	0	0	0	149	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	104	1	1	10021	10	9	10010	10000	0	0	0	0	640	3	27	4	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	0	532	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	104	1	1	10021	10	9	10010	10000	0	0	0	0	640	4	27	5	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	104	1	1	10021	10	9	10010	10000	0	0	0	0	640	3	27	5	4	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	104	1	1	10021	10	9	10010	10000	0	0	0	0	640	4	27	3	4	9993	10054	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	0	191	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	104	1	1	10021	10	9	10010	10000	0	0	0	0	640	4	27	4	4	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	0	84	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	104	1	1	10021	10	9	10010	10000	0	0	0	0	640	4	27	5	5	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	104	1	1	10021	10	9	10010	10000	0	0	0	0	640	3	27	3	4	9993	10010	10	10036	10036	10036	10036	10036

Test 5: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmn w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160205	53429	400	21	37	46	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	240200	53404	66	1	1	160201	100	99	100	160100	80100	0	0	10110	2	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	702	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	240200	53404	66	1	1	160201	100	99	100	160100	80100	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	0	3	33359	160100	160200	240200	53404	66	1	1	160201	100	99	100	160100	80100	0	0	10110	1	19	1	1	53440	160000	100	53405	53405	53405	53405	53405
160204	53404	400	66	702	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	240200	53404	66	1	1	160201	100	99	100	160100	80100	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	0	3	33359	160100	160200	240200	53404	66	1	1	160201	100	99	100	160100	80100	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	240200	53404	66	1	1	160201	100	99	100	160100	80100	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	240200	53404	66	1	1	160201	100	99	100	160100	80100	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	0	3	33359	160100	160200	240200	53404	66	1	1	160201	100	99	100	160100	80100	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	240200	53404	66	1	1	160201	100	99	100	160100	80100	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	240200	53404	66	1	1	160201	100	99	100	160100	80100	0	0	10110	1	19	1	1	53400	160000	100	53405	53405	53405	53405	53405

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	61	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	53390	400	1	0	0	0	0	0	43	25	160010	160012	160010	1029388	2	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	240020	53374	66	1	1	160021	10	9	10	160010	80010	86	0	3	10023	8	1	1	42	19	1	1	1	36	36	53370	160000	21	11	10	53375	53375	53375	53375	53406
160024	53374	400	0	0	0	0	3	0	708	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	240020	53374	66	1	1	160021	10	9	10	160010	80010	0	0	3	10023	8	6	1	37	19	3	1	1	37	38	53370	160000	21	11	10	53375	53375	53375	53375	53390
160024	53374	400	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	2	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	240020	53374	66	1	1	160021	10	9	10	160010	80010	0	0	6	10024	8	5	1	38	19	1	1	2	40	37	53370	160000	21	11	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	240020	53374	66	1	1	160021	10	9	10	160010	80010	0	0	3	10024	11	5	1	26	19	1	1	1	38	27	53370	160000	21	11	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	0	3	33349	160010	160020	240020	53374	66	1	1	160021	10	9	10	160010	80010	0	0	159	10022	8	5	1	39	19	1	1	1	37	30	53370	160000	21	11	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	5	49	50343	53374	53374	33331	0	3	33351	160010	160020	240020	53374	66	1	1	160021	10	9	10	160010	80010	78	0	12	10022	8	5	1	40	19	1	1	1	39	24	53370	160000	21	11	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	240020	53374	66	1	1	160021	10	9	10	160010	80010	0	0	3	10023	8	5	1	38	19	1	1	1	38	37	53370	160000	21	11	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	555	132	160149	160218	160084	1029388	1	1	5	49	50294	53374	53756	33370	0	3	33351	160010	160020	240020	53469	66	4	1	160021	10	9	10	160010	80010	88	4	6	10023	8	5	1	39	19	1	1	1	38	37	53370	160000	21	11	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	240020	53374	66	1	1	160021	10	9	10	160010	80010	0	0	3	10022	8	5	1	41	19	1	1	1	38	38	53370	160000	21	11	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	43	25	160010	160078	160010	1029388	1	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	240020	53374	66	1	1	160021	10	9	10	160010	80010	0	0	33	10022	8	5	1	43	19	1	1	1	39	40	53370	160000	21	11	10	53375	53375	53375	53375	53375

Test 6: throughput

Count: 4

Code:

  fcmp s0, s0
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi
  ccmn w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3353

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50204	13488	101	0	0	0	0	0	87	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	120200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	40100	1	3	3210	3	19	1	1	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	0	0	0	0	520	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	120200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	40100	0	0	3210	1	19	1	1	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	0	0	0	0	2108	0	25	50100	40100	10000	40100	10000	574757	80000	0	13385	13414	13414	6128	2467	3	7119	50100	40200	10000	120200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	40100	0	0	3210	1	19	1	1	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	0	0	0	0	66	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	120200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	40100	0	0	3210	1	19	2	1	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	101	0	0	0	0	0	520	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	120200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	40100	0	0	3210	1	19	1	1	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	0	0	0	0	245	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	120200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	40100	0	0	3210	1	19	1	1	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	101	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574757	80000	0	13385	13414	13414	6128	2456	3	7119	50100	40200	10000	120200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	40100	0	0	3210	1	19	1	1	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	0	0	0	0	340	0	25	50100	40100	10000	40100	10000	574757	80000	0	13385	13414	13414	6128	2456	3	7119	50100	40200	10000	120200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	40100	0	0	3210	1	19	1	1	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	0	0	0	0	1245	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	120200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	40100	1	3	3210	1	19	1	1	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	101	0	0	0	0	0	45	0	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	120200	20000	13414	13414	1	1	50201	100	99	100	40100	10000	40100	0	0	3210	1	19	1	1	13411	40000	100	13415	13415	13415	13415	13415

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50024	13383	101	0	0	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3795	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	40010	0	0	0	0	0	3140	4	19	1	1	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3784	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	40010	0	0	0	0	0	3140	1	19	1	1	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	710	0	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5575	3784	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	40010	0	0	0	0	0	3140	1	19	1	1	13379	40000	10	13383	13383	13383	13498	13383
50024	13382	100	0	0	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3784	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	40010	0	0	3	3	0	3140	1	19	1	1	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5575	3795	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	40010	0	0	0	0	0	3140	1	19	1	1	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3795	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	40010	0	0	0	0	0	3140	1	19	1	1	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	101	0	0	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5575	3784	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	40010	0	0	0	0	0	3140	1	19	1	1	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3795	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	40010	0	0	0	0	0	3140	1	19	1	1	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5575	3795	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	40010	0	0	0	6	0	3140	1	19	1	1	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	45	0	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3784	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	40010	0	0	1	0	0	3140	1	19	1	1	13379	40000	10	13383	13383	13383	13383	13383

CCMN (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations