Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STR (register, lsl, 64-bit)

Test 1: uops

Code:

  str x0, [x6, x7, lsl #3]
  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int store (96)inst ldst (9b)l1d tlb access (a0)st unit uop (a7)acafcfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
100554240052525100010001000223521540540353339810001000300054054011100110001000100010000100073116115371000541541541541541
100454040052525100010001000223521540540353339810001000300054054011100110001000100010000100073116115371000541541541541541
100454040052525100010001000223521540540353339810001000300054054011100110001000100010000100073116115371000541541541541541
100454040052525100010001000223520540540353339810001000300054054011100110001000100010000100073116115371000541541541541541
100454040052525100010001000223521540540353339810001000300054054011100110001000100010000100073116115371000541541541541541
100454040052525100010001000223521540540353339810001000300054054011100110001000100010000100073116115371000541541541541541
100454040052525100010001000223521540540353339810001000300054054011100110001000100010000100073116115371000541541541541541
100454040052525100010001000223521540540353339810001000300054054011100110001000100010000100073116115371000541541541541541
100454040052525100010001000223520540540353339810001000300054054011100110001000100010000100073116115371000541541541541541
100454040052525100010001000223520540540353339810001000300054054011100110001000100010000100073116115371000541541541541541

Test 2: throughput

Count: 8

Code:

  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f22233a3f494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int store (96)inst int alu (97)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
802054004229900000000000040025002580100100800001008000650018393781493696040040400402995972999280106200800162002400484004031993118020110099100800001008000010080000000080000002800000000111511801600400370800001004004140041400414004140041
802044004029900000000140014003300258010010080000100800065001839378149369604004040040299597299928010620080016200240048400403199311802011009910080000100800001008000000008000000080000140141111511801600400450800001004004840048400484004840048
8020440047300100000057010040025095558010010080000100800065001839378149369674004740047299667299998010620080016200240048400473200011802011009910080000100800001008001614001800140114800000000111511801600400370800001004004140041400414004140041
8020440040300000000000000400250025801001008000010080006500183937814936960400404004029959729992801062008001620024004840040319931180201100991008000010080000100800000000800606500800000000111511801600400370800001004004140041400414004140041
802044004030000000000000040025002580100100800001008000650018393781493696040040400402995972999280106200800162002400484004031993118020110099100800001008000010080000000080000000800000000111511801600400370800001004004140041400414004140041
8020440040300000000001400140032002580100100800001008000650018397181493696040040400402995972999280106200800162002400484004031993118020110099100800001008000010080000000080000000800000000111511801600400370800001004004140041400414004140041
802044004030000000000000040025002580100100800001008000650018393781493696040040400402995972999280106200800162002400484004031993118020110099100800001008000010080000000080000000800000000111511801600400370800001004004140041400414004140041
8020440040299000000001400140032002580100100800001008000650018397181493696040040400402995910299878011220080022200240066400543200011802011009910080000100800001008001614000800140114800000000222512812311400370800001004004140041400414004140041
8020440040300000000001400040025002580100100800001008001250018393161493696040040400402995010299808011220080022200240066400403199311802011009910080000100800001008000000008000000080000140140222512812311400440800001004004940048400484004840048
802044004730000000000000040025002580100100800001008001250018393160493696740047400482995810299878011220080022200240066400473200011802011009910080000100800001008001516000800140114800000000222512812311400370800001004004140041400414004140041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)18191e1f3a3f4f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int store (96)inst int alu (97)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)a4st unit uop (a7)l1d cache writeback (a8)acafcfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
800254005730010006141400430258001010800001080000501839352493696040040400402997533002080010208000020240000400404004011800211091080000108000010800000080000115800005020316334003780000104004140041400414004140041
8002440040300000000040025025800101080000108011750183935249369604004040040299753300208001020800002024000040040400401180021109108000010800001080000008000000800005020216224003780000104004140041400414004140041
800244004030000000004002529525800101080000108000050183935249369604004040040299753300208044220800002024000040040400401180021109108000010800001080000008000000800005020241224003780000104004140041400414018140041
80024400403000000000400250258001010800001080000501839352493696040040400402997533002080010208000020240000400404004011800211091080000108000010800000080000012800005020416324003780000104004140041400414004140041
8002440040300000000040025025800101080000108000050183935249369604004040040299753300208001020800002024000040040400401180021109108000010800001080000008000003800005020316224003780000104004140041400414004140041
8002440040299000000040025025800101080000108000050183935249369604004040594299753300208001020800002024000040040400401180021109108000010800001080000008000000800005020316234003780000104004140041400414004140041
8002440040300000000040025025800101080000108000050183935249369604004040040299753300208001020800002024000040040400401180021109108000010800001080000008000000800005020216444003780000104004140041400414004140041
8002440040300000000040025025800101080000108000050183935249369604004040040299753300208001020800002024000040040400401180021109108000010800001080000008000000800005020348224003780000104004140041400414004140041
80024400403000000120040177025800101080000108000050183935249369604004040040299753300208001020800002024000040040400401180021109108000010800001080000008000010800005020216334003780000104004140041400414004140041
80024400403000000000400250145800101080000108000050183935249369604004040040299753300208001020800002024000040040400401180021109108000010800001080000008000000800005020216234003780000104004140041400414004140041