Firestorm: STR (register, lsl, 64-bit) measurements

Code:

  str x0, [x6, x7, lsl #3]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	st unit uop (a7)	ac	af	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	0	0	525	25	1000	1000	1000	22352	1	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	1	16	1	1	537	1000	541	541	541	541	541
1004	540	4	0	0	525	25	1000	1000	1000	22352	1	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	1	16	1	1	537	1000	541	541	541	541	541
1004	540	4	0	0	525	25	1000	1000	1000	22352	1	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	1	16	1	1	537	1000	541	541	541	541	541
1004	540	4	0	0	525	25	1000	1000	1000	22352	0	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	1	16	1	1	537	1000	541	541	541	541	541
1004	540	4	0	0	525	25	1000	1000	1000	22352	1	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	1	16	1	1	537	1000	541	541	541	541	541
1004	540	4	0	0	525	25	1000	1000	1000	22352	1	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	1	16	1	1	537	1000	541	541	541	541	541
1004	540	4	0	0	525	25	1000	1000	1000	22352	1	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	1	16	1	1	537	1000	541	541	541	541	541
1004	540	4	0	0	525	25	1000	1000	1000	22352	1	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	1	16	1	1	537	1000	541	541	541	541	541
1004	540	4	0	0	525	25	1000	1000	1000	22352	0	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	1	16	1	1	537	1000	541	541	541	541	541
1004	540	4	0	0	525	25	1000	1000	1000	22352	0	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	1	16	1	1	537	1000	541	541	541	541	541

Count: 8

Code:

  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]
  str x0, [x6, x7, lsl #3]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	299	0	0	0	0	0	0	0	0	0	0	0	0	40025	0	0	25	80100	100	80000	100	80006	500	1839378	1	49	36960	40040	40040	29959	7	29992	80106	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80000	0	0	2	80000	0	0	0	0	1	1	1	5118	0	16	0	0	40037	0	80000	100	40041	40041	40041	40041	40041
80204	40040	299	0	0	0	0	0	0	0	0	14	0	0	1	40033	0	0	25	80100	100	80000	100	80006	500	1839378	1	49	36960	40040	40040	29959	7	29992	80106	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80000	0	0	0	80000	14	0	14	1	1	1	1	5118	0	16	0	0	40045	0	80000	100	40048	40048	40048	40048	40048
80204	40047	300	1	0	0	0	0	0	0	57	0	1	0	0	40025	0	95	55	80100	100	80000	100	80006	500	1839378	1	49	36967	40047	40047	29966	7	29999	80106	200	80016	200	240048	40047	32000	1	1	80201	100	99	100	80000	100	80000	100	80016	14	0	0	1	80014	0	1	14	80000	0	0	0	0	1	1	1	5118	0	16	0	0	40037	0	80000	100	40041	40041	40041	40041	40041
80204	40040	300	0	0	0	0	0	0	0	0	0	0	0	0	40025	0	0	25	80100	100	80000	100	80006	500	1839378	1	49	36960	40040	40040	29959	7	29992	80106	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80060	65	0	0	80000	0	0	0	0	1	1	1	5118	0	16	0	0	40037	0	80000	100	40041	40041	40041	40041	40041
80204	40040	300	0	0	0	0	0	0	0	0	0	0	0	0	40025	0	0	25	80100	100	80000	100	80006	500	1839378	1	49	36960	40040	40040	29959	7	29992	80106	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80000	0	0	0	80000	0	0	0	0	1	1	1	5118	0	16	0	0	40037	0	80000	100	40041	40041	40041	40041	40041
80204	40040	300	0	0	0	0	0	0	0	0	14	0	0	1	40032	0	0	25	80100	100	80000	100	80006	500	1839718	1	49	36960	40040	40040	29959	7	29992	80106	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80000	0	0	0	80000	0	0	0	0	1	1	1	5118	0	16	0	0	40037	0	80000	100	40041	40041	40041	40041	40041
80204	40040	300	0	0	0	0	0	0	0	0	0	0	0	0	40025	0	0	25	80100	100	80000	100	80006	500	1839378	1	49	36960	40040	40040	29959	7	29992	80106	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80000	0	0	0	80000	0	0	0	0	1	1	1	5118	0	16	0	0	40037	0	80000	100	40041	40041	40041	40041	40041
80204	40040	299	0	0	0	0	0	0	0	0	14	0	0	1	40032	0	0	25	80100	100	80000	100	80006	500	1839718	1	49	36960	40040	40040	29959	10	29987	80112	200	80022	200	240066	40054	32000	1	1	80201	100	99	100	80000	100	80000	100	80016	14	0	0	0	80014	0	1	14	80000	0	0	0	0	2	2	2	5128	1	23	1	1	40037	0	80000	100	40041	40041	40041	40041	40041
80204	40040	300	0	0	0	0	0	0	0	0	14	0	0	0	40025	0	0	25	80100	100	80000	100	80012	500	1839316	1	49	36960	40040	40040	29950	10	29980	80112	200	80022	200	240066	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80000	0	0	0	80000	14	0	14	0	2	2	2	5128	1	23	1	1	40044	0	80000	100	40049	40048	40048	40048	40048
80204	40047	300	0	0	0	0	0	0	0	0	0	0	0	0	40025	0	0	25	80100	100	80000	100	80012	500	1839316	0	49	36967	40047	40048	29958	10	29987	80112	200	80022	200	240066	40047	32000	1	1	80201	100	99	100	80000	100	80000	100	80015	16	0	0	0	80014	0	1	14	80000	0	0	0	0	2	2	2	5128	1	23	1	1	40037	0	80000	100	40041	40041	40041	40041	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40057	300	1	0	0	0	6	14	1	40043	0	25	80010	10	80000	10	80000	50	1839352	49	36960	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80000	1	15	80000	5020	3	16	3	3	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	0	0	0	0	0	40025	0	25	80010	10	80000	10	80117	50	1839352	49	36960	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80000	0	0	80000	5020	2	16	2	2	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	0	0	0	0	0	40025	295	25	80010	10	80000	10	80000	50	1839352	49	36960	40040	40040	29975	3	30020	80442	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80000	0	0	80000	5020	2	41	2	2	40037	80000	10	40041	40041	40041	40181	40041
80024	40040	300	0	0	0	0	0	0	0	40025	0	25	80010	10	80000	10	80000	50	1839352	49	36960	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80000	0	12	80000	5020	4	16	3	2	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	0	0	0	0	0	40025	0	25	80010	10	80000	10	80000	50	1839352	49	36960	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80000	0	3	80000	5020	3	16	2	2	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	299	0	0	0	0	0	0	0	40025	0	25	80010	10	80000	10	80000	50	1839352	49	36960	40040	40594	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80000	0	0	80000	5020	3	16	2	3	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	0	0	0	0	0	40025	0	25	80010	10	80000	10	80000	50	1839352	49	36960	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80000	0	0	80000	5020	2	16	4	4	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	0	0	0	0	0	40025	0	25	80010	10	80000	10	80000	50	1839352	49	36960	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80000	0	0	80000	5020	3	48	2	2	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	0	0	12	0	0	40177	0	25	80010	10	80000	10	80000	50	1839352	49	36960	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80000	1	0	80000	5020	2	16	3	3	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	0	0	0	0	0	40025	0	145	80010	10	80000	10	80000	50	1839352	49	36960	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80000	0	0	80000	5020	2	16	2	3	40037	80000	10	40041	40041	40041	40041	40041

STR (register, lsl, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations