Firestorm: TBZ (not taken) measurements

Code:

  tbz x0, #1, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	3117	18	0	0	0	0	35	25	1000	1000	1000	5000	1	1956	1932	3	16	1000	1000	1000	2042	1952	1	1	1001	1000	1000	0	0	0	0	0	0	1818	638	968	518	479	2065	2085	1983	2001	2035	2007
1004	2002	15	0	0	0	0	35	25	1000	1000	1000	5000	1	1898	1990	3	18	1000	1000	1000	1882	1986	1	1	1001	1000	1000	0	0	0	0	0	0	1936	445	1048	465	522	1989	1997	2023	1863	2165	2011
1004	1976	15	0	0	0	0	35	25	1000	1000	1000	5000	1	2062	1966	3	18	1000	1000	1000	1864	2036	1	1	1001	1000	1000	0	0	0	0	0	0	1930	463	988	464	532	1963	2139	1989	1909	2059	2025
1004	1996	15	0	0	0	0	35	25	1000	1000	1000	5000	1	2058	2064	3	16	1000	1000	1000	1964	2094	1	1	1001	1000	1000	0	0	0	0	0	0	1952	502	944	512	443	1985	2075	1997	1865	2067	2023
1004	2010	15	0	0	0	0	35	25	1000	1000	1000	5000	1	2052	1994	3	18	1000	1000	1000	2054	1964	1	1	1001	1000	1000	0	0	0	0	0	0	1946	513	932	531	466	2069	1949	2011	2013	1845	1981
1004	1970	14	0	0	0	0	35	25	1000	1000	1000	5000	1	1970	1862	3	18	1000	1000	1000	1974	1986	1	1	1001	1000	1000	0	0	0	0	0	0	1924	477	968	499	467	1925	1951	2021	1985	1855	1987
1004	1948	15	0	0	0	0	35	25	1000	1000	1000	5000	1	1884	1962	3	18	1000	1000	1000	1962	1962	1	1	1001	1000	1000	0	0	0	0	0	0	1918	463	900	424	470	1929	2065	1965	2011	2013	2071
1004	1974	15	0	0	0	0	35	25	1000	1000	1000	5000	1	1946	2008	3	18	1000	1000	1000	1952	2020	1	1	1001	1000	1000	0	0	0	0	0	0	1922	452	1048	466	499	1877	1935	2007	2007	2035	2061
1004	1966	15	1	0	9	0	35	25	1000	1000	1000	5000	1	1970	2034	3	18	1000	1000	1000	2034	2010	1	1	1001	1000	1000	0	0	0	0	0	0	1920	426	942	475	510	2057	1945	2041	2061	1959	2051
1004	1972	16	0	0	0	0	35	25	1000	1000	1000	5000	1	1954	2036	3	18	1000	1000	1000	2158	1980	1	1	1001	1000	1000	0	0	0	0	0	0	1846	523	958	472	490	2055	1963	2013	1945	2027	1843

Count: 8

Code:

  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4

Initialization

  mov x0, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5013

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80204	40386	302	0	0	28	28	80110	80110	80114	400560	1	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	3	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	1	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40256
80204	40090	300	0	0	49	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40418	40091	40091	40091
80204	40090	300	0	0	28	28	80110	80110	80114	400560	1	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	0	28	28	80110	80110	80114	400560	1	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	0	598	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091
80205	40090	300	0	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	1	0	0	1	1	1	5118	0	16	0	0	40087	100	40091	40091	40091	40091	40091

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	42461	310	0	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	5021	20	20	14	15	40037	0	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	9	0	5021	17	20	15	17	40037	0	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	5021	9	20	9	16	40037	0	10	40053	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	5021	13	20	17	15	40037	0	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	12	0	5021	16	20	17	18	40037	0	10	40041	40041	40041	40041	40041
80024	40040	299	0	0	320	25	80010	80010	80010	400050	0	49	36960	40040	40094	13337	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	3	0	5021	19	20	19	17	40037	0	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	66	0	5021	18	20	14	17	40037	0	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	684	80010	80010	80010	400050	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	9	0	5021	17	20	14	15	40037	0	10	40041	40041	40041	40041	40041
80024	40040	299	0	12	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	105	0	5021	17	20	15	16	40037	0	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	35	25	80010	80010	80010	400050	1	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	117	0	5021	16	20	16	9	40037	0	10	40041	40041	40041	40041	40041

TBZ (not taken)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations