Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
strb w0, [x6, w7, sxtw]
mov x0, 0 mov x7, 8
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 1f | 22 | 23 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 60 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int store (96) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | f5 | f6 | f7 | f8 | fd |
| 1005 | 554 | 4 | 1 | 1 | 1 | 19 | 1 | 0 | 1 | 539 | 16 | 16 | 2 | 25 | 1000 | 1000 | 1000 | 23460 | 1 | 552 | 554 | 365 | 3 | 412 | 1000 | 1000 | 3000 | 552 | 554 | 1 | 1 | 1001 | 1000 | 1000 | 1015 | 16 | 44 | 0 | 1 | 1016 | 1 | 17 | 1002 | 16 | 44 | 14 | 2 | 73 | 2 | 16 | 1 | 1 | 549 | 1000 | 555 | 554 | 552 | 553 | 564 |
| 1004 | 563 | 4 | 1 | 1 | 1 | 17 | 0 | 0 | 1 | 537 | 16 | 16 | 2 | 25 | 1000 | 1000 | 1000 | 23028 | 1 | 554 | 554 | 377 | 3 | 411 | 1000 | 1000 | 3000 | 564 | 554 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 15 | 44 | 0 | 1 | 1016 | 0 | 17 | 1002 | 16 | 44 | 14 | 0 | 73 | 1 | 16 | 1 | 1 | 548 | 1000 | 555 | 553 | 552 | 564 | 564 |
| 1004 | 554 | 4 | 1 | 0 | 0 | 21 | 0 | 0 | 1 | 539 | 16 | 16 | 2 | 25 | 1000 | 1000 | 1000 | 22884 | 1 | 552 | 554 | 367 | 3 | 412 | 1000 | 1000 | 3000 | 552 | 554 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 15 | 44 | 0 | 1 | 1016 | 2 | 19 | 1002 | 16 | 44 | 14 | 1 | 73 | 1 | 16 | 1 | 1 | 548 | 1000 | 554 | 552 | 553 | 564 | 555 |
| 1004 | 555 | 4 | 1 | 1 | 0 | 19 | 0 | 0 | 1 | 539 | 16 | 16 | 1 | 25 | 1000 | 1000 | 1000 | 23508 | 0 | 554 | 552 | 367 | 3 | 410 | 1000 | 1000 | 3000 | 554 | 553 | 1 | 1 | 1001 | 1000 | 1000 | 1015 | 15 | 44 | 0 | 0 | 1016 | 1 | 16 | 1002 | 16 | 44 | 14 | 1 | 73 | 1 | 16 | 1 | 1 | 548 | 1000 | 555 | 555 | 554 | 553 | 553 |
| 1004 | 552 | 4 | 1 | 0 | 0 | 18 | 0 | 0 | 1 | 536 | 16 | 16 | 2 | 25 | 1000 | 1000 | 1000 | 23028 | 1 | 554 | 554 | 377 | 3 | 411 | 1000 | 1000 | 3000 | 564 | 554 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 16 | 44 | 0 | 1 | 1016 | 1 | 16 | 1002 | 16 | 44 | 14 | 0 | 73 | 1 | 16 | 1 | 1 | 551 | 1000 | 554 | 553 | 553 | 565 | 555 |
| 1004 | 554 | 4 | 1 | 1 | 1 | 17 | 0 | 0 | 1 | 539 | 16 | 16 | 6 | 25 | 1000 | 1000 | 1000 | 22908 | 1 | 552 | 555 | 367 | 3 | 412 | 1000 | 1000 | 3000 | 554 | 554 | 1 | 1 | 1001 | 1000 | 1000 | 1015 | 15 | 44 | 0 | 0 | 1016 | 1 | 18 | 1002 | 16 | 44 | 14 | 1 | 73 | 1 | 16 | 1 | 1 | 551 | 1000 | 555 | 555 | 555 | 555 | 554 |
| 1004 | 552 | 4 | 1 | 1 | 1 | 18 | 0 | 0 | 1 | 537 | 16 | 16 | 2 | 25 | 1000 | 1000 | 1000 | 23028 | 1 | 554 | 554 | 365 | 3 | 412 | 1000 | 1000 | 3000 | 552 | 554 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 14 | 44 | 0 | 1 | 1016 | 0 | 16 | 1002 | 16 | 44 | 14 | 1 | 73 | 1 | 16 | 1 | 1 | 551 | 1000 | 555 | 555 | 553 | 553 | 553 |
| 1004 | 563 | 4 | 1 | 0 | 1 | 19 | 0 | 0 | 1 | 537 | 16 | 16 | 1 | 25 | 1000 | 1000 | 1000 | 23028 | 1 | 554 | 553 | 367 | 3 | 410 | 1000 | 1000 | 3000 | 554 | 552 | 1 | 1 | 1001 | 1000 | 1000 | 1015 | 15 | 44 | 0 | 0 | 1016 | 0 | 18 | 1002 | 16 | 44 | 14 | 0 | 73 | 1 | 16 | 1 | 1 | 551 | 1000 | 555 | 554 | 552 | 553 | 564 |
| 1004 | 563 | 4 | 1 | 0 | 1 | 19 | 0 | 0 | 1 | 538 | 16 | 16 | 1 | 25 | 1000 | 1000 | 1000 | 23004 | 1 | 552 | 554 | 364 | 3 | 412 | 1000 | 1000 | 3000 | 551 | 554 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 15 | 44 | 0 | 0 | 1016 | 1 | 16 | 1002 | 16 | 44 | 14 | 1 | 73 | 1 | 16 | 1 | 1 | 549 | 1000 | 554 | 552 | 553 | 564 | 555 |
| 1004 | 554 | 4 | 1 | 1 | 1 | 17 | 0 | 0 | 1 | 539 | 16 | 16 | 1 | 25 | 1000 | 1000 | 1000 | 23439 | 1 | 552 | 554 | 366 | 3 | 412 | 1000 | 1000 | 3000 | 553 | 554 | 1 | 1 | 1001 | 1000 | 1000 | 1015 | 14 | 44 | 0 | 0 | 1016 | 0 | 20 | 1002 | 16 | 44 | 14 | 0 | 73 | 1 | 16 | 1 | 1 | 549 | 1000 | 553 | 552 | 564 | 555 | 555 |
Count: 8
Code:
strb w0, [x6, w7, sxtw] strb w0, [x6, w7, sxtw] strb w0, [x6, w7, sxtw] strb w0, [x6, w7, sxtw] strb w0, [x6, w7, sxtw] strb w0, [x6, w7, sxtw] strb w0, [x6, w7, sxtw] strb w0, [x6, w7, sxtw]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5007
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 19 | 1e | 1f | 22 | 23 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80205 | 40040 | 300 | 1 | 1 | 1 | 0 | 6 | 14 | 1 | 0 | 1 | 40044 | 0 | 16 | 300 | 25 | 80160 | 100 | 80000 | 100 | 80006 | 500 | 1839718 | 1 | 49 | 36972 | 0 | 40058 | 40050 | 29979 | 7 | 29999 | 80106 | 200 | 80016 | 200 | 240786 | 40059 | 32000 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80015 | 14 | 36 | 0 | 2 | 80016 | 0 | 1 | 18 | 80000 | 16 | 0 | 14 | 2 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40055 | 80000 | 100 | 40053 | 40059 | 40053 | 40049 | 40051 |
| 80204 | 40059 | 300 | 1 | 1 | 0 | 0 | 0 | 21 | 0 | 0 | 1 | 40035 | 16 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80006 | 500 | 1839814 | 0 | 49 | 36979 | 0 | 40052 | 40047 | 29966 | 7 | 30011 | 80107 | 200 | 80016 | 200 | 240048 | 40059 | 32012 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80016 | 15 | 0 | 0 | 1 | 80016 | 0 | 0 | 14 | 80000 | 16 | 0 | 14 | 1 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40057 | 80000 | 100 | 40058 | 40054 | 40048 | 40053 | 40059 |
| 80204 | 40052 | 300 | 1 | 1 | 0 | 0 | 0 | 17 | 1 | 0 | 1 | 40036 | 16 | 0 | 5 | 25 | 80100 | 100 | 80000 | 100 | 80006 | 500 | 1840246 | 1 | 49 | 36978 | 0 | 40052 | 40058 | 29978 | 7 | 30010 | 80106 | 200 | 80016 | 200 | 240048 | 40058 | 32011 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80014 | 16 | 0 | 0 | 2 | 80016 | 0 | 1 | 14 | 80002 | 16 | 0 | 14 | 1 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40058 | 80000 | 100 | 40054 | 40059 | 40053 | 40048 | 40053 |
| 80204 | 40057 | 300 | 1 | 0 | 0 | 0 | 0 | 19 | 1 | 0 | 1 | 40036 | 16 | 0 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80006 | 500 | 1840228 | 1 | 49 | 36969 | 0 | 40047 | 40058 | 29967 | 7 | 30003 | 80107 | 200 | 80016 | 200 | 240048 | 40048 | 32000 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80015 | 15 | 36 | 0 | 0 | 80016 | 0 | 1 | 14 | 80002 | 16 | 36 | 14 | 2 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40055 | 80000 | 100 | 40059 | 40053 | 40048 | 40054 | 40060 |
| 80204 | 40047 | 300 | 1 | 0 | 0 | 0 | 6 | 19 | 0 | 0 | 1 | 40043 | 16 | 16 | 5 | 25 | 80100 | 100 | 80000 | 100 | 80007 | 500 | 1839718 | 1 | 49 | 36978 | 0 | 40047 | 40047 | 29966 | 7 | 29999 | 80106 | 200 | 80016 | 200 | 240048 | 40052 | 32000 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80015 | 16 | 36 | 0 | 1 | 80014 | 0 | 1 | 14 | 80002 | 16 | 36 | 14 | 1 | 1 | 1 | 1 | 5118 | 0 | 17 | 0 | 0 | 40056 | 80000 | 100 | 40061 | 40048 | 40048 | 40059 | 40059 |
| 80204 | 40047 | 300 | 1 | 1 | 1 | 0 | 0 | 18 | 1 | 0 | 1 | 40042 | 0 | 0 | 7 | 25 | 80100 | 100 | 80000 | 100 | 80007 | 500 | 1839749 | 1 | 49 | 36980 | 0 | 40058 | 40048 | 29978 | 7 | 29999 | 80107 | 200 | 80016 | 200 | 240048 | 40058 | 32011 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80015 | 15 | 36 | 0 | 0 | 80016 | 0 | 1 | 18 | 80002 | 14 | 36 | 14 | 2 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40044 | 80000 | 100 | 40059 | 40051 | 40060 | 40052 | 40053 |
| 80204 | 40047 | 300 | 1 | 1 | 0 | 0 | 0 | 18 | 1 | 0 | 1 | 40044 | 0 | 0 | 5 | 25 | 80100 | 100 | 80000 | 100 | 80006 | 500 | 1840296 | 1 | 49 | 36980 | 0 | 40058 | 40059 | 29978 | 7 | 30002 | 80107 | 200 | 80016 | 200 | 240048 | 40058 | 32011 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80016 | 14 | 36 | 0 | 1 | 80016 | 0 | 1 | 19 | 80002 | 16 | 0 | 14 | 1 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 1 | 40060 | 80000 | 100 | 40048 | 40054 | 40049 | 40048 | 40048 |
| 80204 | 40047 | 300 | 1 | 1 | 0 | 0 | 0 | 19 | 1 | 0 | 1 | 40032 | 0 | 16 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80007 | 500 | 1839718 | 1 | 49 | 36977 | 0 | 40058 | 40058 | 29966 | 7 | 30012 | 80107 | 202 | 80016 | 200 | 240048 | 40047 | 32001 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80014 | 14 | 36 | 0 | 0 | 80016 | 0 | 1 | 14 | 80002 | 16 | 0 | 14 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40049 | 80000 | 100 | 40048 | 40059 | 40053 | 40049 | 40050 |
| 80204 | 40059 | 300 | 1 | 1 | 2 | 0 | 0 | 18 | 1 | 0 | 1 | 40043 | 16 | 0 | 5 | 25 | 80100 | 100 | 80000 | 100 | 80006 | 500 | 1839958 | 1 | 49 | 36972 | 0 | 40047 | 40051 | 29969 | 7 | 29999 | 80106 | 200 | 80016 | 200 | 240048 | 40060 | 32005 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80014 | 14 | 34 | 2 | 1 | 80016 | 0 | 0 | 17 | 80002 | 16 | 36 | 14 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40047 | 80000 | 100 | 40058 | 40053 | 40048 | 40053 | 40060 |
| 80204 | 40053 | 300 | 1 | 1 | 1 | 0 | 0 | 14 | 1 | 0 | 1 | 40044 | 16 | 15 | 5 | 25 | 80100 | 100 | 80000 | 100 | 80007 | 500 | 1840275 | 1 | 49 | 36979 | 0 | 40047 | 40059 | 29971 | 7 | 30011 | 80106 | 200 | 80016 | 200 | 240048 | 40052 | 32000 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80015 | 14 | 36 | 2 | 1 | 80014 | 0 | 2 | 14 | 80000 | 16 | 35 | 14 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40055 | 80000 | 100 | 40059 | 40050 | 40060 | 40052 | 40053 |
Result (median cycles for code divided by count): 0.5005
| retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | 18 | 1e | 1f | 22 | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d cache miss st (a2) | a4 | st unit uop (a7) | l1d cache writeback (a8) | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | cf | d0 | d2 | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | da | dd | fetch restart (de) | e0 | ea | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80025 | 40052 | 300 | 0 | 0 | 0 | 3 | 1 | 40025 | 16 | 16 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839352 | 49 | 36962 | 40050 | 40040 | 29975 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40042 | 40051 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 34 | 0 | 80002 | 0 | 2 | 80000 | 2 | 34 | 0 | 5020 | 0 | 0 | 0 | 17 | 16 | 0 | 17 | 31 | 40039 | 0 | 80000 | 10 | 40041 | 40041 | 40050 | 40043 | 40050 |
| 80024 | 40042 | 300 | 1 | 0 | 0 | 3 | 0 | 40036 | 16 | 16 | 2 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839856 | 49 | 36960 | 40042 | 40042 | 29977 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40042 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 34 | 0 | 80002 | 1 | 2 | 80002 | 0 | 34 | 0 | 5021 | 0 | 0 | 1 | 16 | 16 | 0 | 14 | 20 | 40037 | 0 | 80000 | 10 | 40052 | 40041 | 40041 | 40043 | 40043 |
| 80024 | 40042 | 300 | 1 | 0 | 0 | 9 | 1 | 40025 | 16 | 16 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839424 | 49 | 36962 | 40051 | 40050 | 29985 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40051 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 0 | 80002 | 0 | 2 | 80002 | 2 | 34 | 0 | 5020 | 0 | 0 | 0 | 16 | 16 | 0 | 17 | 13 | 40039 | 0 | 80000 | 10 | 40043 | 40043 | 40043 | 40043 | 40051 |
| 80024 | 40042 | 299 | 1 | 0 | 0 | 3 | 1 | 40025 | 16 | 16 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839424 | 49 | 36962 | 40049 | 40042 | 29975 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40042 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 0 | 80002 | 0 | 131 | 80002 | 2 | 34 | 0 | 5021 | 0 | 0 | 1 | 17 | 16 | 0 | 16 | 16 | 40047 | 0 | 80000 | 10 | 40043 | 40043 | 40041 | 40043 | 40043 |
| 80024 | 40042 | 300 | 1 | 0 | 0 | 9 | 0 | 40027 | 16 | 16 | 3 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839424 | 49 | 36960 | 40050 | 40040 | 29977 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40049 | 40040 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 34 | 0 | 80002 | 0 | 2 | 80002 | 2 | 0 | 0 | 5020 | 0 | 0 | 0 | 17 | 16 | 0 | 15 | 23 | 40037 | 0 | 80000 | 10 | 40043 | 40050 | 40043 | 40051 | 40041 |
| 80024 | 40042 | 300 | 1 | 0 | 0 | 0 | 1 | 40025 | 16 | 16 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839352 | 49 | 36960 | 40042 | 40040 | 29977 | 3 | 30020 | 80010 | 20 | 80000 | 20 | 240000 | 40042 | 40040 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 34 | 0 | 80002 | 0 | 0 | 80000 | 2 | 0 | 0 | 5021 | 0 | 0 | 1 | 17 | 16 | 0 | 14 | 14 | 40039 | 0 | 80000 | 10 | 40052 | 40043 | 40052 | 40043 | 40041 |
| 80024 | 40042 | 300 | 1 | 0 | 0 | 6 | 0 | 40035 | 16 | 16 | 2 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839760 | 49 | 36962 | 40042 | 40042 | 29977 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40042 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 34 | 0 | 80000 | 0 | 8 | 80002 | 0 | 34 | 0 | 5021 | 0 | 0 | 1 | 16 | 16 | 0 | 14 | 12 | 40042 | 0 | 80000 | 10 | 40043 | 40052 | 40041 | 40041 | 40043 |
| 80024 | 40042 | 299 | 1 | 0 | 0 | 0 | 0 | 40027 | 16 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839424 | 49 | 36962 | 40051 | 40042 | 29975 | 3 | 30020 | 80010 | 20 | 80000 | 20 | 240000 | 40050 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 0 | 80062 | 0 | 2 | 80000 | 2 | 34 | 0 | 5021 | 0 | 0 | 1 | 17 | 16 | 0 | 17 | 23 | 40042 | 0 | 80000 | 10 | 40041 | 40041 | 40043 | 40041 | 40052 |
| 80024 | 40042 | 300 | 1 | 0 | 0 | 3 | 0 | 40025 | 16 | 16 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839424 | 49 | 36962 | 40050 | 40042 | 29984 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40051 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 0 | 0 | 80000 | 1 | 0 | 80002 | 2 | 34 | 0 | 5021 | 0 | 0 | 1 | 17 | 16 | 0 | 15 | 13 | 40037 | 0 | 80000 | 10 | 40041 | 40043 | 40043 | 40043 | 40051 |
| 80024 | 40042 | 299 | 1 | 0 | 0 | 3 | 1 | 40025 | 16 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839424 | 49 | 36960 | 40042 | 40040 | 29985 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40040 | 40049 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80000 | 34 | 0 | 80002 | 0 | 0 | 80002 | 0 | 0 | 0 | 5021 | 0 | 0 | 1 | 18 | 16 | 0 | 18 | 34 | 40039 | 21 | 80000 | 10 | 40041 | 40043 | 40043 | 40043 | 40043 |