Firestorm: STR (pre-index, 64-bit) measurements

Code:

  str x0, [x6, #8]!

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1040	8	0	0	6	4	14	0	7	0	1025	7	7	0	2	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1016	0	40	2	27	1000	1	14	10	0	1012	0	31	73	4	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	4	24	1	5	0	1025	9	0	0	2	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1012	0	31	2	17	1000	0	14	6	0	1014	0	47	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	6	4	18	1	7	0	1025	27	6	0	3	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1024	0	55	3	25	1002	0	22	6	4	1020	0	31	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	12	4	16	0	0	0	1025	20	0	1	2	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1016	6	47	2	19	1001	0	0	6	0	1000	0	71	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	0	4	14	1	5	0	1025	9	5	1	3	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1014	0	47	2	14	1000	1	18	8	3	1000	0	31	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	5	0	0	6	24	1025	11	0	0	3	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1000	0	63	3	15	1012	0	18	14	3	1014	0	51	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	1	0	3	20	0	5	0	1025	9	5	6	3	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1000	0	47	2	9	1000	1	30	12	0	1014	0	31	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	4	16	1	5	20	1025	9	0	8	3	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1000	0	39	2	15	1003	0	0	0	0	1000	0	39	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	4	14	1	4	0	1025	8	0	0	2	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1012	0	31	3	17	1000	0	12	16	0	1016	0	31	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	24	4	0	0	7	0	1025	11	0	7	2	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1014	0	23	2	12	1000	0	14	12	0	1014	0	55	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 2->2

Code:

  str x0, [x6, #8]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10209	10040	75	4	4	0	2139	105	809	1	776	73	0	128	10025	803	89	88	54	25	20100	10100	10000	10106	10000	521991	468824	49	6960	10040	10040	8681	6	8743	20106	200	10008	200	20016	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10952	28	1649	374	0	686	10279	256	0	898	38	898	10914	40	1229	28	0	1	1	1	717	0	16	0	0	10037	10000	1	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	4	0	0	2202	124	788	1	720	93	0	156	10025	778	91	77	53	25	20100	10100	10000	10106	10000	522055	468824	49	6960	10040	10040	8681	7	8742	20106	200	10008	200	20016	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10926	24	1159	385	2	683	10279	286	0	898	42	903	10961	34	1173	21	0	1	1	1	718	0	16	0	0	10037	10000	4	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	3	0	0	2100	98	803	1	800	79	0	96	10025	792	83	89	46	25	20100	10100	10000	10106	10000	522093	468824	49	6960	10040	10040	8681	6	8742	20106	200	10008	200	20016	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10954	21	1373	376	0	661	10264	259	0	924	48	948	10877	29	1076	21	0	1	1	1	717	0	16	0	0	10037	10000	7	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	3	0	0	2250	97	847	1	768	69	0	144	10025	800	80	91	51	25	20100	10100	10000	10100	10000	522069	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10917	24	1192	388	0	692	10249	281	4	928	44	831	10934	41	1179	28	0	0	0	0	710	1	17	1	1	10037	10000	2	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	4	4	0	2322	106	822	1	720	77	3	104	10025	800	75	84	64	25	20100	10100	10000	10100	10000	521977	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10954	28	1385	393	0	719	10274	278	0	937	42	868	10919	39	1112	28	0	0	0	0	710	1	17	1	1	10037	10000	2	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	4	0	0	2493	117	827	1	720	89	0	168	10025	770	86	84	46	25	20100	10100	10000	10100	10000	521971	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10933	28	1351	390	0	670	10260	297	8	897	34	873	10887	46	1108	28	4	0	0	0	710	1	17	1	1	10037	10000	4	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	3	0	0	2193	93	800	1	760	77	0	152	10025	804	83	90	40	25	20100	10100	10000	10100	10000	522085	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10890	24	1231	428	0	674	10270	276	3	897	42	910	10880	38	1250	21	0	0	0	0	710	1	17	1	1	10037	10000	0	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	3	0	0	2169	109	835	1	728	86	0	148	10025	759	51	97	57	25	20100	10100	10000	10100	10000	522033	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10924	24	1260	384	0	656	10268	289	3	918	32	890	10922	26	1117	14	2	0	0	0	710	1	17	1	1	10037	10000	3	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	2	0	0	2145	107	835	1	784	82	0	148	10025	773	70	77	53	25	20100	10100	10000	10100	10000	522013	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10878	14	1344	381	0	662	10236	272	0	882	38	935	10952	26	1121	14	0	0	0	0	710	1	17	1	1	10037	10000	1	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	2	0	2	2169	90	831	1	688	79	0	356	10025	787	94	78	50	25	20100	10100	10000	10100	10000	522043	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10904	16	1366	389	0	680	10275	270	0	888	40	822	10903	29	1138	14	0	0	0	0	710	1	17	1	1	10037	10000	2	0	10000	10100	10041	10041	10041	10041	10041

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10029	10040	75	1	1	1	2274	91	814	1	744	80	11	88	10025	791	122	80	70	25	20010	10010	10000	10010	10000	520809	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10950	9	1243	389	2	658	10247	272	0	892	40	820	10927	21	1143	14	0	640	3	16	3	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	0	0	2229	87	770	1	784	69	0	152	10025	794	94	87	60	25	20010	10010	10000	10010	10000	521073	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10877	7	1422	358	0	683	10259	289	2	906	36	892	10926	20	1113	7	1	640	3	16	3	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	1	0	2277	87	807	1	728	72	9	108	10025	780	90	63	60	25	20010	10010	10000	10010	10000	521049	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10914	14	1247	380	12	693	10255	256	2	902	172	895	10940	29	1257	14	0	640	3	16	2	2	10037	10000	2	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	2	0	2280	108	830	1	688	77	10	112	10025	817	50	78	79	25	20010	10010	10000	10010	10000	520913	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10868	14	1300	364	0	697	10269	303	0	864	50	937	10902	29	1206	14	0	640	3	16	3	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	0	2304	107	795	1	680	80	10	152	10025	791	50	72	61	25	20064	10039	10000	10010	10000	521049	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10906	14	1273	382	2	663	10267	301	0	916	46	979	10896	25	1092	14	2	640	2	16	3	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	2	2262	106	821	1	744	75	10	152	10025	860	82	62	88	25	20010	10010	10000	10010	10000	521017	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10908	14	1326	332	0	680	10254	286	4	936	42	956	10960	24	1251	14	2	640	3	16	3	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	76	2	2	0	2139	108	766	1	664	81	0	112	10025	815	70	60	74	25	20010	10010	10000	10010	10000	520857	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10924	14	1253	363	6	643	10262	312	2	896	36	838	10918	28	1162	14	0	640	3	16	3	3	10037	10000	2	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	2	0	2280	95	765	1	720	80	10	132	10025	777	64	80	68	25	20010	10010	10000	10010	10000	520873	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10894	14	1311	389	0	678	10285	277	0	918	46	925	10893	29	1226	14	0	640	3	16	3	2	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	0	2223	102	786	1	704	67	0	152	10025	789	41	52	62	25	20010	10010	10000	10010	10000	521017	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10902	18	1321	362	0	656	10273	285	2	882	82	896	10917	31	1163	14	0	640	3	16	3	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	2	2085	99	801	1	736	71	0	120	10025	801	55	64	63	25	20010	10010	10000	10010	10000	520955	468824	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10902	16	1302	414	0	648	10255	263	0	906	46	838	10915	29	1206	14	0	640	2	16	3	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041

Test 3: throughput

Count: 8

Code:

  str x0, [x6, #8]!
  str x0, [x7, #8]!
  str x0, [x8, #8]!
  str x0, [x9, #8]!
  str x0, [x10, #8]!
  str x0, [x11, #8]!
  str x0, [x12, #8]!
  str x0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5099

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80209	40514	306	4	4	0	0	0	1959	782	772	1	688	125	140	40688	780	1651	1501	182	25	163953	80432	80000	80100	80000	401945	1873580	1	447	49	37755	40829	40777	30706	26	30849	160100	200	80000	200	160000	40770	93	1	1	80201	100	99	100	80000	100	80000	100	80871	25	4135	505	18	883	80544	291	0	937	40	1747	81392	559	3766	35	6	5110	1	17	1	1	40816	80712	80000	80100	40974	40852	40783	40805	40820
80204	40813	306	3	0	3	0	0	1983	844	811	1	664	112	132	40830	765	1828	1690	181	25	162521	84756	80000	80100	80000	402049	1875044	1	263	49	37747	40787	40824	30726	3	30715	160100	200	80000	200	160000	40760	86	1	1	80201	100	99	100	80000	100	80000	100	80961	34	3814	503	7	850	80516	288	3	879	84	1641	81285	524	3526	42	0	5110	1	17	1	1	40813	80556	80000	80100	40823	40725	40784	40864	40817
80204	40775	306	3	3	0	0	0	1896	739	816	1	688	110	80	40658	773	1820	1990	112	25	160588	83046	80000	80100	80000	402191	1877732	1	306	49	37663	40882	40899	30635	3	30828	160100	200	80000	200	160240	40861	86	1	1	80201	100	99	100	80000	100	80000	100	80932	44	4026	448	9	848	80607	262	3	843	40	1592	81388	508	4072	42	6	5110	1	16	1	1	40664	82906	80000	80100	40749	40879	40925	40731	40717
80204	40794	307	3	3	0	0	0	1806	839	772	1	664	104	92	40833	731	1743	1583	142	25	160710	83310	80000	80100	80000	402510	1874878	1	2619	49	37760	40824	40739	30678	3	30738	160100	200	80000	200	160000	40774	85	1	1	80201	100	99	100	80000	100	80000	100	80905	44	3845	461	7	842	80575	271	6	878	40	1717	81386	535	3788	21	0	5110	1	17	1	1	40854	80751	80000	80100	40869	40931	40737	40759	40923
80204	40778	305	3	0	0	0	0	1830	781	816	1	696	107	124	40820	739	1660	1845	160	25	160400	81871	80018	80100	80000	402311	1877660	1	1254	49	37783	40765	40796	30662	3	30871	160100	200	80000	200	160000	40714	86	1	1	80201	100	99	100	80000	100	80000	100	80886	26	4127	490	9	860	80554	300	0	857	44	1471	81437	525	3671	35	6	5110	1	16	1	1	40881	83903	80000	80100	40782	40744	40862	40733	40844
80204	40845	305	3	0	0	0	0	2016	946	785	1	664	123	132	40761	765	1723	1752	136	25	160427	80808	80006	80100	80000	402486	1876845	1	855	49	37732	40784	40890	30772	3	30823	160100	200	80000	200	160000	40780	86	1	1	80201	100	99	100	80000	100	80000	100	80939	26	4448	472	23	872	80567	272	0	881	42	1640	81409	550	3554	42	0	5110	1	17	1	1	40796	82185	80000	80100	40768	40855	40770	40819	40790
80204	40810	305	3	0	0	0	0	1812	825	775	1	656	115	132	40792	789	1719	1764	112	25	160594	80865	80000	80100	80000	407405	1878764	1	1818	49	37771	40840	40805	30695	3	30847	160100	200	80000	200	160000	40771	92	1	1	80201	100	99	100	80000	100	80000	100	80907	35	4645	479	5	856	80484	291	0	847	38	1608	81346	536	4002	35	0	5110	1	16	1	1	40797	80500	80000	80100	40881	40886	40843	40736	40897
80204	40791	306	3	0	3	0	0	1842	954	777	1	656	128	120	40796	771	1870	1730	165	25	160769	80809	80000	80100	80000	411640	1873198	1	192	49	37578	40802	40761	30663	3	30686	160100	200	80000	200	160000	40803	86	1	1	80201	100	99	100	80000	100	80000	100	80941	44	3970	435	6	855	80532	299	0	831	82	1519	81363	565	3991	40	0	5110	1	16	1	1	40655	83442	80000	80100	40786	40830	40703	40794	40784
80204	40827	305	3	3	3	0	0	1746	895	795	1	680	102	124	40730	774	1746	1812	132	25	160685	86797	80000	80100	80000	402247	1878668	1	436	49	37683	40700	40732	30707	3	30781	160100	200	80000	200	160000	40779	92	1	1	80201	100	99	100	80000	100	80000	100	80885	40	4085	454	14	909	80571	330	2	920	40	1701	81458	522	3907	27	2	5110	1	17	1	1	40826	81980	80000	80100	40726	40708	40742	40830	40843
80204	40788	305	2	2	0	0	0	1872	865	806	1	632	117	124	40698	764	1897	1724	113	25	165349	82800	80000	80100	80000	402172	1876724	1	281	49	37662	40739	40759	30627	3	30798	160100	200	80000	200	160000	40742	85	1	1	80201	100	99	100	80000	100	80000	100	80870	27	3983	478	5	868	80516	281	0	889	40	1596	81365	541	4554	26	0	5110	1	17	1	1	40839	80320	80000	80100	40743	40738	40823	40762	40762

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5101

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c3	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80029	40681	305	0	0	0	0	0	0	1602	710	788	1	616	125	52	40970	771	1752	1843	226	25	160369	80667	80095	80010	80000	401574	1880776	0	264	49	37711	40813	40731	30774	3	30702	160010	20	80000	20	160000	40796	75	1	1	80021	10	9	10	80000	10	80000	10	80869	8	3950	481	3	879	80569	268	1	866	36	1563	81429	500	4166	13	1	0	5020	0	3	17	3	2	40967	80144	80000	80010	40731	40804	40704	40791	40834
80024	40787	306	1	0	0	0	0	0	1785	780	778	1	688	106	72	40901	802	1689	1780	188	25	165155	80495	80101	80010	80000	409073	1877944	0	1453	49	37627	40836	40794	30754	3	30750	160010	20	80000	20	160000	40766	75	1	1	80021	10	9	10	80000	10	80000	10	80874	0	4518	466	16	897	80548	298	0	844	36	1604	81380	540	3945	0	0	0	5020	0	3	16	2	3	40822	80685	80000	80010	40732	40848	40730	40837	40779
80024	40745	306	0	0	0	0	0	0	1776	874	812	1	704	101	140	40817	753	1473	1594	141	25	160545	80532	80085	80010	80000	402122	1875904	0	223	49	37627	40744	40776	30836	3	30779	160010	20	80000	20	160000	40716	75	1	1	80021	10	9	10	80000	10	80000	10	80864	14	3844	492	12	862	80534	277	1	877	36	1504	81416	458	4356	14	0	0	5020	0	3	17	2	3	40783	80589	80000	80010	40837	40880	40808	40762	40708
80024	40806	305	1	0	1	1	0	0	1797	766	805	1	680	125	148	40722	772	1988	1697	204	25	160655	83264	80104	80010	80000	401455	1879408	0	536	49	37816	40688	40820	30792	3	30814	160010	20	80000	20	160000	40835	75	1	1	80021	10	9	10	80000	10	80000	10	80874	0	3934	472	12	841	80483	261	0	871	34	1528	81436	507	4687	0	0	0	5020	0	3	18	3	3	40727	86513	80000	80010	40797	40766	40756	40803	40802
80024	40840	305	0	0	0	0	0	0	1797	750	751	1	728	116	120	40808	804	1517	1835	135	25	160556	85215	80031	80010	80000	400836	1877152	0	266	49	37693	40843	40676	30646	3	30781	160010	20	80000	20	160000	40882	75	1	1	80021	10	9	10	80000	10	80000	10	80936	13	4354	489	3	852	80514	257	0	878	126	1538	81363	557	3963	14	0	0	5020	0	3	16	3	2	40839	80677	80000	80010	40816	40891	40803	40868	40964
80024	40747	306	1	1	0	0	0	0	1713	763	780	1	624	117	104	40899	794	1846	1745	162	25	166016	88009	80062	80010	80000	402911	1873192	0	145	49	37708	40804	40770	30772	3	30760	160010	20	80000	20	160000	40760	76	1	1	80021	10	9	10	80000	10	80000	10	80904	7	4266	503	7	913	80490	277	1	863	40	1644	81403	539	3753	13	0	0	5020	0	3	16	3	2	40726	80510	80000	80010	40900	40837	40852	40830	40766
80024	40838	306	1	1	1	0	0	0	1881	739	784	1	680	117	128	40679	780	1606	1618	177	25	163846	80457	80000	80010	80000	410421	1874224	0	289	49	37707	40784	40848	30868	3	30726	160010	20	80000	20	160000	40699	75	1	1	80021	10	9	10	80000	10	80000	10	80874	0	4365	457	4	840	80561	261	0	860	40	1629	81400	511	4556	0	0	0	5020	2	3	18	3	3	40839	80638	80000	80010	40732	40810	40849	40848	40842
80024	40788	306	0	0	0	0	0	0	1902	786	784	1	672	129	124	40776	793	1791	1793	178	25	160569	83740	80043	80010	80000	413639	1877200	0	386	49	37736	40767	40721	30765	3	30842	160010	20	80000	20	160000	40719	75	1	1	80021	10	9	10	80000	10	80000	10	80910	12	4497	469	10	846	80527	272	1	905	40	1598	81394	532	3507	14	0	0	5020	0	3	16	3	3	40772	83206	80000	80010	40716	40818	40790	40813	40863
80024	40769	306	1	1	1	1	0	0	1764	765	792	1	632	119	108	40817	778	1894	1380	177	25	160683	81019	80000	80010	80000	408098	1873096	0	671	49	37767	40879	40810	30796	3	30861	160010	20	80000	20	160000	40806	75	1	1	80021	10	9	10	80000	10	80000	10	80848	15	4567	466	10	858	80541	283	0	841	154	1574	81389	526	3967	14	1	0	5020	0	3	17	3	2	40794	80449	80000	80010	40846	40812	40814	40776	40791
80024	40857	305	0	0	0	0	0	0	1602	766	798	1	624	102	100	40734	816	1918	1601	177	25	160679	89530	80000	80010	80000	402452	1875496	0	1879	49	37731	40833	40831	30723	3	30788	160010	20	80000	20	160000	40896	75	1	1	80021	10	9	10	80000	10	80000	10	80891	14	4179	513	11	843	80572	259	1	856	40	1615	81416	511	4861	13	0	0	5020	0	3	16	2	3	40777	80574	80000	80010	40733	40871	40720	40729	40874

STR (pre-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations