Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUBS (sxtw, 64-bit)

Test 1: uops

Code:

  subs x0, x0, w1, sxtw
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10042035150006110001862252000200010001262351203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
10042035150006110001862252000200010001262351203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
10042035150006110001862252000200010001262351203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
10042035150006110001862252000200010001262351203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
10042035150006110001862252000200010001262351203520351729318661000100020002035441110011000000731431119202000100020362036203620822036
10042035150006110001862252000200010001262350203520351729318661000100020002035411110011000010731431119202000100020362036203620362036
10042035150006110001862252000200010001262350203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
10042035150006110001862252000200010001262351203520351729318661000100020002035411110011000200731431119532000100020362036203620362036
10042035150006110001862252000200010001262350203520351729318661000100020002035411110011000010731431119202000100020362036203620362036
10042035150006110001862252000200010001262351203520351729318661000100020002035411110011000000731431119202000100020362036203620362036

Test 2: Latency 1->2

Code:

  subs x0, x0, w1, sxtw
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03181e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020420035150000611000019862252010020100101001305121149169552003520035185811118720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
102042003515000061100181986225201002010010100130512114917001200352003518581318720101001028820376200354111102011009910010100100030710339111992220000101002003620036200362003620036
102042003515001448861100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
102042003515000061100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
10204200351500026461100001986225201002010010100130512114916955200352003518615318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
102042003515000061100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
102042003515000061100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
102042003515000061100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
102042003515000061100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
102042003515000061100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100500710139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002420035150061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000640441221993020000100102003620036200362003620036
1002420035150061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010063640241221993020000100102003620036200362003620036
1002420035150061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102017720036200362003620036
1002420035150061100001986225200102001010010130522949169552003520035186033187401001010020200202008141111002110910100101020640241221993020000100102003620036200362003620036
1002420035150061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002210910100101000640241221993020000100102003620036200362003620036
100242003515012611000019862252001020010100101305229491709420035200351860331874010010100202002020035411110021109101001010057640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010075640241221993020000100102003620036200362003620036
10024200351500441100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
1002420035150061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  subs x0, x1, w0, sxtw
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515000000006110000198622520100201001010013051211491695502003520035185813187201010010200202002003541111020110099100101001000000000710239221992220000101002003620036200362003620036
102042003515000000006110000198622520100201001010013051211491695502003520035185813187201010010200202002003541111020110099100101001000000000710239221992220000101002003620036200362003620036
1020420035150000000042010000198622520100201001010013051211491695502003520035185813187201010010200202002003541111020110099100101001000000000710239221992220000101002003620036200362003620036
102042003514900000006110000198622520100201001010013051211491695502003520035185813187201010010200202002003541111020110099100101001000000000710239221992220000101002003620036200362003620036
102042003515000000008210000198622520100201001010013051211491695502003520035185813187201010010200202002003541111020110099100101001000000000710239221992220000101002003620036200362003620036
102042003515000000006110000198622520100201001010013051210491695502003520035185813187201010010200202002003541111020110099100101001000000000710239221992220000101002003620036200362003620036
102042003515000000006110000198622520100201001010013051211491695502003520035185813187201010010200202002003541111020110099100101001000000000710239221992220000101002003620036200362003620036
102042003515000000006110000198622520100201001010013051210491695502003520035185813187201010010200202002003541111020110099100101001000000012660710239221992220000101002003620036200362003620036
1020420035150000000025110000198622520100201001010013051210491695502003520035185813187201010010200202002003541111020110099100101001000000000710239221992220000101002003620036200362003620036
10204200351500000000286910000198622520100201001010013051211491695502003520035185813187201010010200202002003541111020110099100101001000000000710239221992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002420035150000000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000000210640241221993020000100102003620036200362003620036
100242003515000000061100001986225200102001010010130522904916955200352003518603318740100101002020020200354111100211091010010100000000640241221993020000100102003620036200362003620036
1002420035150000000611000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101000080210640241221993020000100102003620036200362003620036
100242003515000000061100001986225200102001010010130522904916955200352003518603318740100101002020020200354111100211091010010100000000640241221993020000100102003620036200362003620036
100242003515000000061100001986225200102001010010130522914916955200352003518603318740100101002020020200354111100211091010010100000000640241221993020000100102003620036200362003620036
100242003515000000061100001986225200102001010010130522904916955200352003518603318740100101002020196200354111100211091010010100000000640241221993020000100102003620036200362003620036
100242003515000000061100001986225200102001010010130522914916955200352003518603318740100101002020020200354111100211091010010100001000640241221993020000100102003620036200362003620036
100242003515000000061100001986225200102001010010130522904916955200352003518603318740100101002020020200354111100211091010010100001000640241221993020000100102003620036200362003620036
100242003515000000061100001986225200102001010010130522904916955200352003518603318740100101002020020200354111100211091010010100000000640241221993020000100102003620036200362003620036
100242003515000000061100001986225200102001010010130522904916955200352003518603318740100101002020020200354111100211091010010100002090640241221993020000100102003620036200362022120036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs x0, x1, w2, sxtw
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03l1i tlb fill (04)191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9facbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035225100611000029899253010030100201071956240049269553003530035273917274862010720224302363003585112020110099100201001010001111320162998230000201003003630036300363003630036
20204300352250002511000029899253010030100201071956240049269553003530035273917274862010720224302363003585112020110099100201001010001111319162998230000201003003630036300363003630036
2020430035225000611000029899253010030100201071956240049269553003530035273917274862010720224302363003585112020110099100201001010001111319162998330000201003003630036300363003630036
2020430035225000611000029899253010030100201851956240049269553003530035273918274862010720224302363003585112020110099100201001010001111319162998230000201003003630036300363003630036
20204300352250001241000029899253010030100201071956240049269553003530035273918274862010720224302363003585112020110099100201001010001111319162998330000201003003630036300363003630036
2020430035224009611000029899253010030100201071956240049269553003530035273917274852010720224302363003585112020110099100201001010001111319162998230000201003003630036300363003630036
2020430035224000611000029899253010030100201071956240049269553003530035273918274862010720224302363003585112020110099100201001010001111319162998230000201003003630036300363003630036
2020430035225000611000029899253010030100201071956240049269553003530035273918274862010720224302363003585112020110099100201001010001111319162998230000201003003630036300363003630036
20204300352250005991000029899253010030100201071956240049269553003530035273917274862010720224302363003585112020110099100201001010001111319162998330000201003003630036300363003630036
2020430035224000611000029899253010030100201071956240049269553003530035273918274852010720224302363003585112020110099100201001010001111319162998230000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522500087110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000001270233112995930000200103003630036300363003630036
20024300352250006110000298912530032300322001019562890492695530035300352739132749820010200203002030035851120021109102001010010000011270133112995930000200103003630036300363003630036
200243003522500314910006298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010000001270133112995930000200103003630036300363003630036
200243003522400080510000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000001270133112995930000200103003630036300363003630036
200243003522500087110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000001270133122995930000200103003630036300363003630036
200243003522500014510000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000001270133112995930000200103003630036300363003630036
20024300352250061031000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001020985001270141122995930000200103003630036300363003630036
20024300352250006110000298912530010300102001019562890492695530081300352739132752520010201993015230035851120021109102001010010000001270133112995930000200103003630036300363003630036
20024300352240006110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010000001270133112995930000200103003630036300363003630036
20024300352250006110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010010901270133122995930000200103003630036300363003630036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs x0, x1, w2, sxtw
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)030918191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202043003522500048061100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101001111319162998230000201003003630036300363003630036
20204300352250000061100002989925301003010020107195624004926955300353003527391727485201072022430236300668511202011009910020100101001111320163002230000201003003630036300363003630036
20204300352250000061100002989925301003010020107195624014926955300353003527391727486201072022430236300358511202011009910020100101001111320162998230000201003003630036300363003630036
20204300352240000061100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101001111319162998230000201003003630036300363003630036
202043003522500098861100002989925301003010020107195624004926955300353003527391727486201072022430236300358521202011009910020100101001111319162998330000201003003630036300363003630036
20204300672240000061100002989925301003010020107195624014926955300353003527391727486201072022430236300358511202011009910020100101001111319162998230000201003003630036300363003630036
202043003522500012081100002989925301003010020107195624014926955300353003527391727485201072022430236300358511202011009910020100101001111319162998330000201003003630036300363003630036
202043003522510024061100002989925301003010020107195624014926955300353003527391827485201072022430236300358511202011009910020100101001111320162998330000201003003630036300363003630036
202043003522400030061100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101001111319162998330000201003003630036300363003630036
2020430035225003198061100002989925301003010020107195624004926955300353003527391827486201072022430236300358511202011009910020100101001111319162998230000201003003630036300363003630081

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024300352240006110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010001270133322995930000200103003630036300363003630036
20024300352250006110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010001270233222995930000200103003630036300363003630036
20024300352240006110000298972530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010001270233222995930000200103003630036300363003630036
20024300352250006110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010001270133122995930000200103003630036300363003630036
20024300352250006110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010001270133222995930000200103003630036300673003630036
20024300352250006110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010001270133222995930000200103003630036300363003630036
20024300352250006110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010001270133222995930000200103003630036300363003630036
20024300352250006110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010001270333222995930000200103003630036300363003630036
20024300352250006110000298912530010300102001019562890492695530035300352739132749820010200203018830035851120021109102001010010001270233222995930000200103003630036300363003630036
20024300352250006110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010101270133222995930000200103003630036300363003630036

Test 6: throughput

Count: 8

Code:

  subs x0, x8, w9, sxtw
  subs x1, x8, w9, sxtw
  subs x2, x8, w9, sxtw
  subs x3, x8, w9, sxtw
  subs x4, x8, w9, sxtw
  subs x5, x8, w9, sxtw
  subs x6, x8, w9, sxtw
  subs x7, x8, w9, sxtw
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)0318191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802045344740004542880013487912816013716013780276344283114950334534145341443345290984335580176802881603765341439118020110099100801001000011151242160053411160037801005341553415534155341553415
802045341440000069380013487912916013716013780176344189014950334534145341443345290984335580176802881603765341439118020110099100801001000011151240160053411160037801005341553415534155341553415
80204534144000002880013487912916013716013780176344189004950334534145341443345290984335580176802881603765341439118020110099100801001000011151240160053410160037801005341553415534155341553415
80204534144000002880013487912916013716013780176344189004950334534145341443345290984335580176802881603765341439118020110099100801001000011151240160053411160037801005341553415534155341553415
80204534143990002880013487912916013716013780176344189004950334534145341443345290934336080100802001602005341039118020110099100801001000000051101241153390160000801005341153411534115341153411
80204534104002036180000487412516010016010080203344000504950330534105341043298302434336080100802001602005341039118020110099100801001000000051101241153390160000801005341153411534115341153411
80204534104000006180000487412516010016010080100344000504950330534105341043298290934336080100802001602005341039118020110099100801001000000051101241153456160000801005341153411534115341153411
8020453410400001626180000487412516010016010080100344000504950330534105341043298290934336080100802001602005341039118020110099100801001000000051101241153390160000801005341153411534115341153411
80204534103990006180000487412516010016010080100344000504950330534105341043298290934336080100802001602005341039118020110099100801001000000051101241153390160000801005341153411534115341153411
80204534104000006180000487412516010016010080100344000504950330534105341043298302434336080100802001602005341039118020110099100801001000000051101241153390160000801005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024534014000000906180000479462516001016001080010343813004950300533805338043290325134335280010800201600205338039118002110910800101000000050208245353360160000800105338153381533815338153381
80024533804000000006180000479462516001016001080010343813004950300533805338043290325134335280010800201600205338039118002110910800101000000050203244553360160000800105338153381533815338153381
80024533803990000006180000479462516001016001080010343813014950300533805338043290325134335280010800201600205338039118002110910800101000000050203245653360160000800105338153381533815338153381
80024533804000000006180000479462516001016001080010343813004950300533805338043290325134335280010800201600205338039118002110910800101000003050203243553360160000800105338153381533815338153381
80024533804000000006180000479462516001016001080010343813014950300533805338043290293634335280010800201600205338039118002110910800101000000050205315453360160000800105338153381533815338153381
800245338039900110072680000479462516001016001080010343813014950300533805338043290325134335280010800201600205338039118002110910800101000000050255245553360160000800105338153437533815338153381
80024533803990000006180000479462516001016001080010343813014950300533805338043290325134335280010801321600205338039118002110910800101000000050203243553360160000800105338153381533815338153381
80024533803990000906180000479462516001016001080010343813004950300533805338043290293634335280010800201600205338039118002110910800101000000050205245653360160000800105338153381533815338153381
80024533804000000006180000479462516001016001080010343813004950300533805338043290293634335280010800201600205338039118002110910800101003120050203246453360160000800105338153381533815338153381
80025533804000000008280000479462516001016001080010343813014950300533805338043290325134335280010800201600205338039118002110910800101000000050205245353360160000800105338153381533815338153381