Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMN (uxtw, 64-bit)

Test 1: uops

Code:

  cmn x0, w1, uxtw
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
100470950821000304252000200010004087717097094982135611000100020007097811100110000073222116842000710710710710710
100470950611000304252000200010004087707097094982535611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087717097094982535611000100020007097811100110000073122116842000710710710710710
100470960611000304252000200010004087717097094982535611000100020007097811100110000073122116842000710710710710710
100470956611000304252000200010004087717097094982535611000100020007097811100110000073122116842000710710710710710
100470960611000304252000200010004087717097094982535611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087717097094982135611000100020007097811100110000073122116842000710710710710710
1004709506110003042520002000100040877170970949825356110001000200070978111001100001573122116842000710710710710710
100470950611000304252000200010004087717097094982535611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087717097094982135611000100020007097811100110000073122116842000710710710710710

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmn x0, w1, uxtw
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)09l2 tlb miss data (0b)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035225000014510000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
2020430035224000050010000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010020013101331222995430000101003003630036300363003630036
202043003522400106110000298932530100301002010019561981492700030080300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
2020430035224000050910000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
2020430035225000051810000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
2020430035225000052710000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231223002230000101003003630036300363013030082
2020430080226010035210006299098930141301002035119561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101241222999030000101003026430264302633026430036
2020430125225000057910000298932530146301002010019561981492695530035300352736932747820100203813020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
2020430035225000010710000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)0318191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002430071225000061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270633222995830000100103003630036300363003630036
2002430035225000061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270233222995830000100103003630036300363003630036
2002430035225000061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270233222995830000100103003630036300363003630036
2002430035225000061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270233222995830000100103003630036300363003630036
20024300352250000652100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270233222995830000100103003630036300673003630036
2002430035225000061100002989125300103001020010195628914926955300353003527391327498200102002030020300351452120021109102001010010001270233222995830000100103003630036300363003630036
2002430035225000061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270317232995830000100103003630036300363003630036
2002430035225000061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270233222995830000100103003630036300363003630036
2002430035225000061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270233222995830000100103003630036300363003630036
2002430035225000061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270233222995830000100103003630036300363003630036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmn x0, w1, uxtw
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204300352250145100002989325301003010020100195619849269553003530035273690327478201002020030200300351451120201100991002010010100000013101231322995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619849269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035224061100002989325301003010020100195619849269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
20204300352250346100002989325301003010020100195619849269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
20204300352250316100002989325301003010020100195619849269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619849269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035224061100002989325301003010020100195619849269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619849269553003530035273690327478201002020030200300351451120201100991002010010100001013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619849269553003530035273690727478201002020030200300351451120201100991002010010100000013101231222995430000101003017530309300363003630036
20204300352256147100002989325301003010020100195619849269553003530035273697327478201002020030200300351451120201100991002010010100100013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522500061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270233332995830000100103003630036300363003630036
200243003522500061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270333332995830000100103003630036300363003630036
2002430035225000536100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270233232995830000100103003630036300363003630036
2002430035225000441100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270333332995830000100103003630036300363003630036
200243003522500061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270333332995830000100103003630036300363003630036
2002430035225000726100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270333322995830000100103003630036300363003630036
2002430035225000631100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270333332995830000100103003630036300363003630036
2002430035225000287100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270333332995830000100103003630036300363003630036
2002430035225000251100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270333332995830000100103003630036300363003630036
200243003522400061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270333322995830000100103003630036300363003630036

Test 4: throughput

Count: 8

Code:

  cmn x0, w1, uxtw
  cmn x0, w1, uxtw
  cmn x0, w1, uxtw
  cmn x0, w1, uxtw
  cmn x0, w1, uxtw
  cmn x0, w1, uxtw
  cmn x0, w1, uxtw
  cmn x0, w1, uxtw
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020453456400000021103800004874125160100160100801003440005049503305341053410432982063343360801008020016020053410781180201100991008010010000000514025611533921600001005341153411534115341153411
802045341040010000103800004874125160100160100801003440005049503305341053410432982060343360801008020016020053410781180201100991008010010000000511012411533921600001005341153411534115341153411
80204534104000000561212800004874125160100160100801003440005049503305346453470432982060343360801008020016020053410781180201100991008010010000030511012412533921600001005341153411534115341153411
80204534104000000082800004874125160100160100801003440005149503305341053410432982063343462801008020016020053410781180201100991008010010000000511013111533921600001005341153411534115341153411
80204534104000000061800004874125160100160100801003440005149503305356953410432982063343360801008020016020053410781180201100991008010010000000511012411533921600001005341153411534115341153411
802045341040000000231800004874125160100160100801003440005049503305341053410432982050343360801008020016020053410781180201100991008010010001030511012411533921600001005341153411534115341153625
802045341040000000768800004874125160100160100801003440005049503305362753410432982063343360801008020016020053410781180201100991008010010000000511012411533921600001005341153411534115341153411
80204534104000000061801584874125160100160100801003440005049503305341053410432982063343360801008020016020053410781180201100991008010010000030511012411533921600001005341153411534115341153411
802045341040000000233800004874125160100160100801003440005149503305341053410432982063343360801008020016020053410781180201100991008010010000000511012411533921600001005341153411534115341153411
8020453410400000039140800004874125160100160100801003440005149503305341053410432982050343360801008020016020053410781180201100991008010010000000511012412533921600001005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03181e1f3f4c4d5051schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6b6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002453401400018061800004794653364251600101600108001034381300149503000533805338043290270734335280010800201600205338078118002110910800101000000502001924017653359160000105338153381533815338153381
80024533803990006180000479460251600101600108001034381300149503000533805338043290270734335280010800201600205338078118002110910800101002100505701724081753403160000105338153381533815338153381
8002453380400012021080000479460251600101600108001034381300149503000533805338043290256234335280010800201600205338078118002110910800101000100502001224017653526160000105338153434534345338153381
800245338040000061800004794602516001016001080010343813001495030005338053380432902562343352800108002016002053485781180021109108001010000005058017240171753359160000105338153381533815338153381
8002453380399000618000047946025160010160010800103438130014950300053380533804329025623433528001080457160020533807811800211091080010100000050200824017653444160000105338153381533815338153381
800245338040005135272680000479460251600101600108001034381300149503000533805338043290270734335280010800201600205338078118002110910800101000030502001724061753359160000105338153433533815338153381
800245338039900061800004794602516001016001080010343813001495030005338053380432902562343352800108002016002053380781180021109108001010000005020017170171753359160000105338153381533815338153381
80024533803990006180000479460251600101600108001034381300149503000533805338043290256234335280010800201600205338078118002110910800101000200502008240171753359160000105338153381533815338153381
8002453433400056106180000479460251600101600108001034381300149503000533805338043290270734335280010800201600205338078118002110910800101020000502008240171653359160000105338153381533815338153381
8002453380400000618000047946025160010160010800103438130014950300053380533804329025623433528001080020160020533807811800211091080010100000050200624017853359160000105338153381533815338153381