Firestorm: PRFM (register, PLDL3STRM) measurements

Code:

  prfm pldl3strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1624	12	31	16	31	2414	1553	912	25	1000	1000	1000	70276	1	1601	1636	1295	3	1489	1000	1000	1000	1603	1597	1	1	1001	269	2250	2243	3249	0	2436	2270	1000	73	2	16	1	1	1517	1000	1586	1591	1631	1623	1600
1004	1618	12	32	16	31	2429	1562	880	25	1000	1000	1000	70478	1	1565	1586	1347	3	1483	1000	1000	1000	1614	1599	1	1	1001	252	2235	2275	3252	0	2429	2269	1000	73	1	16	1	1	1494	1000	1614	1595	1589	1596	1578
1004	1614	12	32	16	30	2430	1615	899	25	1000	1000	1000	70084	1	1601	1609	1312	3	1444	1000	1000	1000	1607	1612	1	1	1001	258	2252	2255	3225	0	2437	2275	1000	73	1	16	1	1	1496	1000	1620	1621	1585	1613	1587
1004	1599	12	32	16	30	2424	1591	895	25	1000	1000	1000	70459	1	1604	1632	1290	3	1443	1000	1000	1000	1600	1569	1	1	1001	270	2262	2251	3239	0	2413	2271	1000	73	1	16	1	1	1505	1000	1619	1583	1562	1601	1619
1004	1584	12	30	16	32	2439	1577	885	25	1000	1000	1000	69451	1	1603	1618	1345	3	1492	1000	1000	1000	1612	1594	1	1	1001	260	2253	2257	3237	0	2433	2252	1000	73	1	16	1	1	1512	1000	1622	1620	1605	1623	1567
1004	1618	12	32	16	32	2428	1605	920	25	1000	1000	1000	69879	1	1761	1576	1319	3	1454	1000	1000	1000	1586	1593	1	1	1001	270	2273	2255	3260	0	2434	2239	1000	73	1	16	1	1	1508	1000	1591	1612	1604	1581	1622
1004	1627	12	32	16	31	2439	1609	889	25	1000	1000	1000	70042	1	1567	1596	1328	3	1481	1000	1000	1000	1607	1629	1	1	1001	264	2250	2264	3255	0	2440	2249	1000	73	1	16	1	1	1524	1000	1633	1629	1629	1580	1585
1004	1647	12	31	16	32	2422	1605	858	25	1000	1000	1000	69957	1	1574	1609	1349	3	1477	1000	1000	1000	1585	1590	1	1	1001	265	2258	2244	3248	0	2431	2238	1000	73	1	16	1	1	1479	1000	1608	1617	1613	1596	1624
1004	1615	12	31	16	32	2428	1586	883	25	1000	1000	1000	70291	1	1594	1587	1295	3	1444	1000	1000	1000	1606	1605	1	1	1001	243	2221	2270	3263	0	2415	2238	1000	73	1	16	1	1	1510	1000	1609	1623	1638	1639	1666
1004	1613	12	32	16	32	2423	1582	870	25	1000	1000	1000	69825	1	1566	1630	1295	3	1475	1000	1000	1000	1604	1595	1	1	1001	257	2262	2273	3261	0	2469	2220	1000	73	1	16	1	1	1508	1000	1624	1620	1603	1585	1605

Test 2: throughput

Code:

  prfm pldl3strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5670

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15625	117	0	367	192	0	363	0	0	24773	15643	9721	25	20208	10211	10000	10100	10000	130503	727098	41	49	12592	15719	15736	12841	3	13217	20100	10200	10000	10200	10000	15597	156	1	1	20201	100	99	2207	100	10100	100	23025	22982	33018	0	0	24773	23174	10000	0	1310	2	16	2	2	15589	10087	10000	10100	15594	15620	15556	15706	15683
20204	15718	118	0	363	193	0	364	0	0	24685	15643	9613	25	20223	10181	10000	10100	10000	131183	732376	38	49	12568	15643	15677	12930	3	13106	20100	10200	10000	10200	10000	15663	155	1	1	20201	100	99	2498	100	10100	100	22955	22981	32820	0	0	24590	22872	10000	0	1311	2	17	2	2	15586	10096	10000	10100	15563	15657	15742	15616	15598
20204	15796	116	0	370	190	0	374	0	0	24618	15613	9837	25	20214	10241	10000	10100	10000	129240	727847	42	49	12588	15729	15646	12887	3	13046	20100	10200	10000	10200	10000	15638	154	1	1	20201	100	99	2250	100	10100	100	22864	22897	32760	0	0	24556	23118	10000	0	1310	2	16	2	2	15432	10102	10000	10100	15759	15595	15595	15657	15567
20204	15639	115	0	367	195	0	368	0	0	24699	15622	9747	25	20241	10323	10000	10100	10000	129578	731979	33	49	12585	15749	15779	12864	7	13219	20100	10200	10000	10200	10000	15732	154	1	1	20201	100	99	2320	100	10100	100	22904	22969	32924	0	2	24647	22956	10000	0	1310	2	16	2	2	15540	10123	10000	10100	15715	15689	15677	15621	15588
20204	15706	117	0	372	191	0	362	0	0	24843	15683	9628	25	20178	10199	10000	10100	10000	129698	737113	41	49	12583	15623	15704	12838	3	13187	20100	10200	10000	10200	10000	15507	155	1	1	20201	100	99	2307	100	10100	100	23205	23192	32870	0	0	24861	22993	10000	0	1310	2	16	2	2	15493	10126	10000	10100	15737	15621	15638	15890	15531
20204	15780	118	0	368	192	0	362	0	0	24673	15592	9602	25	20202	10229	10000	10100	10000	129467	735273	43	49	12627	15603	15672	12914	3	13211	20100	10200	10000	10200	10000	15620	155	1	1	20201	100	99	2384	100	10100	100	23059	22944	33133	0	0	24741	22913	10000	0	1310	2	16	2	2	15543	10120	10000	10100	15556	15711	15543	15554	15611
20204	15669	117	0	369	195	0	365	0	0	24674	15552	9720	25	20393	10220	10000	10100	10000	130206	729588	43	49	12618	15755	15628	12925	3	13142	20100	10200	10000	10200	10000	15686	162	1	1	20201	100	99	2270	100	10100	100	22987	22743	33059	0	0	24649	22835	10000	0	1310	2	25	2	2	15549	10117	10000	10100	15634	15557	15811	15578	15703
20204	15775	117	0	365	194	0	364	0	0	24717	15636	9717	25	20229	10193	10000	10100	10000	131490	729822	30	49	12557	15639	15661	12962	3	13204	20100	10200	10000	10200	10000	15801	155	1	1	20201	100	99	2447	100	10100	100	22835	23096	32973	0	0	24737	22971	10000	0	1310	2	16	2	2	15527	10117	10000	10100	15665	15599	15679	15650	15640
20204	15669	117	0	369	191	0	364	0	0	24807	15722	9695	25	20230	10232	10000	10100	10000	130259	731455	39	49	12497	15719	15602	12989	3	13188	20100	10200	10000	10200	10000	15614	156	1	1	20201	100	99	2349	100	10100	100	22829	23142	33086	0	0	24910	22978	10000	0	1310	2	16	2	2	15681	10120	10000	10100	15551	15828	15619	15609	15661
20204	15660	116	0	370	186	0	367	0	0	24707	15681	9698	25	20229	10214	10000	10100	10000	130566	731411	32	49	12556	15678	15772	12942	3	13105	20100	10200	10000	10200	10000	15439	154	1	1	20201	100	99	2303	100	10100	100	23073	22871	32791	0	0	24790	22891	10000	0	1310	2	16	2	2	15469	10087	10000	10100	15562	15664	15664	15589	15641

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5686

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15684	119	358	185	356	0	24623	15573	9934	25	20148	10260	10000	10010	10000	132659	732581	0	37	49	12749	15688	15752	12996	3	13083	20010	10020	10000	10020	10000	15602	143	1	1	20021	10	9	2305	10	10010	10	22877	22983	33058	3	24533	22894	10000	1270	3	16	3	3	15671	10168	10000	10010	15669	15692	15867	15763	15692
20024	15725	117	349	186	355	0	24726	15699	9763	25	20324	10142	10000	10010	10000	131948	741530	0	45	49	12605	15691	15617	12962	3	13169	20010	10020	10000	10020	10000	15757	151	1	1	20021	10	9	2317	10	10010	10	22823	22932	32866	28	24542	22884	10000	1270	4	16	3	3	15515	10117	10000	10010	15605	15596	15615	15777	15671
20024	15719	119	358	184	360	0	24740	15657	9757	25	20145	10100	10000	10010	10000	133254	729466	0	33	49	12638	15778	15660	13117	3	13108	20010	10020	10000	10020	10000	15571	147	1	1	20021	10	9	2273	10	10010	10	22927	22929	32936	0	24792	22982	10000	1271	3	16	3	3	15481	10108	10000	10010	15696	15648	15669	15684	15769
20024	15657	118	359	182	354	0	24749	15714	9759	25	20181	10136	10000	10010	10000	131271	736015	0	42	49	12506	15553	15598	13058	3	13101	20010	10020	10000	10020	10000	15748	144	1	1	20021	10	9	2319	10	10010	10	22900	22953	33258	0	24655	23127	10000	1271	3	16	3	3	15546	10111	10000	10010	15694	15670	15648	15758	15691
20024	15852	118	361	185	358	0	24507	15719	9566	25	20121	10145	10000	10010	10000	132240	736453	0	50	49	12574	15760	15657	12911	3	13297	20010	10020	10000	10020	10000	15557	318	1	1	20021	10	9	2358	10	10010	10	22900	22753	32839	0	24677	22906	10000	1271	3	16	3	3	15459	10135	10000	10010	15706	15783	15777	15648	15596
20024	15704	118	361	186	351	0	24605	15653	9792	25	20109	10157	10000	10010	10000	131431	739227	0	48	49	12533	15585	15700	13050	3	13190	20010	10020	10000	10020	10000	15637	151	1	1	20021	10	9	2386	10	10010	10	23162	22850	32942	0	24677	23103	10000	1270	3	16	3	3	15471	10135	10000	10010	15637	15705	15741	15556	15505
20024	15671	117	360	187	353	0	24624	15653	9800	25	20139	10133	10000	10010	10000	132305	737313	1	41	49	12707	15604	15642	12919	3	13166	20010	10020	10000	10020	10000	15703	151	1	1	20021	10	9	2232	10	10010	10	22998	23036	33163	0	24810	23246	10000	1271	3	16	3	3	15719	10162	10000	10010	15691	15667	15805	15681	15639
20024	15780	118	357	182	352	0	24674	15626	9742	25	20136	10142	10000	10010	10000	131988	731652	1	46	49	12551	15702	15753	13095	3	13086	20010	10020	10000	10020	10000	15615	144	1	1	20021	10	9	2443	10	10010	10	23010	22793	32853	0	24599	22842	10000	1270	3	16	3	3	15560	10123	10000	10010	15634	15634	15709	15754	15696
20024	15525	118	354	188	353	0	24554	15666	9674	25	20139	10145	10000	10010	10000	132834	734386	1	47	49	12567	15593	15638	12958	3	13188	20010	10020	10000	10020	10000	15643	151	1	1	20021	10	9	2210	10	10010	10	23018	23079	33053	26	24846	22927	10000	1270	3	16	3	3	15492	10156	10000	10010	15754	15703	15623	15664	15659
20024	15771	117	353	183	356	0	24674	15705	9727	25	20127	10145	10000	10010	10000	133309	736375	1	46	49	12544	15697	15771	13076	3	13225	20010	10020	10000	10020	10000	15597	148	1	1	20021	10	9	2299	10	10010	10	22934	23036	32940	0	24612	22984	10000	1271	3	16	3	3	15549	10141	10000	10010	15679	15641	15737	15769	15537

Test 3: throughput

Code:

  prfm pldl3strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5454

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15533	116	336	180	338	24543	0	15385	9526	25	10100	100	10000	100	10000	500	720074	49	12377	15390	15467	13951	6	14170	10100	200	10016	200	10024	15443	12206	1	1	10201	100	99	2582	100	100	100	22760	22782	32748	0	4	24599	22781	10000	1	1	1	719	0	16	0	0	15396	10000	100	15482	15499	15415	15482	15493
10204	15473	116	337	171	334	24504	0	15481	9423	25	10100	100	10000	100	10000	500	725238	49	12290	15393	15499	13988	7	14136	10211	200	10008	200	10024	15484	12248	1	1	10201	100	99	2632	100	100	100	22717	22698	32770	0	1	24496	22741	10000	1	1	1	722	2	24	2	2	15235	10000	100	15406	15404	15433	15382	15501
10204	15437	116	333	170	335	24508	1	15399	9496	25	10100	100	10000	100	10000	500	724602	49	12429	15427	15414	14040	6	14064	10100	200	10000	200	10000	15387	12181	1	1	10201	100	99	2628	100	100	100	22847	22851	32765	0	26	24535	22890	10000	1	1	1	722	2	24	2	2	15308	10000	100	15441	15459	15463	15399	15468
10204	15554	116	333	175	333	24611	0	15440	9502	25	10100	100	10000	100	10000	500	724146	49	12325	15438	15341	14028	7	14212	10100	200	10008	200	10008	15410	12214	1	1	10201	100	99	2474	100	100	100	22811	22796	32807	0	27	24619	22757	10000	1	1	1	717	0	16	0	0	15454	10000	100	15411	15371	15441	15443	15413
10204	15441	116	336	175	333	24610	0	15418	9471	25	10100	100	10000	100	10000	500	727995	49	12382	15471	15467	13920	6	14112	10105	200	10024	200	10008	15456	12257	1	1	10201	100	99	2576	100	100	100	22718	22611	32738	0	0	24969	22801	10000	1	1	1	717	0	16	0	0	15225	10000	100	15518	15490	15518	15446	15512
10204	15472	115	336	176	339	24589	0	15454	9519	25	10100	100	10000	100	10000	500	724273	49	12376	15419	15464	14023	6	14122	10100	200	10016	200	10008	15418	12149	1	1	10201	100	99	2611	100	100	100	22769	22753	32733	0	1	24543	22727	10000	1	1	1	717	0	16	0	0	15351	10000	100	15470	15491	15433	15327	15403
10204	15488	116	344	182	337	24682	0	15521	9511	25	10100	100	10000	100	10000	500	720431	49	12335	15486	15402	14026	7	14227	10100	200	10016	200	10008	15444	12268	1	1	10201	100	99	2625	100	100	100	22764	22819	32771	0	0	24517	22765	10000	1	1	1	718	0	16	0	0	15334	10000	100	15401	15498	15415	15468	15488
10204	15462	115	335	173	336	24547	0	15395	9471	25	10100	100	10000	100	10000	500	721800	49	12337	15458	15482	13987	7	14231	10102	200	10016	200	10016	15443	12216	1	1	10201	100	99	2583	100	100	100	22717	22726	32652	0	0	24453	22802	10000	1	1	1	718	0	16	0	0	15379	10000	100	15431	15386	15457	15516	15436
10204	15461	115	329	166	336	24604	0	15448	9558	25	10100	100	10000	100	10000	500	722574	49	12329	15506	15471	14079	6	14144	10108	200	10016	200	10016	15338	12244	1	1	10201	100	99	2633	100	100	100	22896	22670	32670	0	47	24614	22852	10000	1	1	1	717	0	16	0	0	15396	10000	100	15473	15462	15507	15418	15446
10204	15499	115	334	178	336	24538	0	15425	9423	25	10100	100	10000	100	10003	500	723944	49	12417	15313	15420	13982	6	14249	10103	200	10016	200	10008	15399	12193	1	1	10201	100	99	2609	100	100	100	22818	22816	32721	0	0	24501	22755	10000	1	1	1	719	0	16	0	0	15304	10000	100	15415	15468	15494	15431	15570

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5492

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15536	116	294	149	292	23934	15458	9545	25	10010	10	10000	10	10000	50	724421	0	49	12330	15525	15473	14023	3	14208	10010	20	10000	20	10000	15462	15362	1	1	10021	10	9	2635	10	10	10	22196	22236	32198	0	23850	22122	10000	640	2	16	2	2	15363	0	10000	10	15479	15455	15491	15437	15468
10024	15495	115	293	147	292	23872	15388	9576	25	10010	10	10000	10	10000	50	723993	0	49	12484	15484	15515	14084	3	14214	10010	20	10000	20	10000	15462	15363	1	1	10021	10	9	2634	10	10	10	22252	22122	32199	0	24000	22184	10000	640	2	16	2	2	15350	0	10000	10	15450	15443	15411	15498	15537
10024	15505	116	289	147	292	23893	15482	9489	25	10010	10	10000	10	10000	50	723471	0	49	12369	15384	15403	13979	3	14225	10010	20	10000	20	10000	15455	15392	1	1	10021	10	9	2627	10	10	10	22249	22157	32151	0	23909	22244	10000	640	2	16	2	2	15357	0	10000	10	15452	15451	15468	15531	15471
10024	15525	116	295	148	292	23777	15477	9541	25	10010	10	10000	10	10000	50	726322	0	49	12375	15467	15505	13981	3	14154	10010	20	10000	20	10000	15477	15445	1	1	10021	10	9	2620	10	10	10	22146	22166	32163	3	23912	22157	10000	640	2	16	2	2	15304	0	10000	10	15496	15512	15543	15450	15403
10024	15531	115	293	146	291	23880	15498	9503	25	10010	10	10000	10	10000	50	726238	1	49	12335	15523	15453	14111	3	14197	10010	20	10000	20	10000	15447	15478	1	1	10021	10	9	2544	10	10	10	22226	22208	32284	2	23844	22189	10000	640	2	16	2	2	15409	0	10000	10	15441	15484	15441	15492	15525
10024	15519	115	291	146	292	23918	15461	9525	25	10010	10	10000	10	10000	50	726020	0	49	12413	15500	15521	14153	3	14194	10010	20	10000	20	10000	15397	15433	1	1	10021	10	9	2622	10	10	10	22147	22269	32192	1	23953	22243	10000	640	2	16	2	2	15396	0	10000	10	15504	15513	15477	15471	15517
10024	15479	116	292	147	296	23906	15490	9447	25	10010	10	10000	10	10000	50	724536	0	49	12397	15490	15467	14096	3	14167	10010	20	10000	20	10000	15424	15428	1	1	10021	10	9	2493	10	10	10	22172	22213	32201	0	23930	22291	10000	640	2	16	2	2	15314	0	10000	10	15495	15426	15553	15507	15416
10024	15564	116	291	145	291	23871	15568	9470	25	10010	10	10000	10	10000	50	729190	0	49	12442	15523	15526	14148	3	14179	10010	20	10000	20	10000	15452	15459	1	1	10021	10	9	2569	10	10	10	22195	22166	32193	0	23903	22177	10000	640	2	16	2	2	15448	0	10000	10	15536	15526	15520	15468	15408
10024	15452	117	296	146	293	23869	15452	9536	25	10010	10	10000	10	10000	50	727484	0	49	12460	15486	15416	14135	3	14221	10010	20	10000	20	10000	15425	15541	1	1	10021	10	9	2556	10	10	10	22179	22174	32248	0	23828	22216	10000	640	2	16	2	2	15376	0	10000	10	15390	15524	15532	15502	15497
10024	15481	116	293	145	288	23886	15465	9593	25	10010	10	10000	10	10000	50	723737	1	49	12427	15419	15436	14086	3	14218	10010	20	10000	20	10000	15406	15384	1	1	10021	10	9	2575	10	10	10	22189	22164	32219	0	24162	22188	10000	640	2	16	2	2	15323	0	10000	10	15398	15505	15515	15492	15506

PRFM (register, PLDL3STRM)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations