Firestorm: STR (register, uxtw, 32-bit) measurements

Code:

  str w0, [x6, w7, uxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	558	4	1	0	0	1	0	19	1	1	545	16	16	5	25	1000	1000	1000	22932	1	552	561	360	3	416	1000	1000	3000	552	557	1	1	1001	1000	1000	1014	15	36	0	0	1016	0	1	19	1002	16	35	14	3	73	1	16	1	1	547	1000	548	553	548	561	561
1004	542	4	0	0	0	0	0	3	0	0	535	16	0	0	25	1000	1000	1000	22424	1	542	540	355	3	400	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	0	34	0	0	1002	0	0	2	1002	2	34	0	0	73	1	16	1	1	539	1000	541	552	543	543	543
1004	542	5	0	0	0	0	0	0	0	0	527	16	16	0	25	1000	1000	1000	22352	1	540	542	353	3	400	1000	1000	3000	542	540	1	1	1001	1000	1000	1000	0	0	0	0	1002	0	0	2	1000	2	34	0	0	73	1	16	1	1	539	1000	541	551	543	543	543
1004	542	4	0	0	0	0	0	6	0	0	525	16	0	0	25	1000	1000	1000	22424	0	542	549	353	3	400	1000	1000	3000	542	550	1	1	1001	1000	1000	1000	0	0	0	0	1000	0	0	2	1002	0	0	0	0	73	1	16	1	1	548	1000	541	543	552	552	543
1004	542	4	0	0	0	0	0	0	0	0	527	16	16	0	25	1000	1000	1000	22352	1	542	542	355	3	400	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	0	34	0	0	1002	1	0	2	1000	2	34	0	0	73	1	16	1	1	547	1000	543	551	552	541	543
1004	540	4	0	0	0	0	0	9	0	0	527	16	16	0	25	1000	1000	1000	22424	1	542	549	353	3	408	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	34	0	0	1002	0	0	0	1002	2	0	0	0	73	1	16	1	1	539	1000	551	550	541	541	541
1004	540	4	0	0	0	0	0	9	0	0	527	16	16	2	25	1000	1000	1000	22424	1	542	550	353	3	408	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	34	0	0	1000	0	0	2	1002	2	34	0	0	73	1	16	1	1	539	1000	543	541	543	541	550
1004	540	4	0	0	0	0	0	3	0	0	525	0	16	0	25	1000	1000	1000	22424	1	540	551	355	3	400	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	0	0	0	0	1002	0	0	0	1002	2	34	0	0	73	1	16	1	1	537	1000	541	551	550	541	543
1004	542	4	0	0	0	0	0	0	1	0	525	16	16	0	25	1000	1000	1000	22352	1	542	551	355	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	0	34	0	0	1002	0	0	5	1002	0	34	0	0	73	1	16	1	1	539	1000	543	541	541	552	552
1004	551	4	0	0	0	0	0	3	0	0	527	0	16	0	25	1000	1000	1000	22352	1	542	550	355	3	400	1000	1000	3000	542	551	1	1	1001	1000	1000	1000	0	34	0	0	1002	0	0	0	1002	0	0	0	0	73	1	16	1	1	539	1000	541	543	543	551	541

Count: 8

Code:

  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]
  str w0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40051	300	0	9	1	0	40025	16	16	0	25	80100	100	80000	100	80007	500	1839455	1	49	36969	40042	40049	29968	7	29992	80107	200	80016	200	240048	40049	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	2	80002	2	34	0	1	1	1	5118	0	16	0	40120	80000	100	40050	40043	40051	40043	40051
80204	40040	300	0	9	1	0	40025	0	16	0	25	80100	100	80000	100	80006	500	1839455	1	49	36960	40040	40040	29959	7	29994	80107	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	2	80002	0	34	0	1	1	1	5118	0	16	0	40037	80000	100	40043	40052	40043	40043	40041
80204	40042	300	0	0	0	0	40035	16	16	0	25	80100	100	80000	100	80007	500	1839810	1	49	36960	40042	40042	29959	7	29992	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80002	0	0	80002	2	0	0	1	1	1	5118	0	16	0	40039	80000	100	40043	40043	40043	40041	40043
80204	40050	299	0	3	1	0	40027	16	16	0	25	80100	100	80000	100	80007	500	1839810	1	49	36962	40042	40040	29961	7	29992	80107	200	80016	200	240432	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80000	0	0	80002	2	34	0	1	1	1	5118	0	16	0	40037	80000	100	40041	40051	40043	40043	40043
80204	40042	300	0	3	1	0	40034	16	16	0	25	80100	100	80000	100	80007	500	1839455	1	49	36960	40040	40049	29968	7	29992	80106	200	80016	200	240048	40179	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	2	80002	2	0	0	1	1	1	5118	0	16	0	40039	80000	100	40041	40041	40050	40041	40041
80204	40042	300	0	9	0	0	40027	16	16	0	25	80100	100	80000	100	80007	500	1839455	1	49	36960	40040	40042	29959	7	30002	80107	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80002	0	2	80002	0	0	0	1	1	1	5118	0	16	0	40037	80000	100	40043	40041	40043	40043	40043
80204	40042	300	0	3	1	0	40036	16	16	0	25	80100	100	80000	100	80006	500	1839455	1	49	36969	40042	40049	29959	7	29994	80107	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	0	80000	0	34	0	1	1	1	5118	0	16	0	40039	80000	100	40043	40043	40043	40051	40041
80204	40040	300	0	3	1	0	40027	0	16	0	25	80100	100	80000	100	80007	500	1839455	1	49	36960	40042	40050	29959	7	29994	80107	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80002	0	2	80002	2	0	0	1	1	1	5118	0	16	0	40039	80000	100	40041	40043	40051	40043	40051
80204	40042	299	0	0	1	0	40027	16	16	3	25	80100	100	80000	100	80007	500	1839858	1	49	36960	40042	40042	29961	7	29992	80107	200	80016	200	240048	40051	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80000	0	2	80002	2	0	0	1	1	1	5118	0	16	0	40039	80000	100	40043	40043	40052	40043	40052
80204	40042	300	0	0	0	0	40027	16	0	0	25	80100	100	80000	100	80006	500	1839455	1	49	36960	40040	40042	29961	7	29992	80107	200	80502	200	240048	40179	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	2	80000	2	34	0	1	1	1	5118	0	16	0	40047	80000	100	40043	40050	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40051	300	0	0	0	0	0	0	9	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	49	36960	40040	40042	29977	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	80002	0	8	80002	2	34	0	5020	27	16	20	25	40037	80000	10	40043	40043	40043	40043	40052
80024	40042	304	0	0	0	0	0	0	3	1	40034	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	49	36960	40042	40042	29977	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	80002	0	855	80002	0	0	0	5020	28	16	14	25	40039	80000	10	40043	40043	40043	40043	40051
80024	40042	300	0	0	0	0	0	0	3	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839856	1	49	36960	40042	40050	29985	3	30022	80010	22	80000	20	240000	40049	40049	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	80002	0	194	80000	2	34	0	5020	22	16	25	15	40039	80000	10	40050	40043	40043	40043	40051
80024	40042	300	0	0	0	0	0	0	0	0	40583	16	0	0	25	80010	10	80000	10	80000	50	1839424	1	49	36962	40042	40042	29975	3	30030	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	80002	0	0	80002	2	34	0	5020	13	16	25	15	40039	80000	10	40041	40043	40050	40043	40050
80024	40043	300	0	0	0	0	0	0	6	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	1	49	36970	40042	40040	29977	3	30029	80010	20	80000	20	240000	40042	40049	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	80002	1	3	80002	2	34	0	5020	15	16	27	15	40037	80000	10	40043	40043	40043	40041	40051
80024	40040	300	0	0	0	0	0	0	3	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	1	49	36962	40042	40042	29975	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	80002	7	11	80002	2	34	0	5020	20	16	27	21	40039	80000	10	40050	40043	40051	40043	40043
80024	40042	300	0	0	0	0	4	0	9	1	40027	16	16	3	55	80070	10	80060	10	80000	50	1839424	1	49	36962	40050	40042	29984	3	30022	80010	20	80000	20	240000	40050	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	80000	0	2	80002	2	34	0	5020	26	16	14	26	40039	80000	10	40051	40043	40051	40043	40043
80024	40042	300	0	0	0	0	0	6	6	1	40027	0	16	0	25	80010	10	80000	10	80000	50	1839856	1	49	36962	40042	40051	29986	3	30022	80010	20	80000	20	240000	40051	40050	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	80000	12	2	80002	2	34	0	5020	15	16	27	27	40037	80000	10	40043	40041	40052	40043	40043
80024	40040	300	0	0	0	0	0	0	3	1	40036	16	0	0	25	80010	10	80000	10	80000	50	1839424	1	49	36971	40042	40040	29977	55	30031	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	80002	0	2	80002	2	34	0	5020	28	16	27	26	40048	80000	10	40043	40043	40043	40596	40051
80024	40040	299	0	0	0	0	0	0	3	0	40027	16	16	0	145	80010	10	80000	10	80000	50	1839856	0	49	36962	40042	40040	29977	29	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	80002	4	5	80002	2	34	0	5020	20	16	27	18	40037	80000	10	40043	40054	40043	40052	40050

STR (register, uxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations