Firestorm: MSR (FPSR) measurements

Code:

  msr fpsr, x0

Initialization

  mrs x0, fpsr

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	82	83	flush restart other nonspec (84)	85	inst all (8c)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	12027	93	15	0	12012	26	49	8957	12027	12027	11630	3	11743	12027	12027	1	1	1001	0	73	1	158	1	1	12024	12028	12028	12028	12028	12028
1004	12027	93	0	0	12012	26	49	8957	12027	12027	11630	3	11743	12027	12027	1	1	1001	0	73	1	158	1	1	12024	12028	12028	12028	12028	12028
1004	12027	93	0	0	12012	26	49	8957	12027	12027	11630	3	11743	12027	12027	1	1	1001	0	73	1	158	1	1	12024	12028	12028	12028	12028	12028
1004	12027	93	0	0	12012	26	49	8957	12027	12027	11630	3	11743	12027	12027	1	1	1001	0	73	1	158	1	1	12024	12028	12028	12028	12028	12028
1004	12027	93	0	0	12012	26	49	8957	12027	12027	11630	3	11743	12027	12027	1	1	1001	0	73	1	158	1	1	12024	12028	12028	12028	12028	12028
1004	12027	93	18	0	12012	26	49	8957	12027	12027	11630	3	11743	12027	12027	1	1	1001	0	73	1	158	1	1	12024	12028	12028	12028	12028	12028
1004	12027	93	213	0	12012	26	49	8957	12027	12027	11630	3	11743	12027	12027	1	1	1001	0	73	1	158	1	1	12024	12028	12028	12028	12028	12028
1004	12027	93	3	0	12012	26	49	8957	12027	12027	11630	3	11743	12027	12027	1	1	1001	0	73	1	158	1	1	12024	12028	12028	12028	12028	12028
1004	12027	94	33	0	12012	26	49	8957	12027	12027	11630	3	11743	12027	12027	1	1	1001	0	86	1	158	1	1	12024	12028	12028	12028	12028	12028
1004	12027	93	0	0	12012	26	49	8957	12027	12027	11630	3	11743	12027	12027	1	1	1001	0	73	1	158	1	1	12024	12028	12028	12028	12028	12028

Code:

  msr fpsr, x0

Initialization

  mrs x0, fpsr

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
10204	120063	931	0	0	0	12	0	0	120020	26	100	100	100	500	0	49	116965	0	120035	120035	118606	7	118719	100	200	200	120035	95759	1	1	10201	100	99	100	100	100	0	0	0	0	0	3	1	1	1	719	0	34	0	0	120032	100	120036	120036	120036	120036	120036
10204	120035	931	0	0	0	0	0	0	120020	26	100	100	100	500	0	49	116965	0	120035	120035	118606	7	118719	100	200	200	120035	120232	9	1	10201	100	99	100	100	100	0	0	0	0	0	0	1	1	1	719	0	34	0	0	120032	100	120036	120036	120036	120036	120036
10204	120035	931	0	0	0	12	0	0	120020	26	100	100	100	500	0	49	116965	0	120035	120035	118606	7	118719	100	200	200	120035	95759	1	1	10201	100	99	100	100	100	0	0	0	0	0	0	1	1	1	719	0	34	0	0	120032	100	120036	120036	120036	120036	120036
10204	120035	930	0	0	0	0	0	0	120020	26	100	100	100	500	0	49	116965	0	120035	120035	118606	7	118719	100	200	200	120035	95759	1	1	10201	100	99	100	100	100	0	0	0	0	0	3	1	1	1	719	0	34	0	0	120032	100	120036	120036	120036	120036	120036
10204	120035	930	0	0	0	0	0	0	120019	26	100	100	100	500	0	49	116964	3	120035	120035	118606	7	118719	100	200	200	120035	95759	1	1	10201	100	99	100	100	100	0	0	0	0	0	0	1	1	1	719	0	34	0	0	120032	100	120036	120036	120036	120036	120036
10204	120035	930	0	0	0	0	0	0	120020	26	100	100	100	500	0	49	116965	0	120035	120035	118606	7	118719	100	200	200	120035	95759	1	1	10201	100	99	100	100	100	0	0	0	0	0	0	1	1	1	719	0	34	0	0	120032	100	120036	120036	120036	120036	120036
10204	120035	930	0	0	0	0	0	0	120020	26	100	100	100	500	0	49	116965	0	120035	120035	118606	7	118719	100	200	200	120035	95759	1	1	10201	100	99	100	100	100	0	0	0	0	0	0	1	1	1	719	0	34	0	0	120032	100	120036	120036	120036	120036	120036
10204	120035	931	0	0	0	105	0	0	120020	26	100	100	100	500	0	49	116964	0	120034	120034	118380	6	118493	100	200	200	120034	95759	1	1	10201	100	99	100	100	100	0	0	0	0	0	0	1	1	1	719	0	34	0	0	120032	100	120036	120036	120036	120036	120036
10204	120035	931	0	0	0	0	0	0	120020	26	100	100	100	500	1	49	116965	0	120035	120035	118606	7	118719	100	200	200	120035	95759	1	1	10201	100	99	100	100	100	0	0	0	0	0	3	1	1	1	719	0	34	0	0	120032	100	120036	120036	120036	120036	120036
10204	120035	931	0	0	0	0	0	0	120020	26	100	100	100	500	0	49	116965	0	120035	120035	118606	7	118719	100	200	200	120035	95759	1	1	10201	100	99	100	100	100	0	0	0	0	0	3	1	1	1	719	0	34	0	0	120032	100	120036	120036	120036	120036	120036

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0027

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	eb	? int retires (ef)	f5	f6	f7	f8	fd
10024	120042	930	0	0	0	0	0	120012	26	10	10	10	50	0	49	116957	0	120027	120027	118514	3	118627	10	20	20	120027	120027	1	1	10021	10	9	0	10	10	10	0	1	0	3	0	0	640	2	146	2	2	120024	0	10	120028	120028	120028	120028	120028
10024	120027	931	0	0	0	0	0	120012	26	10	10	10	50	1	49	116957	0	120027	120027	118514	3	118627	10	20	20	120027	120027	1	1	10021	10	9	0	10	10	10	0	0	0	0	0	1	640	2	146	2	2	120024	0	10	120028	120028	120028	120028	120028
10024	120027	930	0	0	0	0	0	120012	26	10	10	10	50	1	49	116957	0	120027	120027	118514	3	118627	10	20	20	120027	120027	1	1	10021	10	9	0	10	10	10	0	0	0	0	0	0	640	2	146	2	2	120024	0	10	120028	120028	120028	120028	120028
10024	120027	930	0	0	0	0	0	120012	26	10	10	10	50	1	49	116957	0	120027	120027	118514	3	118627	10	20	20	120027	120027	1	1	10021	10	9	0	10	10	10	0	0	0	0	0	0	640	2	146	2	2	120024	0	10	120028	120028	120028	120028	120028
10024	120027	930	0	0	0	0	672	120012	26	10	10	10	50	1	49	116957	0	120027	120027	118514	3	118627	10	20	20	120027	120027	1	1	10021	10	9	0	10	10	10	0	0	0	0	0	0	640	2	146	2	2	120024	0	10	120028	120028	120028	120028	120028
10024	120058	930	0	0	0	0	0	120012	26	10	10	10	50	0	49	116957	0	120027	120027	118514	3	118627	10	20	20	120027	120027	1	1	10021	10	9	0	10	10	10	0	0	0	3	0	0	640	2	146	2	2	120024	0	10	120028	120028	120028	120028	120028
10024	120027	931	0	0	0	0	12	120012	26	10	10	10	50	0	49	116957	0	120027	120027	118514	3	118627	10	20	20	120027	120027	1	1	10021	10	9	0	10	10	10	0	0	0	3	0	0	640	2	146	2	2	120024	0	10	120028	120028	120028	120028	120028
10024	120027	930	0	0	0	0	0	120012	26	10	10	10	50	1	49	116957	0	120027	120027	118514	3	118627	10	20	20	120027	120027	1	1	10021	10	9	0	10	10	10	0	0	0	6	0	0	640	2	146	2	2	120024	0	10	120028	120028	120028	120028	120028
10024	120027	930	0	0	0	0	12	120012	26	10	10	10	50	1	49	116957	0	120027	120027	118514	3	118627	10	20	20	120027	120027	1	1	10021	10	9	0	10	10	10	0	0	0	3	0	1	640	2	146	2	2	120024	0	10	120028	120028	120028	120028	120028
10024	120027	930	0	0	0	0	0	120012	26	10	10	10	50	0	49	116957	0	120027	120027	118514	3	118627	10	20	20	120027	120027	1	1	10021	10	9	0	10	10	10	0	1	0	0	0	0	640	2	146	2	2	120024	0	10	120028	120028	120028	120028	120028

MSR (FPSR)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations