Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MSR (FPSR)

Test 1: uops

Code:

  msr fpsr, x0
  mrs x0, fpsr

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e1f3f51696a6d6emap stall dispatch (70)map rewind (75)map stall (76)8283flush restart other nonspec (84)85inst all (8c)accfd5map dispatch bubble (d6)ddfetch restart (de)e0f5f6f7f8fd
1004120279315012012264989571202712027116303117431202712027111001073115811120241202812028120281202812028
100412027930012012264989571202712027116303117431202712027111001073115811120241202812028120281202812028
100412027930012012264989571202712027116303117431202712027111001073115811120241202812028120281202812028
100412027930012012264989571202712027116303117431202712027111001073115811120241202812028120281202812028
100412027930012012264989571202712027116303117431202712027111001073115811120241202812028120281202812028
1004120279318012012264989571202712027116303117431202712027111001073115811120241202812028120281202812028
10041202793213012012264989571202712027116303117431202712027111001073115811120241202812028120281202812028
100412027933012012264989571202712027116303117431202712027111001073115811120241202812028120281202812028
1004120279433012012264989571202712027116303117431202712027111001086115811120241202812028120281202812028
100412027930012012264989571202712027116303117431202712027111001073115811120241202812028120281202812028

Test 2: throughput

Code:

  msr fpsr, x0
  mrs x0, fpsr

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0035

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int retires (ef)f5f6f7f8fd
10204120063931000120012002026100100100500049116965012003512003511860671187191002002001200359575911102011009910010010000000311171903400120032100120036120036120036120036120036
10204120035931000000120020261001001005000491169650120035120035118606711871910020020012003512023291102011009910010010000000011171903400120032100120036120036120036120036120036
10204120035931000120012002026100100100500049116965012003512003511860671187191002002001200359575911102011009910010010000000011171903400120032100120036120036120036120036120036
1020412003593000000012002026100100100500049116965012003512003511860671187191002002001200359575911102011009910010010000000311171903400120032100120036120036120036120036120036
1020412003593000000012001926100100100500049116964312003512003511860671187191002002001200359575911102011009910010010000000011171903400120032100120036120036120036120036120036
1020412003593000000012002026100100100500049116965012003512003511860671187191002002001200359575911102011009910010010000000011171903400120032100120036120036120036120036120036
1020412003593000000012002026100100100500049116965012003512003511860671187191002002001200359575911102011009910010010000000011171903400120032100120036120036120036120036120036
102041200359310001050012002026100100100500049116964012003412003411838061184931002002001200349575911102011009910010010000000011171903400120032100120036120036120036120036120036
1020412003593100000012002026100100100500149116965012003512003511860671187191002002001200359575911102011009910010010000000311171903400120032100120036120036120036120036120036
1020412003593100000012002026100100100500049116965012003512003511860671187191002002001200359575911102011009910010010000000311171903400120032100120036120036120036120036120036

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0027

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)191e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? int retires (ef)f5f6f7f8fd
100241200429300000012001226101010500491169570120027120027118514311862710202012002712002711100211090101010010300640214622120024010120028120028120028120028120028
100241200279310000012001226101010501491169570120027120027118514311862710202012002712002711100211090101010000001640214622120024010120028120028120028120028120028
100241200279300000012001226101010501491169570120027120027118514311862710202012002712002711100211090101010000000640214622120024010120028120028120028120028120028
100241200279300000012001226101010501491169570120027120027118514311862710202012002712002711100211090101010000000640214622120024010120028120028120028120028120028
10024120027930000067212001226101010501491169570120027120027118514311862710202012002712002711100211090101010000000640214622120024010120028120028120028120028120028
100241200589300000012001226101010500491169570120027120027118514311862710202012002712002711100211090101010000300640214622120024010120028120028120028120028120028
1002412002793100001212001226101010500491169570120027120027118514311862710202012002712002711100211090101010000300640214622120024010120028120028120028120028120028
100241200279300000012001226101010501491169570120027120027118514311862710202012002712002711100211090101010000600640214622120024010120028120028120028120028120028
1002412002793000001212001226101010501491169570120027120027118514311862710202012002712002711100211090101010000301640214622120024010120028120028120028120028120028
100241200279300000012001226101010500491169570120027120027118514311862710202012002712002711100211090101010010000640214622120024010120028120028120028120028120028