Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ldp w0, w1, [x6, #8]
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires: 2.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | 0e | 0f | 1e | 22 | 24 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 60 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int load (95) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 2005 | 394 | 3 | 0 | 0 | 45 | 1 | 0 | 1 | 386 | 2 | 12 | 0 | 19 | 25 | 1000 | 1000 | 1000 | 14075 | 1 | 394 | 374 | 92 | 3 | 127 | 1000 | 2000 | 1000 | 398 | 35 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 0 | 1038 | 0 | 1038 | 6 | 0 | 40 | 0 | 73 | 3 | 16 | 1 | 1 | 395 | 14 | 10 | 7 | 1000 | 1000 | 399 | 399 | 375 | 395 | 399 |
| 2004 | 398 | 2 | 1 | 0 | 44 | 0 | 0 | 1 | 384 | 2 | 0 | 1 | 19 | 25 | 1000 | 1000 | 1000 | 15065 | 1 | 374 | 398 | 76 | 3 | 127 | 1000 | 2000 | 1000 | 398 | 35 | 1 | 1 | 1001 | 1000 | 1000 | 1 | 1000 | 43 | 1039 | 0 | 1039 | 6 | 1 | 0 | 44 | 73 | 1 | 16 | 1 | 1 | 395 | 10 | 10 | 0 | 1000 | 1000 | 399 | 399 | 395 | 375 | 399 |
| 2004 | 398 | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 359 | 2 | 12 | 1 | 19 | 25 | 1000 | 1000 | 1000 | 15288 | 1 | 398 | 394 | 72 | 3 | 127 | 1000 | 2000 | 1000 | 398 | 35 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 43 | 1039 | 0 | 1039 | 0 | 1 | 39 | 44 | 73 | 1 | 16 | 1 | 1 | 395 | 0 | 14 | 7 | 1000 | 1000 | 375 | 395 | 375 | 399 | 399 |
| 2004 | 374 | 2 | 0 | 0 | 45 | 0 | 0 | 0 | 359 | 2 | 12 | 0 | 0 | 25 | 1000 | 1000 | 1000 | 15284 | 1 | 398 | 398 | 92 | 3 | 131 | 1000 | 2000 | 1000 | 374 | 35 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 43 | 1000 | 0 | 1038 | 0 | 1 | 38 | 0 | 73 | 1 | 16 | 1 | 1 | 395 | 14 | 14 | 7 | 1000 | 1000 | 375 | 399 | 395 | 375 | 399 |
| 2004 | 397 | 3 | 1 | 1 | 44 | 0 | 0 | 0 | 379 | 0 | 1 | 12 | 19 | 25 | 1000 | 1000 | 1000 | 15288 | 1 | 374 | 374 | 96 | 3 | 107 | 1000 | 2000 | 1000 | 394 | 35 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 43 | 1000 | 0 | 1038 | 0 | 1 | 38 | 0 | 73 | 1 | 16 | 1 | 1 | 395 | 14 | 0 | 7 | 1000 | 1000 | 395 | 395 | 395 | 375 | 377 |
| 2004 | 394 | 2 | 0 | 0 | 45 | 1 | 0 | 1 | 379 | 2 | 0 | 0 | 16 | 25 | 1000 | 1000 | 1000 | 14075 | 1 | 374 | 398 | 72 | 3 | 131 | 1000 | 2000 | 1000 | 398 | 35 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 43 | 1039 | 38 | 1038 | 6 | 1 | 38 | 0 | 73 | 1 | 16 | 1 | 1 | 395 | 10 | 10 | 4 | 1000 | 1000 | 375 | 375 | 399 | 375 | 375 |
| 2004 | 398 | 3 | 0 | 0 | 44 | 1 | 0 | 0 | 383 | 2 | 0 | 1 | 0 | 25 | 1000 | 1000 | 1000 | 15294 | 1 | 398 | 374 | 72 | 3 | 107 | 1000 | 2000 | 1000 | 398 | 35 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 43 | 1038 | 38 | 1038 | 6 | 1 | 38 | 43 | 73 | 2 | 16 | 2 | 2 | 395 | 14 | 10 | 4 | 1000 | 1000 | 399 | 399 | 399 | 375 | 399 |
| 2004 | 374 | 3 | 0 | 0 | 44 | 0 | 0 | 1 | 359 | 2 | 1 | 1 | 0 | 25 | 1000 | 1000 | 1000 | 14075 | 1 | 398 | 394 | 72 | 3 | 131 | 1000 | 2000 | 1000 | 374 | 35 | 1 | 1 | 1001 | 1000 | 1000 | 1 | 1000 | 43 | 1038 | 41 | 1038 | 6 | 1 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 391 | 14 | 0 | 7 | 1000 | 1000 | 399 | 375 | 399 | 400 | 375 |
| 2004 | 374 | 2 | 1 | 1 | 44 | 1 | 0 | 1 | 359 | 2 | 1 | 1 | 0 | 25 | 1000 | 1000 | 1000 | 15284 | 1 | 398 | 374 | 92 | 3 | 131 | 1000 | 2000 | 1000 | 374 | 35 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 43 | 1000 | 42 | 1038 | 0 | 1 | 0 | 44 | 73 | 1 | 16 | 1 | 1 | 391 | 14 | 0 | 7 | 1000 | 1000 | 399 | 375 | 399 | 399 | 375 |
| 2004 | 398 | 2 | 0 | 1 | 45 | 0 | 0 | 0 | 384 | 2 | 12 | 0 | 19 | 25 | 1000 | 1000 | 1000 | 15288 | 1 | 398 | 374 | 92 | 3 | 131 | 1000 | 2000 | 1000 | 398 | 35 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 0 | 1039 | 38 | 1039 | 6 | 1 | 0 | 44 | 73 | 1 | 16 | 1 | 1 | 371 | 14 | 10 | 0 | 1000 | 1000 | 375 | 395 | 399 | 395 | 399 |
Chain cycles: 3
Code:
ldp w0, w1, [x6, #8] eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 4.0050
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 18 | 1e | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | c2 | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 50205 | 70047 | 525 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 70032 | 69714 | 59700 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 613652 | 3342056 | 0 | 49 | 66973 | 70035 | 70035 | 63405 | 3 | 63695 | 40100 | 30200 | 20000 | 60200 | 10000 | 70050 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 2610 | 2 | 64 | 1 | 1 | 69813 | 30003 | 6 | 6 | 0 | 10000 | 40100 | 70051 | 70051 | 70048 | 70048 | 70051 |
| 50204 | 70050 | 524 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70035 | 69714 | 59684 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 613915 | 3341304 | 0 | 49 | 67061 | 70048 | 70055 | 63388 | 3 | 63710 | 40100 | 30200 | 20000 | 60200 | 10000 | 70035 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 1 | 0 | 10000 | 1 | 0 | 0 | 0 | 0 | 2610 | 1 | 64 | 1 | 1 | 69813 | 30003 | 6 | 6 | 9 | 10000 | 40100 | 70051 | 70051 | 70051 | 70051 | 70051 |
| 50204 | 70035 | 525 | 0 | 0 | 0 | 0 | 0 | 28 | 1 | 0 | 70032 | 69711 | 59684 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 613915 | 3342056 | 0 | 49 | 66973 | 70051 | 70053 | 63388 | 3 | 63707 | 40100 | 30200 | 20000 | 60200 | 10000 | 70050 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 1 | 3 | 10000 | 1 | 0 | 1 | 0 | 0 | 2610 | 1 | 64 | 1 | 1 | 69813 | 30003 | 6 | 6 | 0 | 10000 | 40100 | 70051 | 70051 | 70036 | 70051 | 70048 |
| 50204 | 70050 | 525 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70035 | 69698 | 59694 | 25 | 40100 | 30100 | 10000 | 30100 | 10000 | 613915 | 3342152 | 0 | 49 | 66967 | 70052 | 70053 | 63403 | 3 | 63710 | 40100 | 30200 | 20000 | 60200 | 10000 | 70050 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 12 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 2610 | 1 | 64 | 1 | 1 | 69813 | 30003 | 9 | 0 | 9 | 10000 | 40100 | 70048 | 70048 | 70053 | 70051 | 70036 |
| 50204 | 70050 | 525 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70035 | 69714 | 59700 | 25 | 40100 | 30103 | 10000 | 30100 | 10000 | 613915 | 3342056 | 0 | 49 | 66967 | 70037 | 70051 | 63388 | 3 | 63710 | 40100 | 30200 | 20000 | 60200 | 10000 | 70035 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 0 | 0 | 1 | 0 | 0 | 2610 | 1 | 64 | 1 | 1 | 69818 | 30000 | 0 | 6 | 0 | 10000 | 40100 | 70051 | 70051 | 70051 | 70051 | 70051 |
| 50204 | 70035 | 524 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 70020 | 69698 | 59700 | 25 | 40104 | 30100 | 10000 | 30100 | 10000 | 613652 | 3342056 | 0 | 49 | 67043 | 70054 | 70050 | 63388 | 3 | 63710 | 40100 | 30200 | 20000 | 60200 | 10000 | 70047 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 2610 | 1 | 64 | 1 | 1 | 69810 | 30003 | 9 | 6 | 0 | 10000 | 40100 | 70051 | 70051 | 70053 | 70051 | 70051 |
| 50204 | 70050 | 525 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70035 | 69714 | 59684 | 25 | 40100 | 30103 | 10001 | 30100 | 10000 | 613652 | 3341304 | 0 | 49 | 67049 | 70055 | 70047 | 63388 | 3 | 63695 | 40100 | 30200 | 20000 | 60200 | 10000 | 70035 | 37 | 2 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 0 | 0 | 1 | 0 | 0 | 2610 | 1 | 64 | 1 | 1 | 69810 | 30003 | 9 | 0 | 0 | 10000 | 40100 | 70051 | 70051 | 70036 | 70036 | 70036 |
| 50204 | 70050 | 524 | 0 | 0 | 0 | 0 | 4 | 10 | 1 | 0 | 70020 | 69698 | 59700 | 25 | 40100 | 30103 | 10001 | 30100 | 10000 | 613915 | 3342056 | 0 | 49 | 66967 | 70062 | 70038 | 63400 | 3 | 63695 | 40100 | 30200 | 20000 | 60200 | 10000 | 70050 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 2610 | 1 | 64 | 1 | 1 | 69813 | 30000 | 0 | 6 | 0 | 10000 | 40100 | 70051 | 70036 | 70051 | 70051 | 70048 |
| 50204 | 70047 | 525 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 70032 | 69711 | 59684 | 25 | 40100 | 30103 | 10001 | 30100 | 10000 | 613915 | 3342056 | 0 | 49 | 66967 | 70036 | 70092 | 63403 | 3 | 63710 | 40100 | 30200 | 20000 | 60200 | 10000 | 70035 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 2610 | 1 | 64 | 1 | 1 | 69798 | 30003 | 6 | 6 | 9 | 10000 | 40100 | 70051 | 70120 | 70051 | 70036 | 70036 |
| 50204 | 70050 | 524 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70035 | 69714 | 59700 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 613652 | 3342056 | 0 | 49 | 66967 | 70047 | 70051 | 63403 | 3 | 63707 | 40100 | 30200 | 20000 | 60200 | 10000 | 70050 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 0 | 2610 | 1 | 64 | 1 | 1 | 69813 | 30003 | 9 | 9 | 0 | 10000 | 40100 | 70051 | 70036 | 70051 | 70051 | 70036 |
Result (median cycles for code, minus 3 chain cycles): 4.0051
| retire uop (01) | cycle (02) | 03 | 0e | 0f | 18 | 19 | 1e | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 5f | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | b5 | l1d cache miss ld nonspec (bf) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 50025 | 70057 | 525 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 70036 | 69715 | 59693 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 615145 | 3342095 | 0 | 0 | 49 | 66971 | 70051 | 70051 | 63403 | 3 | 63719 | 40010 | 30020 | 20000 | 60020 | 10000 | 70035 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 3 | 10000 | 1 | 1 | 0 | 0 | 2521 | 2 | 78 | 2 | 2 | 69818 | 30003 | 10 | 10 | 10 | 10000 | 40010 | 70052 | 70052 | 70052 | 70052 | 70052 |
| 50024 | 70051 | 524 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 70036 | 69715 | 59693 | 25 | 40010 | 30013 | 10001 | 30010 | 10000 | 614994 | 3342095 | 0 | 0 | 49 | 66971 | 70051 | 70051 | 63419 | 3 | 63719 | 40010 | 30020 | 20000 | 60020 | 10000 | 70035 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 2521 | 2 | 78 | 2 | 2 | 69818 | 30003 | 10 | 0 | 10 | 10000 | 40010 | 70052 | 70036 | 70052 | 70052 | 70052 |
| 50024 | 70035 | 524 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 70036 | 69715 | 59693 | 25 | 40010 | 30010 | 10000 | 30010 | 10000 | 615145 | 3341295 | 0 | 0 | 49 | 66971 | 70051 | 70035 | 63419 | 3 | 63719 | 40010 | 30020 | 20000 | 60020 | 10000 | 70051 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 2521 | 3 | 78 | 3 | 2 | 69818 | 30003 | 10 | 10 | 10 | 10000 | 40010 | 70052 | 70053 | 70053 | 70052 | 70052 |
| 50024 | 70051 | 525 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70036 | 69719 | 59677 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 615145 | 3342095 | 0 | 0 | 49 | 66955 | 70035 | 70051 | 63419 | 3 | 63719 | 40010 | 30020 | 20000 | 60020 | 10000 | 70051 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10000 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 2521 | 2 | 78 | 2 | 3 | 69818 | 30000 | 10 | 10 | 10 | 10000 | 40010 | 70037 | 70052 | 70052 | 70052 | 70052 |
| 50024 | 70051 | 525 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70036 | 69719 | 59677 | 25 | 40014 | 30010 | 10001 | 30010 | 10000 | 615145 | 3342095 | 0 | 0 | 49 | 66971 | 70051 | 70051 | 63419 | 3 | 63682 | 40010 | 30020 | 20000 | 60020 | 10000 | 70051 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 1 | 0 | 10000 | 1 | 0 | 0 | 0 | 2521 | 2 | 78 | 3 | 2 | 69818 | 30003 | 10 | 0 | 10 | 10000 | 40010 | 70081 | 70053 | 70040 | 70052 | 70052 |
| 50024 | 70051 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 70020 | 69715 | 59693 | 25 | 40010 | 30013 | 10001 | 30010 | 10000 | 615145 | 3342095 | 1 | 1 | 49 | 63941 | 70051 | 70051 | 63403 | 3 | 63719 | 40010 | 30020 | 20000 | 60020 | 10000 | 70051 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 3 | 10000 | 1 | 1 | 0 | 0 | 2521 | 2 | 78 | 3 | 2 | 69819 | 30003 | 10 | 10 | 10 | 10000 | 40010 | 70052 | 70056 | 70036 | 70054 | 70058 |
| 50024 | 70051 | 525 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 70020 | 69715 | 59693 | 25 | 40014 | 30013 | 10000 | 30010 | 10000 | 615145 | 3342095 | 0 | 0 | 49 | 66971 | 70051 | 70051 | 63419 | 3 | 63719 | 40010 | 30020 | 20000 | 60020 | 10000 | 70051 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 2521 | 2 | 99 | 2 | 2 | 69818 | 30003 | 10 | 0 | 10 | 10000 | 40010 | 70036 | 70052 | 70036 | 70052 | 70052 |
| 50024 | 70051 | 525 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70036 | 69715 | 59693 | 25 | 40014 | 30010 | 10001 | 30010 | 10000 | 615145 | 3342095 | 0 | 0 | 49 | 66971 | 70051 | 70051 | 63419 | 3 | 63719 | 40010 | 30020 | 20000 | 60020 | 10000 | 70051 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 3 | 10000 | 0 | 1 | 0 | 0 | 2521 | 2 | 78 | 3 | 2 | 69801 | 30003 | 10 | 10 | 0 | 10000 | 40010 | 70052 | 70036 | 70052 | 70052 | 70052 |
| 50024 | 70051 | 525 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 70020 | 69716 | 59693 | 25 | 40014 | 30013 | 10000 | 30010 | 10000 | 615145 | 3342095 | 1 | 0 | 49 | 66955 | 70051 | 70051 | 63419 | 3 | 63719 | 40010 | 30020 | 20000 | 60020 | 10000 | 70051 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 2521 | 2 | 99 | 2 | 2 | 69818 | 30003 | 10 | 10 | 0 | 10000 | 40010 | 70052 | 70052 | 70052 | 70052 | 70052 |
| 50024 | 70051 | 525 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70036 | 69715 | 59693 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 615145 | 3342095 | 1 | 0 | 49 | 66971 | 70051 | 70051 | 63419 | 3 | 63719 | 40220 | 30020 | 20000 | 60020 | 10000 | 70051 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10000 | 1 | 10000 | 0 | 0 | 3 | 10000 | 1 | 0 | 0 | 0 | 2521 | 2 | 99 | 3 | 2 | 69818 | 30003 | 10 | 10 | 10 | 10000 | 40010 | 70053 | 70052 | 70052 | 70052 | 70052 |
Chain cycles: 3
Code:
ldp w0, w1, [x6, #8] eor x8, x8, x1 eor x8, x8, x1 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 4.0054
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | 0e | 0f | 18 | 19 | 1e | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | l1d cache miss ld nonspec (bf) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 50205 | 70057 | 525 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 70020 | 69715 | 59703 | 25 | 40100 | 30103 | 10001 | 30100 | 10000 | 613930 | 3341304 | 1 | 49 | 66974 | 70054 | 70051 | 63404 | 0 | 3 | 63714 | 40100 | 30200 | 20000 | 60200 | 10000 | 70035 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 2610 | 2 | 64 | 1 | 1 | 69814 | 30003 | 0 | 10 | 0 | 10000 | 40100 | 70055 | 70055 | 70055 | 70040 | 70036 |
| 50204 | 70054 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 70039 | 69715 | 59700 | 25 | 40100 | 30103 | 10000 | 30100 | 10000 | 613888 | 3342250 | 1 | 49 | 66974 | 70054 | 70054 | 63407 | 0 | 3 | 63695 | 40100 | 30200 | 20000 | 60200 | 10000 | 70051 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 2610 | 1 | 64 | 1 | 1 | 69798 | 30000 | 13 | 13 | 10 | 10000 | 40100 | 70055 | 70055 | 70036 | 70052 | 70055 |
| 50204 | 70035 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 70020 | 69719 | 59703 | 25 | 40100 | 30100 | 10001 | 30100 | 10000 | 613888 | 3342250 | 1 | 49 | 66974 | 70051 | 70054 | 63404 | 0 | 3 | 63714 | 40100 | 30200 | 20000 | 60200 | 10000 | 70054 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 2610 | 1 | 64 | 1 | 1 | 69798 | 30003 | 0 | 13 | 13 | 10000 | 40100 | 70055 | 70060 | 70036 | 70052 | 70036 |
| 50204 | 70035 | 525 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 70036 | 69715 | 59703 | 25 | 40100 | 30100 | 10001 | 30100 | 10000 | 613930 | 3342104 | 1 | 49 | 66971 | 70054 | 70035 | 63404 | 0 | 3 | 63714 | 40100 | 30200 | 20000 | 60200 | 10000 | 70054 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 2610 | 1 | 64 | 1 | 1 | 69817 | 30003 | 13 | 0 | 13 | 10000 | 40100 | 70055 | 70055 | 70052 | 70055 | 70036 |
| 50204 | 70035 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 70020 | 69715 | 59703 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 613888 | 3342250 | 1 | 49 | 66974 | 70054 | 70054 | 63388 | 0 | 3 | 63695 | 40100 | 30200 | 20000 | 60200 | 10000 | 70116 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 2610 | 1 | 64 | 1 | 1 | 69817 | 30003 | 10 | 10 | 10 | 10000 | 40100 | 70055 | 70052 | 70052 | 70036 | 70036 |
| 50204 | 70035 | 524 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 70039 | 69715 | 59703 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 613679 | 3341304 | 1 | 49 | 66974 | 70051 | 70051 | 63388 | 0 | 3 | 63695 | 40100 | 30200 | 20000 | 60200 | 10000 | 70035 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10003 | 1 | 0 | 0 | 2610 | 1 | 64 | 1 | 1 | 69798 | 30000 | 10 | 0 | 13 | 10000 | 40100 | 70036 | 70055 | 70036 | 70055 | 70036 |
| 50204 | 70035 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 70020 | 69698 | 59684 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 613930 | 3342250 | 1 | 49 | 66955 | 70051 | 70035 | 63407 | 0 | 3 | 63695 | 40100 | 30200 | 20000 | 60200 | 10000 | 70051 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 0 | 2610 | 1 | 64 | 1 | 1 | 69798 | 30003 | 0 | 13 | 0 | 10000 | 40100 | 70052 | 70055 | 70055 | 70052 | 70055 |
| 50204 | 70035 | 524 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70060 | 69730 | 59684 | 25 | 40104 | 30100 | 10001 | 30100 | 10000 | 613888 | 3342250 | 1 | 49 | 66955 | 70074 | 70107 | 63408 | 0 | 3 | 63695 | 40100 | 30200 | 20000 | 60200 | 10000 | 70051 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 2610 | 1 | 64 | 1 | 1 | 69817 | 30003 | 13 | 13 | 13 | 10000 | 40100 | 70055 | 70055 | 70036 | 70036 | 70055 |
| 50204 | 70051 | 524 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 70020 | 69719 | 59703 | 25 | 40100 | 30100 | 10001 | 30100 | 10000 | 613888 | 3342250 | 1 | 49 | 66974 | 70054 | 70051 | 63404 | 0 | 3 | 63714 | 40100 | 30200 | 20000 | 60200 | 10000 | 70051 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 2610 | 1 | 64 | 1 | 1 | 69798 | 30024 | 10 | 0 | 13 | 10000 | 40100 | 70036 | 70052 | 70052 | 70036 | 70036 |
| 50204 | 70035 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 70036 | 69698 | 59684 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 613930 | 3341304 | 1 | 49 | 66974 | 70054 | 70035 | 63388 | 0 | 3 | 63714 | 40100 | 30200 | 20000 | 60200 | 10000 | 70035 | 37 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 2610 | 1 | 64 | 1 | 1 | 69817 | 30000 | 13 | 13 | 0 | 10000 | 40100 | 70036 | 70106 | 70065 | 70036 | 70036 |
Result (median cycles for code, minus 3 chain cycles): 4.0054
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3a | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 5f | 60 | 69 | 6a | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cd | cf | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 50025 | 70057 | 525 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 70039 | 69715 | 59693 | 25 | 40010 | 30013 | 10002 | 30010 | 10000 | 615481 | 3341295 | 0 | 0 | 49 | 66973 | 0 | 70056 | 70035 | 63419 | 3 | 63719 | 40010 | 30020 | 20000 | 60020 | 10000 | 70051 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 0 | 0 | 2522 | 0 | 10 | 78 | 0 | 0 | 0 | 5 | 5 | 69818 | 30003 | 10 | 10 | 13 | 10000 | 40010 | 70036 | 70055 | 70036 | 70036 | 70052 |
| 50024 | 70051 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 70036 | 69719 | 59693 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 615145 | 3342095 | 0 | 0 | 49 | 66971 | 0 | 70054 | 70035 | 63422 | 3 | 63719 | 40010 | 30020 | 20000 | 60020 | 10000 | 70054 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 2520 | 0 | 6 | 78 | 0 | 0 | 0 | 5 | 5 | 69818 | 30003 | 13 | 10 | 10 | 10000 | 40010 | 70052 | 70055 | 70052 | 70052 | 70055 |
| 50024 | 70054 | 524 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 1 | 70042 | 69724 | 59710 | 25 | 40018 | 30013 | 10001 | 30010 | 10000 | 615508 | 3342398 | 0 | 1 | 49 | 66977 | 0 | 70058 | 70059 | 63429 | 3 | 63739 | 40010 | 30020 | 20000 | 60020 | 10000 | 70060 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10001 | 1 | 0 | 10001 | 0 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 1 | 0 | 2520 | 0 | 6 | 64 | 0 | 0 | 0 | 5 | 4 | 69820 | 30006 | 0 | 10 | 13 | 10000 | 40010 | 70058 | 70042 | 70058 | 70058 | 70061 |
| 50024 | 70060 | 525 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 1 | 70042 | 69722 | 59713 | 25 | 40018 | 30016 | 10002 | 30010 | 10000 | 615508 | 3341614 | 0 | 1 | 49 | 66977 | 0 | 70041 | 70057 | 63428 | 3 | 63742 | 40010 | 30020 | 20000 | 60020 | 10000 | 70060 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10003 | 3 | 1 | 10001 | 0 | 0 | 1 | 4 | 10000 | 1 | 1 | 1 | 1 | 0 | 0 | 2520 | 0 | 5 | 64 | 0 | 0 | 0 | 7 | 6 | 69820 | 30006 | 10 | 10 | 10 | 10000 | 40010 | 70058 | 70061 | 70061 | 70061 | 70061 |
| 50024 | 70057 | 525 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 1 | 70042 | 69725 | 59713 | 25 | 40018 | 30016 | 10002 | 30010 | 10000 | 615163 | 3341614 | 0 | 0 | 49 | 66961 | 0 | 70041 | 70057 | 63409 | 3 | 63742 | 40010 | 30020 | 20000 | 60020 | 10000 | 70057 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10004 | 4 | 1 | 10003 | 0 | 1 | 1 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 0 | 2520 | 0 | 5 | 64 | 0 | 0 | 0 | 5 | 5 | 69820 | 30006 | 13 | 0 | 13 | 10000 | 40010 | 70061 | 70058 | 70058 | 70058 | 70058 |
| 50024 | 70057 | 525 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 1 | 0 | 0 | 70042 | 69697 | 59695 | 25 | 40014 | 30016 | 10002 | 30010 | 10000 | 615508 | 3342398 | 0 | 0 | 49 | 66980 | 0 | 70060 | 70057 | 63425 | 3 | 63739 | 40010 | 30020 | 20000 | 60020 | 10000 | 70057 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10002 | 3 | 1 | 10001 | 1 | 1 | 2 | 1 | 10000 | 1 | 1 | 1 | 1 | 1 | 0 | 2520 | 0 | 7 | 64 | 0 | 0 | 0 | 5 | 5 | 69920 | 30006 | 10 | 10 | 10 | 10000 | 40010 | 70061 | 70058 | 70061 | 70042 | 70061 |
| 50024 | 70057 | 525 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 1 | 70042 | 69722 | 59710 | 25 | 40018 | 30016 | 10002 | 30010 | 10000 | 615508 | 3342398 | 0 | 0 | 49 | 66977 | 0 | 70057 | 70057 | 63425 | 3 | 63742 | 40010 | 30020 | 20000 | 60020 | 10000 | 70041 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10001 | 1 | 1 | 10002 | 0 | 0 | 0 | 1 | 10000 | 0 | 1 | 1 | 1 | 0 | 0 | 2520 | 0 | 5 | 65 | 0 | 0 | 0 | 5 | 5 | 69805 | 30006 | 10 | 10 | 10 | 10000 | 40010 | 70061 | 70058 | 70058 | 70058 | 70042 |
| 50024 | 70057 | 525 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 1 | 70042 | 69722 | 59695 | 25 | 40014 | 30013 | 10002 | 30010 | 10000 | 615535 | 3342398 | 0 | 0 | 49 | 66961 | 3 | 70060 | 70057 | 63428 | 3 | 63722 | 40010 | 30020 | 20000 | 60020 | 10000 | 70057 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10001 | 1 | 1 | 10003 | 0 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 0 | 2520 | 0 | 6 | 64 | 0 | 0 | 0 | 5 | 5 | 69820 | 30006 | 10 | 10 | 10 | 10000 | 40010 | 70058 | 70058 | 70058 | 70058 | 70061 |
| 50024 | 70060 | 525 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 70020 | 69719 | 59693 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 615145 | 3342095 | 0 | 0 | 49 | 66971 | 0 | 70051 | 70056 | 63403 | 3 | 63736 | 40010 | 30020 | 20000 | 60020 | 10000 | 70035 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 0 | 0 | 2520 | 0 | 5 | 99 | 0 | 0 | 0 | 5 | 5 | 69801 | 30003 | 0 | 0 | 13 | 10000 | 40010 | 70052 | 70052 | 70055 | 70052 | 70036 |
| 50024 | 70054 | 525 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 70039 | 69719 | 59693 | 25 | 40014 | 30010 | 10001 | 30010 | 10000 | 615145 | 3342095 | 0 | 0 | 49 | 66955 | 0 | 70051 | 70035 | 63419 | 3 | 63682 | 40010 | 30020 | 20000 | 60020 | 10000 | 70051 | 37 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 0 | 10000 | 0 | 0 | 1 | 0 | 0 | 0 | 2520 | 1 | 5 | 17 | 0 | 0 | 0 | 6 | 5 | 69818 | 30003 | 25 | 23 | 6 | 10000 | 40010 | 70036 | 70036 | 70055 | 70036 | 70052 |
Count: 8
Code:
ldp w0, w1, [x6, #8] ldp w0, w1, [x6, #8] ldp w0, w1, [x6, #8] ldp w0, w1, [x6, #8] ldp w0, w1, [x6, #8] ldp w0, w1, [x6, #8] ldp w0, w1, [x6, #8] ldp w0, w1, [x6, #8]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.3342
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | a5 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 160205 | 26736 | 200 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 176 | 0 | 1 | 0 | 3 | 26717 | 0 | 18 | 18 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167530 | 0 | 49 | 23652 | 26735 | 26736 | 6654 | 0 | 64 | 6811 | 80100 | 200 | 160000 | 200 | 80000 | 26714 | 35 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80020 | 20 | 42 | 0 | 80057 | 1 | 0 | 1 | 59 | 80038 | 6 | 1 | 57 | 42 | 19 | 2 | 0 | 5110 | 2 | 16 | 2 | 2 | 26740 | 0 | 9 | 0 | 2 | 80000 | 80100 | 26733 | 26733 | 26733 | 26733 | 26733 |
| 160204 | 26732 | 200 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 83 | 0 | 0 | 0 | 2 | 26717 | 2 | 18 | 18 | 15 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1169941 | 0 | 49 | 23652 | 26830 | 26737 | 6755 | 0 | 3 | 6690 | 80100 | 200 | 160000 | 200 | 80000 | 26732 | 35 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80019 | 20 | 0 | 0 | 80054 | 1 | 0 | 1 | 59 | 80000 | 0 | 0 | 57 | 42 | 19 | 2 | 0 | 5110 | 2 | 16 | 2 | 2 | 26729 | 0 | 0 | 9 | 2 | 80000 | 80100 | 26715 | 26733 | 26733 | 26733 | 26733 |
| 160204 | 26732 | 200 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 101 | 0 | 1 | 0 | 3 | 26700 | 2 | 0 | 18 | 15 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167530 | 1 | 49 | 23634 | 26835 | 26738 | 6670 | 0 | 3 | 6690 | 80100 | 200 | 160000 | 200 | 80000 | 26732 | 35 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80019 | 20 | 0 | 0 | 80057 | 0 | 0 | 0 | 59 | 80038 | 6 | 0 | 57 | 42 | 19 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26711 | 0 | 9 | 0 | 2 | 80000 | 80100 | 26733 | 26733 | 26733 | 26733 | 26733 |
| 160204 | 26732 | 200 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 39 | 0 | 0 | 0 | 3 | 26699 | 0 | 18 | 18 | 15 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1169154 | 0 | 49 | 23652 | 26831 | 26737 | 6668 | 0 | 3 | 6690 | 80100 | 200 | 160000 | 200 | 80000 | 26732 | 35 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80020 | 20 | 42 | 0 | 80057 | 1 | 0 | 2 | 21 | 80038 | 6 | 0 | 57 | 42 | 19 | 1 | 0 | 5110 | 2 | 16 | 2 | 2 | 26729 | 0 | 9 | 9 | 2 | 80000 | 80100 | 26733 | 26733 | 26733 | 26733 | 26733 |
| 160204 | 26732 | 200 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 80 | 0 | 1 | 0 | 2 | 26717 | 2 | 18 | 18 | 15 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167530 | 1 | 49 | 23641 | 27212 | 26724 | 6659 | 0 | 3 | 6698 | 80100 | 200 | 160000 | 200 | 80000 | 26732 | 35 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80020 | 19 | 42 | 0 | 80057 | 1 | 0 | 2 | 59 | 80038 | 6 | 1 | 57 | 0 | 19 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26711 | 0 | 9 | 9 | 2 | 80000 | 80100 | 26733 | 26733 | 26733 | 26733 | 26733 |
| 160204 | 26732 | 200 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 98 | 0 | 1 | 0 | 3 | 26717 | 2 | 18 | 18 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167371 | 0 | 49 | 23652 | 26809 | 26738 | 6657 | 117 | 3 | 6830 | 80100 | 200 | 160000 | 200 | 80000 | 26732 | 35 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80020 | 19 | 42 | 0 | 80057 | 1 | 0 | 1 | 59 | 80038 | 6 | 1 | 56 | 42 | 19 | 1 | 0 | 5110 | 2 | 16 | 2 | 2 | 26729 | 0 | 9 | 9 | 2 | 80000 | 80100 | 26733 | 26733 | 26733 | 26715 | 26736 |
| 160204 | 26714 | 200 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 83 | 0 | 0 | 0 | 2 | 26699 | 3 | 18 | 18 | 15 | 25 | 80100 | 100 | 80000 | 100 | 80192 | 500 | 1168757 | 0 | 49 | 23652 | 26838 | 26741 | 6692 | 0 | 3 | 6690 | 80100 | 200 | 160000 | 200 | 80000 | 26732 | 35 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80020 | 21 | 0 | 0 | 80056 | 1 | 0 | 1 | 62 | 80000 | 0 | 1 | 57 | 42 | 19 | 1 | 0 | 5110 | 2 | 16 | 2 | 2 | 26729 | 0 | 9 | 0 | 2 | 80000 | 80100 | 26733 | 26733 | 26733 | 26733 | 26733 |
| 160204 | 26732 | 200 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 65 | 0 | 1 | 0 | 3 | 26717 | 0 | 18 | 18 | 15 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1167530 | 1 | 49 | 23652 | 26771 | 26741 | 6657 | 0 | 3 | 6690 | 80100 | 200 | 160000 | 200 | 80000 | 26732 | 36 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80020 | 19 | 0 | 0 | 80019 | 1 | 0 | 1 | 21 | 80039 | 6 | 1 | 57 | 42 | 19 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26729 | 0 | 9 | 0 | 2 | 80000 | 80100 | 26733 | 26733 | 26733 | 26733 | 26715 |
| 160204 | 26714 | 200 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 92 | 0 | 1 | 0 | 3 | 26717 | 2 | 18 | 18 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1175054 | 0 | 49 | 23652 | 26820 | 26738 | 6661 | 0 | 3 | 6672 | 80100 | 200 | 160000 | 200 | 80000 | 26732 | 35 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80019 | 20 | 42 | 0 | 80057 | 1 | 0 | 0 | 59 | 80038 | 6 | 0 | 19 | 42 | 19 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 26711 | 0 | 9 | 9 | 2 | 80000 | 80100 | 26715 | 26733 | 26715 | 26733 | 26733 |
| 160204 | 26732 | 200 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 65 | 0 | 0 | 1 | 2 | 26717 | 2 | 18 | 18 | 17 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1171753 | 1 | 49 | 23652 | 26838 | 26719 | 6661 | 0 | 3 | 6690 | 80100 | 200 | 160000 | 200 | 80000 | 26732 | 35 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80020 | 19 | 42 | 0 | 80019 | 1 | 0 | 0 | 68 | 80038 | 6 | 1 | 57 | 0 | 19 | 1 | 0 | 5110 | 2 | 16 | 2 | 2 | 26729 | 0 | 9 | 9 | 2 | 80000 | 80100 | 26733 | 26733 | 26715 | 26733 | 26733 |
Result (median cycles for code divided by count): 0.3341
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 24 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cd | cf | d2 | d5 | map dispatch bubble (d6) | d9 | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 160025 | 26723 | 201 | 0 | 0 | 0 | 0 | 45 | 1 | 0 | 3 | 26701 | 2 | 18 | 18 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1170107 | 1 | 49 | 23652 | 26714 | 26714 | 6677 | 3 | 6712 | 80010 | 20 | 160000 | 20 | 80000 | 26732 | 35 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80039 | 0 | 0 | 0 | 0 | 80039 | 6 | 1 | 35 | 43 | 0 | 0 | 0 | 5020 | 0 | 1 | 16 | 0 | 1 | 1 | 26719 | 0 | 0 | 0 | 80000 | 80010 | 26708 | 26708 | 26728 | 26723 | 26728 |
| 160024 | 26727 | 200 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 26715 | 2 | 12 | 0 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1167530 | 1 | 49 | 23647 | 26707 | 26727 | 6677 | 3 | 6687 | 80010 | 20 | 160000 | 20 | 80000 | 26727 | 35 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80000 | 0 | 0 | 0 | 35 | 80000 | 0 | 1 | 0 | 43 | 0 | 0 | 0 | 5020 | 0 | 1 | 16 | 0 | 1 | 1 | 26719 | 10 | 0 | 4 | 80000 | 80010 | 26730 | 26740 | 26736 | 26708 | 26728 |
| 160024 | 26722 | 200 | 0 | 0 | 0 | 0 | 41 | 1 | 0 | 1 | 26725 | 2 | 0 | 18 | 16 | 25 | 80270 | 10 | 80000 | 10 | 80000 | 50 | 1170107 | 1 | 49 | 23627 | 26727 | 26722 | 6668 | 52 | 6828 | 80010 | 20 | 160000 | 20 | 80000 | 26727 | 35 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 0 | 80000 | 0 | 0 | 0 | 39 | 80000 | 6 | 1 | 35 | 39 | 0 | 0 | 0 | 5020 | 0 | 1 | 16 | 0 | 1 | 1 | 26719 | 9 | 0 | 0 | 80000 | 80010 | 26708 | 26728 | 26728 | 26708 | 26728 |
| 160024 | 26707 | 200 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 26717 | 2 | 0 | 12 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1174989 | 1 | 49 | 23652 | 26727 | 26727 | 6672 | 3 | 6687 | 80010 | 20 | 160000 | 20 | 80000 | 26727 | 35 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80039 | 0 | 0 | 0 | 39 | 80000 | 6 | 0 | 35 | 0 | 0 | 0 | 0 | 5020 | 0 | 1 | 16 | 0 | 1 | 1 | 26724 | 10 | 6 | 2 | 80000 | 80010 | 26728 | 26728 | 26728 | 26708 | 26708 |
| 160024 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 26712 | 2 | 12 | 18 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168754 | 1 | 49 | 23647 | 26707 | 26727 | 6672 | 3 | 6707 | 80010 | 20 | 160000 | 20 | 80000 | 26727 | 35 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80035 | 0 | 1 | 0 | 39 | 80035 | 0 | 0 | 0 | 39 | 0 | 0 | 0 | 5020 | 0 | 1 | 16 | 0 | 1 | 1 | 26724 | 10 | 6 | 0 | 80000 | 80010 | 26728 | 26728 | 26708 | 26728 | 26728 |
| 160024 | 26707 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 26707 | 2 | 0 | 12 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168754 | 0 | 49 | 23647 | 26732 | 26722 | 6653 | 3 | 6707 | 80010 | 20 | 160000 | 20 | 80000 | 26727 | 35 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80039 | 0 | 0 | 0 | 59 | 80038 | 6 | 0 | 19 | 42 | 19 | 1 | 0 | 5020 | 0 | 1 | 16 | 0 | 1 | 1 | 26724 | 9 | 9 | 2 | 80000 | 80010 | 26733 | 26733 | 26733 | 26723 | 26728 |
| 160024 | 26732 | 200 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 1 | 26712 | 2 | 0 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1173183 | 1 | 49 | 23647 | 26727 | 26707 | 6668 | 3 | 6707 | 80010 | 20 | 160000 | 20 | 80000 | 26707 | 35 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80019 | 20 | 0 | 80057 | 1 | 0 | 1 | 21 | 80039 | 6 | 0 | 35 | 43 | 0 | 0 | 0 | 5020 | 0 | 1 | 16 | 0 | 1 | 1 | 26719 | 10 | 6 | 2 | 80000 | 80010 | 26708 | 26708 | 26728 | 26723 | 26708 |
| 160024 | 26722 | 200 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 1 | 26841 | 2 | 12 | 18 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168754 | 1 | 49 | 23627 | 26727 | 26707 | 6668 | 3 | 6687 | 80010 | 20 | 160000 | 20 | 80000 | 26722 | 35 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 0 | 80000 | 0 | 0 | 0 | 39 | 80039 | 6 | 1 | 35 | 0 | 0 | 0 | 0 | 5020 | 0 | 1 | 16 | 0 | 1 | 1 | 26724 | 4 | 9 | 0 | 80000 | 80010 | 26728 | 26728 | 26728 | 26728 | 26733 |
| 160024 | 26727 | 200 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 2 | 26712 | 2 | 12 | 0 | 11 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1174628 | 1 | 49 | 23627 | 26727 | 26727 | 6678 | 3 | 6707 | 80010 | 20 | 160000 | 20 | 80000 | 26727 | 35 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80039 | 0 | 1 | 0 | 39 | 80039 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 1 | 16 | 0 | 1 | 1 | 26719 | 10 | 6 | 4 | 80000 | 80010 | 26728 | 26723 | 26723 | 26723 | 26728 |
| 160024 | 26727 | 200 | 0 | 0 | 1 | 0 | 45 | 1 | 0 | 2 | 26823 | 2 | 0 | 0 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168880 | 1 | 49 | 23647 | 26727 | 26722 | 6668 | 3 | 6854 | 80010 | 20 | 160000 | 20 | 80000 | 26727 | 35 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 1 | 10 | 80000 | 0 | 39 | 80039 | 0 | 0 | 0 | 0 | 80039 | 6 | 1 | 0 | 43 | 0 | 0 | 0 | 5020 | 0 | 1 | 16 | 0 | 1 | 1 | 26724 | 10 | 6 | 0 | 80000 | 80010 | 26708 | 26728 | 26708 | 26723 | 26728 |