Firestorm: LDR (unsigned offset, 64-bit) measurements

Code:

  ldr x0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	3	1	1	0	44	0	0	0	360	2	1	0	19	25	1000	1000	1000	15267	0	374	398	216	3	232	1000	1000	1000	394	56	1	1	1001	1000	1000	1	1000	0	43	1000	0	39	1000	6	0	39	43	0	0	73	2	16	1	1	395	14	0	7	1000	399	375	399	399	375
1004	374	3	0	0	0	45	0	0	1	383	2	1	0	19	25	1000	1000	1000	15267	0	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	0	0	1038	1	38	1038	6	1	39	44	0	0	73	1	16	1	1	371	14	14	7	1000	399	400	399	375	375
1004	398	2	0	1	0	0	0	0	0	383	2	0	0	0	25	1000	1000	1000	15508	0	398	374	197	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	0	0	1000	0	38	1038	0	1	0	44	0	0	73	1	16	1	1	395	14	0	4	1000	399	399	399	395	399
1004	394	3	0	0	0	44	0	0	1	383	2	12	12	16	25	1000	1000	1000	14060	1	398	398	217	3	256	1000	1000	1000	374	77	1	1	1001	1000	1000	0	1000	0	0	1038	0	39	1038	6	1	0	44	0	0	73	1	16	1	1	395	14	14	7	1000	395	399	375	399	399
1004	400	3	0	0	0	0	1	0	0	383	2	1	1	19	25	1000	1000	1000	15078	0	398	374	221	3	232	1000	1000	1000	398	56	1	1	1001	1000	1000	0	1000	0	0	1000	0	38	1038	6	1	38	44	0	0	73	1	16	1	1	391	14	14	0	1000	399	399	375	399	399
1004	374	3	0	0	0	0	1	0	1	379	2	0	1	19	25	1000	1000	1000	14060	1	374	374	221	3	256	1000	1000	1000	398	56	1	1	1001	1000	1000	0	1000	0	43	1040	0	39	1038	6	1	39	44	0	0	73	1	16	1	1	395	14	0	4	1000	395	399	395	375	375
1004	398	3	0	0	0	44	0	0	0	359	0	1	1	18	25	1000	1000	1000	14060	1	398	398	197	3	252	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	0	43	1038	0	0	1039	6	0	38	44	0	0	73	1	16	1	1	395	14	14	7	1000	375	399	399	375	399
1004	398	3	0	0	0	44	0	0	1	359	0	0	12	19	25	1000	1000	1000	15018	1	398	398	197	3	252	1000	1000	1000	398	56	1	1	1001	1000	1000	0	1000	0	43	1038	0	39	1000	0	0	0	44	0	0	73	1	16	2	2	391	0	0	7	1000	399	375	399	399	395
1004	398	3	0	0	0	44	0	0	1	383	2	1	0	16	25	1000	1000	1000	14989	1	374	394	221	3	232	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	0	43	1000	0	0	1039	0	0	40	0	0	0	73	1	16	2	2	371	14	14	0	1000	399	375	375	399	399
1004	374	2	0	0	0	53	1	0	1	359	2	1	0	16	25	1000	1000	1000	15274	1	374	398	229	3	232	1000	1000	1000	398	77	1	1	1001	1000	1000	1	1000	0	43	1038	0	0	1038	6	1	38	0	0	0	73	1	16	1	1	395	14	14	7	1000	375	399	375	375	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0055

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70061	525	0	0	1	0	2	0	0	0	70040	0	1	69786	59714	25	40108	30103	10002	30100	10000	616050	3342446	1	49	66963	70055	70055	64639	3	64946	40100	30200	10000	60200	10000	70055	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	2	10001	0	0	0	1	10001	1	1	1	0	0	2610	4	71	1	1	69806	30006	0	6	0	10000	30100	70044	70044	70056	70044	70044
40204	70055	525	0	0	0	0	1	0	0	0	70040	1	0	69786	59714	25	40108	30103	10001	30100	10000	615971	3342446	1	49	66975	70043	70055	64651	3	64958	40100	30200	10000	60200	10000	70055	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10001	0	1	0	1	10001	0	1	0	0	0	2610	1	71	1	1	69818	30003	6	6	6	10000	30100	70056	70056	70044	70044	70056
40204	70055	525	0	0	0	0	8	1	0	0	70044	0	1	69786	59714	25	40108	30106	10002	30100	10000	616050	3341867	1	49	66975	70043	70055	64651	28	65186	40100	30200	10000	60200	10000	70055	35	2	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10001	0	0	0	1	10001	0	1	0	0	0	2610	1	71	1	1	69818	30006	6	6	6	10000	30100	70056	70056	70056	70044	70056
40204	70055	524	0	0	0	0	2	0	0	0	70040	1	1	69786	59703	25	40108	30106	10002	30100	10000	616050	3341867	1	49	66975	70055	70043	64651	3	64946	40100	30200	10000	60200	10000	70044	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	2	10001	0	0	0	1	10001	1	1	1	0	0	2610	1	71	1	1	69818	30006	0	6	6	10000	30100	70066	70102	70059	70059	70044
40204	70043	525	0	0	0	0	2	0	0	0	70040	0	1	69786	59703	25	40108	30103	10001	30100	10000	615971	3342446	1	49	66963	70055	70055	64651	3	64946	40100	30200	10000	60200	10000	70055	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10001	0	0	0	1	10001	1	1	1	0	0	2610	1	71	1	1	69818	30006	0	0	6	10000	30100	70044	70056	70056	70044	70044
40204	70043	525	0	0	0	0	2	0	0	0	70040	1	1	69710	59703	25	40108	30106	10002	30100	10000	616050	3342446	1	49	66975	70055	70043	64639	3	64946	40100	30200	10000	60200	10000	70055	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10001	0	0	0	1	10001	1	1	1	0	0	2610	1	71	1	1	69818	30006	6	0	6	10000	30100	70044	70044	70056	70056	70044
40204	70055	525	0	0	0	0	28	1	0	0	70040	1	0	69786	59714	25	40108	30106	10001	30100	10000	616050	3342446	1	49	66975	70055	70055	64639	3	64958	40100	30200	10000	60200	10000	70055	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10001	0	0	0	1	10001	1	1	1	0	0	2610	1	71	1	1	69818	30003	6	6	6	10000	30100	70056	70056	70057	70056	70056
40204	70055	524	0	0	0	0	1	0	0	0	70028	1	1	69786	59703	25	40104	30103	10002	30100	10000	615971	3342446	1	49	66975	70055	70043	64651	3	64958	40100	30200	10000	60200	10000	70043	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10001	0	0	0	1	10001	1	1	0	0	0	2610	1	71	1	1	69806	30006	6	6	6	10000	30100	70056	70056	70056	70056	70056
40204	70055	524	0	0	0	0	2	0	0	0	70040	1	1	69786	59714	25	40108	30103	10002	30100	10000	616050	3342446	1	49	66963	70043	70043	64639	3	64958	40100	30200	10000	60200	10000	70055	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	2	10001	0	0	0	1	10001	1	1	1	0	0	2610	1	71	1	1	69806	30003	0	6	6	10000	30100	70056	70056	70056	70056	70056
40204	70055	525	0	0	0	1	1	1	0	0	70084	1	1	69786	59703	25	40108	30106	10002	30100	10000	616050	3342446	1	49	66963	70055	70055	64651	3	64958	40100	30200	10000	60200	10000	70055	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	2	10001	0	0	0	1	10001	1	1	1	0	0	2610	1	71	1	1	69818	30006	0	6	6	10000	30100	70056	70056	70056	70056	70064

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	524	0	0	0	0	0	1	0	0	0	0	70032	69728	59706	25	40014	30013	10001	30010	10000	617068	3342062	0	49	66970	70035	70035	64653	3	64972	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	2520	1	71	0	1	1	69810	30003	6	0	6	10000	30010	70036	70051	70051	70048	70048
40024	70047	524	0	0	0	0	0	1	0	0	0	0	70035	69760	59695	25	40014	30010	10001	30010	10000	616982	3342206	0	49	66970	70050	70035	64668	3	64975	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	0	1	2520	1	71	0	1	1	69810	30006	6	0	0	10000	30010	70036	70051	70051	70051	70051
40024	70050	524	0	0	0	0	0	1	0	0	0	0	70032	69746	59709	25	40010	30013	10001	30010	10000	617068	3341470	0	49	66970	70050	70050	64653	3	64960	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	1	0	10000	0	1	2520	1	71	0	1	1	69813	30003	9	6	9	10000	30010	70036	70051	70051	70051	70048
40024	70047	525	0	0	0	0	0	0	0	0	0	0	70032	69743	59706	25	40014	30010	10000	30010	10000	616982	3341470	0	49	66970	70050	70050	64668	3	64975	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	2520	1	71	0	1	1	69810	30003	6	0	6	10000	30010	70036	70036	70051	70048	70036
40024	70050	524	0	0	0	0	0	1	0	0	0	0	70032	69760	59706	25	40014	30010	10001	30010	10000	617068	3342206	0	49	66955	70050	70035	64668	3	64960	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	3	10000	1	1	2520	1	71	0	1	1	69798	30003	0	6	6	10000	30010	70051	70036	70036	70036	70048
40024	70035	525	0	0	0	0	0	0	0	0	0	0	70032	69743	59695	25	40014	30013	10000	30010	10000	616952	3341470	0	49	66970	70093	70119	64671	3	64972	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	1	2520	1	71	0	1	1	69813	30003	9	9	0	10000	30010	70048	70036	70051	70051	70036
40024	70035	524	0	0	0	0	0	1	0	0	0	0	70032	69760	59709	25	40014	30010	10000	30010	10000	617068	3342206	0	49	66955	70050	70050	64653	3	64975	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	2520	1	71	0	1	1	69810	30003	0	0	9	10000	30010	70051	70110	70057	70037	70051
40024	70050	525	0	0	1	0	0	6	0	1	0	0	70032	69760	59695	25	40010	30013	10001	30010	10000	617068	3341470	0	49	66955	70035	70035	64653	3	64975	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	2520	1	71	0	1	1	69822	30003	0	9	6	10000	30010	70048	70048	70036	70051	70051
40024	70047	525	0	0	0	0	0	1	0	0	0	0	70032	69760	59709	25	40014	30010	10001	30010	10000	617068	3342206	0	49	66970	70035	70035	64668	3	64960	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	2520	1	71	0	1	2	69813	30003	9	0	9	10000	30010	70036	70051	70051	70036	70051
40024	70050	525	0	0	0	0	0	1	0	0	0	0	70035	69728	59695	25	40010	30013	10000	30010	10000	617068	3341470	0	49	66955	70047	70047	64653	3	64972	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	2520	1	71	0	2	1	69813	30000	9	9	9	10000	30010	70051	70051	70051	70051	70051

Test 3: throughput

Count: 8

Code:

  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26732	200	1	0	1	1	0	0	0	21	1	0	3	26699	2	0	0	17	25	80100	100	80000	100	80000	500	1169486	49	23652	26714	26732	16655	3	16721	80100	200	80000	200	80000	26714	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	21	42	80019	1	60	0	62	80000	6	0	57	42	19	0	0	5110	1	16	1	1	26711	0	0	2	80000	100	26733	26733	26733	26715	26799
80204	26743	200	1	0	0	0	0	0	0	65	0	0	2	26717	2	18	18	125	25	80100	100	80000	100	80000	500	1169676	49	23652	26732	26732	16637	3	16672	80100	200	80000	200	80000	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	0	80058	0	0	0	27	80000	6	1	19	42	19	0	1	5110	1	16	1	1	26711	0	0	2	80000	100	26733	26733	26733	26715	26736
80204	26733	200	1	0	0	0	0	0	0	65	0	0	2	26717	0	18	0	16	25	80100	100	80000	100	80000	500	1169486	49	23653	26714	26732	16637	3	16691	80100	200	80000	200	80000	26732	63	1	1	80201	100	99	100	80000	100	80000	0	100	80021	20	42	80019	1	1	1	65	80038	0	0	57	0	19	2	0	5110	1	16	1	1	26729	9	0	0	80000	100	26733	26715	26733	26733	26735
80204	26745	200	1	1	1	1	0	0	0	65	1	0	3	26717	2	18	18	15	25	80100	100	80000	100	80000	500	1159120	49	23653	26714	26714	16655	3	16691	80100	200	80000	200	80000	26715	64	1	1	80201	100	99	100	80000	100	80000	0	100	80021	20	42	80057	1	1	1	30	80038	6	1	19	42	19	0	0	5110	1	16	1	1	26729	0	0	0	80000	100	26733	26734	26733	26733	26735
80204	26732	200	1	1	0	0	0	0	0	65	0	0	3	26718	2	18	0	62	25	80100	100	80000	100	80000	500	1166958	49	23634	26714	26733	16655	3	16690	80100	200	80000	200	80000	26714	64	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	0	80019	1	1	0	68	80000	6	1	57	42	19	0	0	5110	1	16	1	1	26729	9	9	2	80000	100	26733	26733	26715	26733	26739
80204	26718	200	1	1	0	0	0	0	0	21	0	0	1	26717	2	0	18	15	25	80100	100	80000	100	80000	500	1159459	49	23634	26732	26732	16644	3	16691	80100	200	80000	200	80000	26733	64	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	42	80019	1	1	0	24	80037	0	1	58	42	19	0	0	5110	1	16	1	1	26730	0	0	0	80000	100	26733	26734	26734	26734	26738
80204	26738	201	1	1	0	0	0	0	0	65	0	0	0	26717	2	18	18	16	25	80100	100	80000	100	80000	500	1167685	49	23653	26732	26714	16655	3	16690	80100	200	80000	200	80000	26732	64	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	0	80057	1	0	1	68	80000	0	1	19	42	19	2	0	5110	1	16	1	1	26733	0	9	0	80000	100	26715	26734	26734	26733	26717
80204	26737	200	1	0	0	0	0	0	0	21	0	0	1	26699	0	18	18	16	25	80100	100	80000	100	80000	500	1167685	49	23652	26714	26714	16637	3	16690	80100	200	80000	200	80000	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80020	21	42	80057	0	1	1	33	80000	0	0	57	0	19	0	0	5110	1	16	1	1	26730	9	9	0	80000	100	26715	26715	26715	26733	26741
80204	26738	200	1	0	0	1	0	0	0	65	0	0	2	26699	2	18	18	16	25	80100	100	80000	100	80000	500	1169486	49	23634	26714	26714	16655	3	16672	80100	200	80000	200	80000	26733	64	1	1	80201	100	99	100	80000	100	80000	0	100	80020	21	0	80019	0	1	1	62	80038	6	0	19	0	19	0	0	5110	1	16	1	1	26729	9	9	2	80000	100	26734	26734	26734	26734	26747
80204	26723	200	1	0	0	1	0	1	0	21	0	0	2	26699	2	0	0	15	25	80100	100	80000	100	80000	500	1166758	49	23653	26732	26714	16637	3	16672	80100	200	80000	200	80000	26715	81	1	1	80201	100	99	100	80000	100	80000	1	100	80020	19	42	80057	1	34	2	65	80000	6	1	57	0	19	0	0	5110	1	16	1	1	26730	0	9	0	80000	100	26734	26734	26715	26733	26738

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26733	200	1	0	0	0	0	0	0	65	1	0	2	26717	2	18	18	18	25	80010	10	80000	10	80000	50	1167599	0	49	23652	26732	26733	16677	3	16713	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	42	80057	1	0	1	59	80038	6	1	57	42	19	1	0	5020	4	16	6	8	26729	0	0	9	6	80000	10	26733	26733	26733	26715	26734
80024	26733	200	1	0	0	0	1	0	0	65	1	0	3	26718	2	18	18	16	25	80010	10	80000	10	80000	50	1165822	0	49	23634	26732	26733	16677	3	16712	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	42	80057	0	0	0	58	80038	6	1	57	42	19	1	0	5020	6	16	6	6	26729	0	9	9	2	80000	10	26734	26734	26733	26733	26733
80024	26732	200	1	1	0	0	1	0	0	65	1	0	3	26717	3	18	18	15	25	80010	10	80000	10	80000	50	1167599	0	49	23653	26732	26732	16677	3	16712	80010	20	80000	20	80000	26732	82	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	0	80058	1	0	0	59	80038	6	1	57	42	19	1	0	5020	8	16	6	7	26729	0	9	9	2	80000	10	26733	26733	26733	26733	26733
80024	26732	200	1	0	1	0	0	0	0	65	1	0	3	26717	2	18	18	16	25	80010	10	80000	10	80000	50	1172719	0	49	23652	26732	26715	16677	3	16712	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	1	10	80021	19	0	80057	0	0	1	59	80037	6	1	57	42	19	0	0	5020	8	16	8	8	26729	0	9	9	2	80000	10	26734	26953	26797	26736	26734
80024	26733	200	1	0	0	0	1	1	1	65	0	0	3	26717	2	18	18	16	25	80010	10	80000	10	80000	50	1166960	0	49	23652	26732	26733	16677	3	16712	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	0	10	80020	19	42	80057	1	0	1	21	80038	6	1	57	42	19	1	0	5020	9	16	5	6	26729	0	9	9	2	80000	10	26733	26733	26733	26733	26733
80024	26732	200	1	1	1	0	1	0	0	65	1	0	2	26717	2	0	0	16	25	80010	10	80000	10	80000	50	1166263	0	49	23652	26732	26733	16677	3	16712	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	0	10	80020	19	0	80057	1	0	0	59	80000	6	1	57	42	19	2	0	5020	5	16	8	8	26729	0	9	0	2	80000	10	26734	26733	26715	26733	26733
80024	26715	200	1	1	0	0	1	0	1	65	1	0	4	26718	2	18	18	16	25	80010	10	80000	10	80000	50	1170204	0	49	23652	26733	26732	16677	3	16712	80010	20	80000	20	80000	26733	64	1	1	80021	10	9	10	80000	10	80000	0	10	80019	20	42	80056	1	0	1	59	80038	6	1	57	42	19	0	0	5020	5	16	5	6	26729	0	0	9	2	80000	10	26733	26733	26733	26733	26733
80024	26739	200	1	1	0	0	1	0	0	65	1	0	3	26717	2	18	18	15	25	80010	10	80000	10	80000	50	1167599	0	49	23652	26714	26733	16677	3	16712	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	80058	0	0	0	59	80038	6	1	57	42	19	1	0	5020	7	16	8	6	26729	0	9	9	2	80000	10	26734	26734	26733	26733	26733
80024	26732	201	1	1	0	0	0	1	1	65	1	0	2	26718	2	18	18	16	25	80010	10	80000	10	80000	50	1165304	0	49	23652	26732	26732	16677	3	16712	80010	20	80000	20	80000	26732	81	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	80057	1	0	1	59	80038	6	1	57	42	19	1	0	5020	6	16	6	6	26729	0	9	9	2	80000	10	26733	26733	26733	26733	26734
80024	26733	200	1	0	1	0	1	0	0	65	1	0	3	26717	2	18	18	15	25	80010	10	80000	10	80000	50	1167599	0	49	23653	26732	26732	16677	3	16712	80010	20	80000	20	80000	26732	82	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	80057	0	0	1	59	80038	6	1	57	42	19	0	0	5020	6	16	6	6	26730	0	9	9	2	80000	10	26733	26733	26733	26716	26733

LDR (unsigned offset, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations