Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

EON (register, lsl, 32-bit)

Test 1: uops

Code:

  eon w0, w0, w1, lsl #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03091e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004203516006110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203515006110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035160010310001735252000200010003257020352035157531842100010002000203542111001100003731671117812000100020362036203620362036
1004203515006110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203516006110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203516006110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203516006110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035160216110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
1004203515006110001735252000200010003257020352035157531842100010002000203542111001100003731671117812000100020362036203620362036
1004203516006110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  eon w0, w0, w1, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515500000006110000198032520100201001010018534204916955200352003518429031870010100102002020020035421110201100991001010010000000000710259221979120000101002003620036200362003620036
1020420035155000000019810000198032520100201001010018534204916955200352003518429031870010100102002020020035421110201100991001010010000000000710259221979120000101002003620036200362003620036
102042003515600000006110000198032520100201001010018534204916955200352003518429031870010100102002020020035421110201100991001010010000000000710259221979120000101002003620130200362003620036
102042003515500000006110000198032520100201001010018534204916955200352003518429031870010100102002020020035421110201100991001010010020010000710259221979120000101002003620036200362003620036
102042003515500000006110000198032520100201001010018534204916955200352003518429031870010100102002020020035421110201100991001010010000000300710259221979120000101002003620036200362003620036
102042003515500000006110000198032520100201001010018534214916955200352003518429031870010100102002020020035421110201100991001010010000000000710259221979120000101002003620036200362003620036
102042003515500000006110000198032520100201001010018534204916955200352003518429031870010100102002020020035421110201100991001010010000000000710259221979120000101002003620036200362003620036
102042003515600000006110000198032520100201001010018534204916955200352003518429031870010100102002020020035421110201100991001010010000000000710259221979120000101002003620036200362017020036
1020420035155000000063110000198032520100201001010018534214916955200352003518429031870010100102002020020035422110201100991001010010000000000710259221979120000101002003620036200362003620036
102042003515500000006110000198032520100201001010018534204916955200352003518429031870010100102002020020035421110201100991001010010000000000710259221979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002420035155000252100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101013640263221979220000100102003620036200362003620036
1002420035155000105100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101013640263221979220000100102003620036200362003620036
1002420035155120061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101013640263221979220000100102003620036200362003620036
10024200351551500388100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101013640263221979220000100102003620036200362003620036
10024200351551200103100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101013640263221979220000100102003620036200362003620036
100242003515500061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101013640263221979220000100102003620036200362003620036
1002420035155120061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
10024200351551200124100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101003640263221979220000100102003620036200362003620036
1002420035155120061100001974325200102001010010185310049170002003520035184513187181001010020200202003542111002110910100101010640263221979220000100102003620036200362003620036
100242003515500061100001974325200102001010010185310049170022003520035184513187181001010189200202003542111002110910100101010640263221979220000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  eon w0, w1, w0, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)0318191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515500240117100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111983420000101002003620036200362003620036
1020420035156000061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
10204200351610012061100001980325201002010010100185342149169552003520035184293187001010010200205402003542111020110099100101001000030710190111979120000101002003620036200362003620036
1020420035156000061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
10204200351550000145100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
10204200351560090061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
1020420035155000061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000100710059111979120000101002003620036200362003620036
10204200351550018061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
1020420035155000061100001980325201002010010100185342049169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
10204200351560024061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515500611000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100100640463551979220000100102003620036200362003620036
100242003515500611000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640663561979220000100102003620036200362003620036
100242003515500611000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100010640663651979220000100102003620036200362003620036
100242003515500611000019741252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100010640563771979220000100102003620036200362003620036
100242003515500891000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100010640663661979220000100102003620036200362003620036
100242003515600611000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100003640563551979220000100102003620036200362003620036
100242003515500611000019743252001020010100101853104917092200352003518451318718100101002020020200354211100211091010010100000640663651979220000100102003620036200362003620036
1002420035155121611000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100000640563561979220000100102003620036200362003620036
1002420035155001031000019743252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100003640563651979220000100102003620036200362003620036
100242003515500611000019741252001020010100101853104916955200352003518451318718100101002020020200354211100211091010010100010640563441979220000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  eon w0, w8, w9, lsl #17
  eon w1, w8, w9, lsl #17
  eon w2, w8, w9, lsl #17
  eon w3, w8, w9, lsl #17
  eon w4, w8, w9, lsl #17
  eon w5, w8, w9, lsl #17
  eon w6, w8, w9, lsl #17
  eon w7, w8, w9, lsl #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802042673220710100002828003126146281601821601828026216190649236520267322673216651816661802628037616055226732391180201100991008010010000000011151359168326729160082801002673326733267332673326733
8020426732207101000031258003126146281601821601828026216190649236520267322673216651816661802628037616055226732391180201100991008010010000000011151359166626729160082801002673326733267332673326733
80204267322071010000314780031261462816018216018280262161906492365202673226732166518166618026281022160552267323921802011009910080100100000000111513510168826729160082801002673326733267332673326733
802042673220710100003828003126146281601821601828026216190649236520267322673216651816661802628037616055226732391180201100991008010010000000011151358168826729160082801002673326733267332673326733
802042673220710100003117800312614628160182160182802621619064923645026725267251661531667780100802001602002672539118020110099100801001000000000005116922111126717160000801002672626726267262672626726
80204267252071010000311580000260942516010016010080100164318492364502672526725166153166778010080200160200267253911802011009910080100100000000000511642210426717160000801002672626726267262672626726
8020426725207101000031158000026094251601001601008010016431849236450267252672516615316677801008020016020026725391180201100991008010010000000000051169229926717160000801002672626726267262672626726
8020426725207101000031558000026094251601001601008010016431849236450267252672516615316677801008020016020026725391180201100991008010010000000000051169229926717160000801002672626726267262672626726
802042672520710100003718000026094251601001601008010016431849236450267252672516615316677801008020016020026725391180201100991008010010000000000051169227726717160000801002672626726267262672626726
802042672520710100003718000026094251601001601008010016431849236450267252672516615316677801008041816020026725391180201100991008010010000000000051167227726717160000801002672626726267262672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024267352141201698000021280251600101600108001016314214923631267112671116623316685800108002016002026711391180021109108001010010050204224426704160000800102671226712267122671226712
8002426711214303618000021280251600101600108001016314214923631267112671116623316685800108002016002026711391180021109108001010000050202224226704160000800102671226712267122671226712
8002426711214186180000212802516001016001080010163142149236312671126711166233166858001080020160020267113911800211091080010100221050202224426704160000800102671226712267122671226712
800242671121401148000021280251600101600108001016314214923631267112671116623316685800108002016002026711391180021109108001010000050204223426704160000800102671226712267122671226712
80024267112154958018000021280251600101600108001016314214923631267112671116623316685800108002016002026711391180021109108001010020150204222426704160000800102671226712267122671226712
80024267112140618000021280251600101600108001016314214923631267112671116623316685800108002016002026711391180021109108001010000050204224226704160000800102671226712267122671226712
80024267112140618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010003050204224226704160000800102671226712267122671226712
800242671121408188000021280251600101600108001016314204923631267112671116623316753800108002016002026711391180021109108001010000050205224426704160000800102671226712267122671226712
800242671121415618000021280251600101600108001016314214923631267112671116623316685800108002016002026711391180021109108001010000050204222426704160000800102671226712267122671226712
800242671121406438000021280251600101600108001016314214923631267112671116623316685800108002016002026711391180021109108001010003050202224226704160000800102671226712267122671226712