Firestorm: LDRSH (register, uxtw, 32-bit) measurements

Code:

  ldrsh w0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	3	1	1	1	0	0	66	1	0	1	388	3	7	7	20	25	1000	1000	1000	15526	1	403	403	226	3	261	1000	1000	2000	402	85	1	1	1001	0	1000	1000	0	1019	21	43	1058	0	0	1	60	1039	6	1	59	43	19	2	73	1	16	1	1	400	13	13	5	1000	403	404	404	404	404
1004	408	3	1	1	1	0	0	67	1	0	2	388	3	7	7	21	25	1000	1000	1000	15526	1	402	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1020	21	43	1058	0	0	0	61	1040	6	1	58	43	19	0	73	1	16	1	1	400	13	13	5	1000	404	404	404	403	405
1004	403	3	1	1	0	0	0	67	0	0	2	387	3	7	7	20	25	1000	1000	1000	15480	1	403	402	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	1	1019	19	43	1061	1	0	2	61	1040	6	1	59	43	19	0	73	1	16	1	1	400	13	13	5	1000	408	404	414	403	404
1004	403	3	1	1	0	1	0	67	1	0	3	366	2	7	7	19	25	1000	1000	1000	15526	1	403	402	225	3	261	1000	1000	2000	402	85	1	1	1001	0	1000	1000	0	1020	20	44	1058	1	0	0	61	1040	6	1	60	43	19	0	73	1	16	1	1	400	13	13	5	1000	405	405	404	403	404
1004	403	2	1	1	0	0	0	66	1	0	3	388	3	7	7	20	25	1000	1000	1000	15555	1	402	403	225	3	261	1000	1000	2000	405	85	1	1	1001	0	1000	1000	0	1020	20	45	1061	0	0	0	60	1039	6	1	59	43	19	0	73	1	16	1	1	400	13	13	5	1000	404	404	403	403	404
1004	403	3	1	1	1	0	0	67	0	0	3	388	2	7	7	20	25	1000	1000	1000	15480	1	403	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1020	20	43	1059	1	0	1	60	1039	6	1	58	43	19	0	73	1	16	1	1	400	13	13	5	1000	404	404	403	404	404
1004	403	3	1	0	1	0	0	66	0	0	2	388	2	7	7	18	25	1000	1000	1000	15523	1	402	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1020	19	43	1058	1	0	0	61	1040	6	1	59	43	19	1	73	1	16	1	1	400	13	13	5	1000	404	404	404	404	403
1004	405	3	1	1	1	0	0	67	0	0	3	388	2	7	7	18	25	1000	1000	1000	15525	1	403	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1019	19	43	1060	1	0	1	60	1040	6	1	58	43	19	2	73	1	16	1	1	400	13	13	5	1000	403	404	404	404	404
1004	403	3	1	0	1	0	0	67	1	0	2	387	3	7	7	20	25	1000	1000	1000	15480	1	403	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1019	21	43	1058	0	0	0	63	1040	6	1	58	43	19	0	73	1	16	1	1	400	13	13	5	1000	404	404	404	404	403
1004	403	3	1	1	1	0	0	66	1	0	2	367	2	7	7	20	25	1000	1000	1000	15480	1	403	403	225	3	260	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1021	20	43	1059	1	0	1	61	1040	6	1	59	43	19	0	73	1	16	1	1	400	13	13	5	1000	403	403	404	404	404

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70054	525	1	0	1	0	1	0	0	70036	69764	59752	25	40100	30103	10001	30111	10007	615576	3341639	0	49	66971	70051	70051	64703	6	64984	40118	30230	10010	60260	20020	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	1	0	10000	1	0	1	0	1	1	1	2620	2	16	1	2	69860	30003	13	10	13	10000	30100	70052	70036	70058	70052	70055
40204	70054	524	1	0	1	0	0	0	0	70020	69764	59752	25	40104	30103	10001	30111	10007	615576	3342567	0	49	67022	70054	70054	64703	6	65003	40118	30230	10010	60260	20020	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	9	10000	0	0	1	0	1	1	1	2620	2	16	2	1	69862	30003	0	10	13	10000	30100	70052	70055	70055	70055	70055
40204	70054	524	0	0	1	0	0	0	0	70039	69785	59752	25	40100	30103	10001	30111	10007	615710	3341639	0	49	66955	70035	70054	64700	6	65003	40118	30230	10010	60260	20020	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	0	1	0	1	1	1	2620	1	16	2	1	69862	30003	13	13	13	10000	30100	70055	70055	70055	70055	70036
40204	70054	525	0	1	1	0	0	0	0	70039	69785	59734	25	40104	30100	10000	30111	10007	615576	3341639	0	49	66972	70051	70051	64703	6	65003	40118	30230	10010	60260	20020	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	0	1	0	1	1	1	2620	2	16	2	2	69862	30013	0	13	10	10000	30100	70055	70055	70036	70055	70036
40204	70035	525	0	0	1	0	0	0	0	70020	69785	59734	25	40104	30103	10001	30111	10007	615576	3342567	0	49	66981	70054	70051	64703	6	64984	40118	30230	10010	60260	20020	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	0	1	0	1	1	1	2620	2	16	1	2	69862	30003	13	10	0	10000	30100	70036	70055	70055	70052	70036
40204	70051	525	0	0	0	0	0	0	0	70040	69764	59752	25	40104	30100	10000	30111	10007	615576	3341639	0	49	66972	70054	70054	64703	6	65003	40118	30230	10010	60260	20020	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	10000	1	0	1	0	1	1	1	2620	2	16	1	2	69862	30003	13	10	0	10000	30100	70036	70055	70036	70055	70055
40204	70051	525	0	0	1	0	0	0	0	70039	69785	59752	25	40104	30103	10001	30111	10007	615576	3342567	0	49	66974	70054	70054	64703	6	65000	40118	30230	10010	60260	20020	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	0	10000	1	0	0	0	1	1	1	2620	2	16	2	1	69900	30003	13	13	13	10000	30100	70055	70055	70036	70055	70036
40204	70035	524	0	0	1	0	0	0	0	70039	69785	59752	25	40104	30103	10001	30111	10007	615576	3341639	0	49	66974	70054	70035	64703	6	65003	40118	30230	10010	60260	20020	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	0	0	1	0	1	1	1	2620	2	16	2	2	69867	30003	13	13	13	10000	30100	70055	70036	70055	70055	70055
40204	70054	524	0	0	0	0	1	0	0	70039	69764	59752	25	40104	30103	10001	30111	10007	615710	3342423	0	49	66975	70054	70054	64700	6	65003	40118	30230	10010	60260	20020	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	0	1	0	1	1	1	2620	2	16	2	1	69859	30000	13	13	13	10000	30100	70055	70055	70055	70055	70055
40204	70035	525	0	0	0	0	0	0	0	70039	69822	59758	25	40104	30100	10001	30111	10007	615576	3341639	0	49	66971	70054	70054	64684	6	64984	40118	30230	10010	60260	20020	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	10000	1	0	1	0	1	1	1	2620	1	16	2	2	69859	30003	13	13	13	10000	30100	70036	70036	70055	70036	70055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	524	0	0	0	0	1	0	0	0	1	0	1	0	1	70071	69729	59706	25	40014	30013	10001	30010	10000	617036	3342489	0	0	49	66976	0	70166	70056	64659	21	64978	40399	30020	10110	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10007	7	0	10001	0	0	1	10000	1	1	0	1	1	0	0	2520	0	0	4	71	4	4	69816	30044	9	0	9	10000	30010	70054	70042	70057	70057	70057
40024	70058	525	1	0	1	1	0	0	0	0	2	0	0	0	1	70038	69777	59715	25	40018	30023	10002	30010	10000	617594	3343262	0	0	49	66961	0	70056	70056	64674	3	64981	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10001	0	0	7	10000	1	1	1	1	1	0	0	2520	0	0	3	102	2	4	69804	30006	0	0	6	10000	30010	70056	70057	70048	70054	70042
40024	70056	524	1	1	0	0	0	0	0	0	2	0	1	0	1	70041	69702	59715	25	40014	30010	10001	30010	10000	616982	3342062	0	0	49	66967	0	70035	70035	64653	3	64975	40010	30020	10000	60020	20000	70050	35	2	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	2	13	10000	1	0	1	0	0	0	0	2520	0	0	2	71	3	4	69810	30003	0	6	9	10000	30010	70051	70036	70048	70051	70051
40024	70047	524	0	0	0	0	0	0	0	0	1	0	1	0	0	70020	69743	59695	25	40014	30013	10001	30010	10000	616982	3342206	0	0	49	66970	0	70047	70035	64668	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10003	0	2	1	10000	1	1	0	1	0	0	0	2520	0	0	4	71	4	2	69819	30006	9	0	9	10000	30010	70054	70054	70054	70054	70057
40024	70041	525	1	1	1	0	0	0	0	0	1	0	0	0	1	70041	69780	59701	25	40018	30013	10002	30010	10000	617009	3342350	0	0	49	66976	0	70056	70041	64674	3	64981	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10003	3	0	10002	1	1	1	10000	0	1	1	1	0	0	0	2520	0	0	2	71	4	2	69813	30003	9	6	9	10000	30010	70039	70051	70036	70056	70051
40024	70050	525	0	0	0	0	0	0	0	0	1	0	1	0	0	70038	69760	59709	25	40010	30013	10001	30010	10000	616982	3341967	0	0	49	66970	0	70050	70050	64653	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10001	0	1	1	10000	1	0	1	0	0	0	0	2520	0	0	4	71	5	2	69813	30003	9	6	9	10000	30010	70051	70051	70051	70051	70036
40024	70050	524	0	0	0	0	0	0	0	1	0	0	0	0	0	70034	69743	59709	25	40014	30013	10000	30010	10000	616952	3342062	0	0	49	66970	0	70047	70035	64668	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10002	0	0	1	10000	1	1	1	1	0	0	0	2520	0	0	4	71	2	4	69804	30006	9	6	9	10000	30010	70057	70042	70054	70054	70057
40024	70056	524	1	1	1	1	0	0	0	0	2	0	1	0	0	70041	69702	59701	25	40018	30016	10002	30010	10000	617009	3342494	1	0	49	66973	0	70056	70041	64674	3	64981	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	0	10002	0	1	1	10000	1	1	1	1	1	0	0	2520	0	0	4	71	4	4	69816	30003	6	0	9	10000	30010	70051	70051	70051	70036	70048
40024	70050	524	0	0	0	0	0	0	0	0	0	0	0	0	0	70022	69760	59695	25	40014	30013	10000	30010	10000	616973	3342062	0	0	49	66970	0	70160	70035	64653	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	1	10002	0	0	1	10000	1	0	1	0	0	0	0	2520	0	0	4	71	4	2	69813	30000	9	0	9	10000	30010	70051	70048	70048	70036	70086
40024	70047	525	0	0	0	0	0	1	0	0	1	0	1	0	0	70035	69732	59695	25	40014	30013	10000	30010	10000	616952	3342062	0	0	49	66967	0	70050	70047	64674	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	0	10002	0	1	1	10000	1	0	1	0	0	0	0	2520	0	0	4	71	4	2	69813	30003	9	6	0	10000	30010	70036	70051	70051	70036	70036

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	1	1	1	1	1	0	2	1	1	70042	69788	59716	25	40108	30103	10002	30100	10000	616077	3341769	1	49	66977	0	70041	70057	64637	3	64963	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10001	0	0	1	1	10000	1	1	0	1	0	2620	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70058	70058	70058	70058
40204	70057	524	1	1	1	1	1	0	0	0	0	70036	69764	59695	25	40104	30103	10000	30100	10000	616014	3342254	1	49	66977	0	70057	70057	64653	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69814	30003	10	0	10	10000	30100	70052	70036	70052	70052	70036
40204	70051	525	0	0	0	0	1	0	1	1	0	70036	69764	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66971	3	70051	70051	64631	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	0	0	1	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70036	70052	70052
40204	70051	525	0	0	0	0	0	0	2	1	1	70042	69788	59716	25	40108	30106	10002	30100	10000	616104	3342542	1	49	66977	0	70057	70041	64653	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10001	0	1	0	4	10000	1	0	1	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70036	70052	70052	70052	70052
40204	70035	525	0	0	0	0	0	0	1	0	0	70036	69782	59710	25	40104	30100	10001	30100	10000	616175	3342254	1	49	66977	0	70057	70057	64653	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70036	70052
40204	70051	524	0	0	0	0	0	0	0	1	0	70020	69782	59710	25	40104	30100	10001	30100	10000	616014	3342254	1	49	66977	0	70057	70057	64653	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	0	10003	0	0	1	1	10000	1	1	1	1	2	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70058	70062	70058	70042	70042
40204	70057	524	1	1	1	1	1	0	1	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66971	0	70035	70051	64631	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	12	10000	1	1	1	1	2	2610	1	71	1	1	69822	30006	10	10	10	10000	30100	70058	70058	70058	70042	70058
40204	70057	525	1	1	1	1	0	0	2	1	1	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3341769	1	49	66971	0	70035	70051	64631	3	64938	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	0	10000	1	1	1	1	1	2610	1	71	1	1	69804	30006	10	10	10	10000	30100	70042	70042	70058	70042	70058
40204	70057	525	1	1	0	1	0	0	1	1	0	70036	69764	59695	25	40104	30100	10001	30100	10000	616175	3341470	1	49	66961	0	70057	70041	64653	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	3	1	10002	0	0	0	1	10000	1	1	1	1	1	2610	1	71	1	0	69804	30006	10	0	10	10000	30100	70058	70058	70042	70058	70058
40204	70057	524	1	0	0	0	0	0	1	0	0	70020	69764	59710	25	40104	30112	10001	30100	10000	616086	3342254	1	49	66971	0	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	0	10000	1	1	1	1	0	2610	1	71	1	1	69798	30003	10	10	10	10000	30100	70052	70052	70036	70036	70037

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	19	1e	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	524	1	0	1	1	0	1	0	0	0	1	0	1	70038	69780	59712	25	40018	30016	10002	30010	10000	617036	3342350	49	66976	0	70056	70056	64674	7	3	64978	40010	30020	10000	60020	20000	70146	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	1	1	10001	0	0	1	10000	1	1	0	1	1	0	2520	0	6	71	5	7	69816	30003	9	0	0	10000	30010	70057	70057	70042	70057	70057
40024	70053	525	1	0	0	0	0	1	1	0	0	2	0	0	70038	69702	59701	25	40018	30016	10002	30010	10000	616995	3342494	49	66976	0	70053	70056	64674	0	3	64981	40010	30020	10000	60020	20000	70116	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10002	0	1	1	10000	1	1	1	1	2	0	2520	0	6	71	5	6	69816	30006	6	6	0	10000	30010	70042	70042	70059	70054	70042
40024	70056	525	1	0	0	2	0	1	0	0	0	2	1	0	70041	69702	59715	25	40014	30016	10001	30010	10000	617036	3341769	49	66976	0	70053	70056	64659	0	3	64981	40010	30020	10000	60020	20000	70115	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	1	0	10002	1	1	1	10000	0	1	1	1	1	0	2520	0	5	71	7	7	69804	30006	9	6	9	10000	30010	70054	70057	70057	70054	70057
40024	70041	525	1	0	0	1	0	1	0	0	0	2	0	0	70026	69702	59715	25	40014	30016	10002	30010	10000	617117	3343502	49	66973	0	70041	70056	64674	0	3	64966	40010	30020	10000	60020	20000	70158	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	3	1	10002	0	0	1	10000	1	1	0	1	1	0	2520	0	6	71	5	5	69804	30003	9	0	9	10000	30010	70057	70042	70042	70054	70042
40024	70053	525	1	0	0	1	0	0	0	0	0	2	0	1	70041	69780	59715	25	40014	30016	10002	30010	10000	617009	3342494	49	66973	0	70056	70041	64659	0	3	64978	40010	30020	10000	60020	20000	70138	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	3	1	10002	0	2	1	10000	0	1	1	1	0	0	2520	0	3	71	5	5	69816	30006	9	0	9	10000	30010	70057	70094	70043	70060	70054
40024	70041	526	1	0	1	1	0	0	0	0	0	2	0	0	70041	69702	59715	25	40018	30016	10001	30010	10000	616995	3342494	49	66976	0	70056	70056	64674	0	3	64981	40010	30020	10000	60020	20000	70134	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10002	0	0	1	10000	0	1	1	1	1	0	2520	0	5	71	6	4	69819	30006	9	9	6	10000	30010	70057	70057	70057	70057	70057
40024	70056	525	1	0	0	1	0	1	0	0	0	2	0	0	70026	69702	59715	25	40018	30016	10001	30010	10000	617036	3342494	49	66973	0	70056	70056	64674	0	3	64966	40010	30020	10000	60020	20000	70120	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	0	10001	0	1	25	10000	1	1	0	1	0	0	2520	0	4	71	6	6	69804	30003	9	6	6	10000	30010	70057	70042	70042	70054	70060
40024	70056	524	1	0	0	0	0	0	0	0	0	1	0	0	70041	69702	59715	25	40018	30016	10002	30010	10000	617036	3341769	49	66976	0	70057	70053	64674	0	3	64981	40010	30020	10000	60020	20000	70133	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	0	1	10000	1	1	0	1	0	0	2520	0	8	71	7	5	69819	30006	9	6	9	10000	30010	70042	70054	70042	70054	70057
40024	70053	525	1	0	1	0	0	1	0	0	0	1	0	0	70041	69702	59715	25	40014	30013	10002	30010	10000	617009	3341769	49	66961	0	70056	70056	64674	0	3	64981	40010	30020	10000	60020	20000	70107	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	0	1	10000	0	1	0	1	0	0	2520	0	5	71	5	5	69804	30006	9	9	9	10000	30010	70054	70042	70042	70042	70057
40024	70053	525	1	0	1	1	0	1	0	0	0	1	0	0	70041	69780	59712	25	40018	30016	10001	30010	10000	617036	3342350	49	66976	0	70041	70056	64671	0	3	64966	40010	30020	10000	60020	20000	70112	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	2	0	10002	0	0	1	10000	1	1	1	1	0	0	2520	0	5	71	6	6	69819	30006	9	0	9	10000	30010	70057	70057	70057	70057	70042

Test 4: throughput

Count: 8

Code:

  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26732	200	1	1	1	1	1	21	0	0	3	26703	2	18	0	16	25	80100	100	80000	100	80015	500	1167009	0	49	23653	26732	26736	16642	6	16685	80115	200	80024	200	160048	26714	82	1	1	80201	100	99	100	80000	100	80000	1	100	80020	20	0	0	80019	2	40	1	71	80000	6	1	57	42	19	1	1	1	1	5118	1	16	2	1	26729	9	9	0	80000	100	26736	26733	26734	26734	26734
80204	26739	200	1	1	1	0	0	65	0	0	2	26718	2	18	18	15	25	80100	100	80000	100	80015	500	1166836	0	49	23634	26714	26734	16662	6	16688	80116	200	80224	200	160048	26732	63	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	0	80058	1	8	1	71	80038	6	1	57	42	19	0	1	1	1	5118	2	16	2	1	26729	9	9	2	80000	100	26733	26733	26715	26734	26827
80204	26714	200	1	0	0	0	0	65	0	0	2	26717	3	0	0	16	25	80100	100	80000	100	80016	500	1169563	1	49	23652	26733	26714	16660	6	16666	80115	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	42	0	80019	1	41	1	59	80038	6	1	57	42	19	1	1	1	1	5118	0	16	2	1	26730	4	0	2	80000	100	26733	26733	26733	26715	26819
80204	26732	200	1	0	0	0	0	65	0	1	2	26717	0	18	18	15	25	80100	100	80000	100	80015	500	1168023	0	49	23634	26732	26733	16642	6	16684	80116	200	80024	200	160048	26714	64	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	0	0	80058	1	0	1	68	80038	0	1	57	42	19	1	1	1	1	5118	2	16	2	2	26730	9	9	2	80000	100	26733	26717	26733	26733	26733
80204	26732	200	1	1	0	1	1	21	0	0	1	26699	2	0	18	21	25	80100	100	80000	100	80015	500	1169757	0	49	23652	26732	26732	16660	6	16685	80115	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	0	0	80057	1	1	2	59	80000	6	0	57	41	19	0	1	1	1	5118	2	16	2	1	26729	9	0	2	80000	100	26715	26715	26733	26733	26743
80204	26734	201	1	0	1	0	0	65	0	1	2	26717	2	18	0	15	25	80100	100	80000	100	80015	500	1167763	0	49	23653	26732	26732	16660	6	16684	80115	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	42	0	80057	0	2	0	59	80038	6	1	57	42	19	1	1	1	1	5118	2	16	2	1	26729	0	9	2	80000	100	26715	26733	26733	26715	26738
80204	26736	200	1	1	1	0	0	21	0	0	2	26717	2	18	18	15	25	80100	100	80000	100	80015	500	1167763	1	49	23634	26732	26733	16659	6	16684	80116	200	80024	200	160048	26715	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	0	80019	1	54	2	71	80000	6	1	19	42	19	1	1	1	1	5118	3	16	2	1	26729	9	9	2	80000	100	26733	26733	26733	26735	26769
80204	26745	201	1	1	1	1	0	83	0	1	3	26718	2	0	18	16	25	80100	100	80000	100	80015	500	1159695	0	49	23653	26726	26733	16659	6	16685	80116	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	40	0	80019	1	33	2	59	80000	6	1	57	42	19	0	1	1	1	5118	1	16	1	2	26729	0	9	0	80000	100	26715	26733	26733	26734	26738
80204	26734	200	1	1	1	0	0	65	0	1	3	26699	2	18	0	0	25	80100	100	80000	100	80015	500	1169563	1	49	23652	26715	26732	16660	6	16684	80115	200	80024	200	160048	26714	64	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	0	0	80058	1	2	1	59	80038	6	0	57	0	19	1	1	1	1	5118	0	16	1	2	26745	9	9	2	80000	100	26733	26715	26733	26715	26738
80204	26736	200	1	1	0	0	0	65	0	0	3	26699	2	18	18	15	25	80100	100	80000	100	80012	500	1167078	0	49	23652	26714	26733	16660	6	16684	80116	200	80024	200	160048	26732	64	1	1	80201	100	99	100	80000	100	80000	1	100	80020	19	41	0	80058	1	2	1	59	80038	6	1	57	41	19	2	1	1	1	5118	2	16	1	2	26711	9	9	2	80000	100	26733	26733	26733	26733	26735

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	19	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26728	200	1	0	0	207	1	0	0	1	26713	2	0	1	16	25	80010	10	80000	10	80000	50	1168843	1	49	23648	0	26736	26851	16683	3	16707	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	43	80039	0	39	80039	6	1	39	44	0	0	5020	0	0	6	16	2	4	26705	10	10	4	80000	10	26729	26709	26729	26729	26728
80024	26727	200	0	0	0	60	1	0	0	1	26713	2	1	12	16	25	80010	10	80000	10	80000	50	1166750	1	49	23647	0	26737	26869	16683	3	16707	80010	20	80000	20	160000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80040	0	38	80039	6	0	39	43	0	0	5020	0	0	4	16	4	2	26705	10	10	4	80000	10	26728	26729	26709	26709	26728
80024	26731	200	0	0	0	69	0	0	0	1	26712	2	1	1	19	25	80010	10	80000	10	80000	50	1166750	1	49	23647	0	26737	26816	16677	3	16711	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	39	80000	6	1	39	43	0	0	5020	0	0	4	16	4	2	26728	0	10	4	80000	10	26729	26728	26728	26729	26728
80024	26708	200	0	0	0	558	1	0	0	0	26713	0	1	12	19	25	80010	10	80000	10	80000	55	1174647	1	49	23647	0	26736	26839	16680	3	16717	80010	20	80000	20	160000	26731	80	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80000	0	38	80039	6	1	39	43	0	0	5020	0	0	4	16	2	4	26705	14	10	4	80000	10	26732	26732	26732	26709	26732
80024	26731	200	0	0	0	516	1	0	0	1	26712	2	1	12	19	25	80010	10	80000	10	80000	50	1167124	1	49	23651	0	26736	26708	16672	3	16807	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	38	80000	6	1	39	43	0	0	5020	0	0	2	16	2	4	26724	10	10	4	80000	10	26728	26709	26728	26732	26732
80024	26728	200	0	0	0	171	0	0	0	1	26716	2	0	0	19	25	80010	10	80000	10	80000	50	1167501	1	49	23628	0	26736	26826	16680	3	16707	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80000	0	38	80039	6	1	38	44	0	0	5020	0	0	4	16	4	2	26705	10	10	4	80000	10	26732	26732	26732	26728	26729
80024	26728	201	0	0	0	15	0	0	0	1	26693	2	12	12	19	25	80010	10	80000	10	80000	50	1167124	1	49	23651	0	26739	26897	16781	3	16708	80010	20	80000	20	160000	26728	81	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	39	80038	6	1	39	44	0	0	5020	0	0	2	16	4	2	26724	0	10	0	80000	10	26728	26728	26709	26732	26732
80024	26731	200	0	0	0	60	1	0	0	1	26713	2	1	1	19	25	80010	10	80000	10	80000	50	1166886	1	49	23628	0	26737	26855	16682	3	16688	80010	20	80000	20	160000	26731	81	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80038	0	38	80038	6	1	39	44	0	0	5020	0	0	2	16	2	4	26728	10	10	4	80000	10	26728	26709	26732	26732	26732
80024	26731	200	0	0	0	60	1	0	0	1	26712	2	12	0	19	25	80010	10	80000	10	80000	50	1167201	1	49	23647	0	26737	26868	16677	3	16711	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	39	80038	6	1	0	43	0	0	5020	0	0	2	16	6	2	26725	10	10	4	80000	10	26728	26709	26728	26732	26728
80024	26727	200	0	0	0	69	1	0	0	1	26713	2	12	12	0	25	80010	10	80000	10	80000	50	1167501	1	49	23647	3	26818	26842	16681	3	16696	80010	20	80000	20	160000	26727	80	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80054	0	0	80000	6	1	0	43	0	0	5020	0	0	6	16	4	6	26724	10	0	4	80000	10	26732	26732	26732	26732	26728

LDRSH (register, uxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations