Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

AND (register, 32-bit)

Test 1: uops

Code:

  and w0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10041035806186225100010001000169160103510357283868100010002000103541111001100000073141119371000100010361036103610361036
100410357061862251000100010001691601035103572838681000100020001035411110011000001873141119371000100010361036103610361036
10041035706186225100010001000169160103510357283868100010002000103541111001100000073141119371000100010361036103610361036
10041035806186225100010001000169161103510357283868100010002000103541111001100000073141119911000100010361036103610361036
10041035806186225100010001000169161103510357283868100010002000103541111001100000073141119371000100010361036103610361036
10041035806186225100010001000169161103510357283868100010002000103541111001100000073141119371000100010361036103610361036
10041035706186225100010001000169161103510357283868100010002000103541111001100000073141119371000100010361036103610361036
10041035806186225100010001000169160103510357283868100010002000103541111001100000073141119371000100010361036103610361036
10041035806186225100010001000169160103510357283868100010002000103541111001100000073141119371000100010361036103610361036
10041035706186225100010001000169160103510357283868100010002000103541111001100000073141119371000100010361036103610361036

Test 2: Latency 1->2

Code:

  and w0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)0318191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102041003575000619877251010010100101008866449695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
102041003575000619877251010010100101008866449695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
102041003575000619877251010010100101008866449695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
1020410035750003469877251010010100101008866449695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
102041003575000619877251010010100101008866449695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
102041003575000619877251010010100101008866449695510035100358580387221010010200202001003541111020110099100101001001071013711994110000101001003610036100361003610036
102041003575000619877251010010100101008866449695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
102041003575000619877251010010100101008866449695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
102041007975000619877251010010100101008866449695510035100358580387221010010200202001003541111020110099100101001000071013711994110000101001003610036100361003610036
102041003575000619877251010010100101008866449695510035100358580387221010010200202001003541111020110099100101001002671013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024100357512016698632510010100101001088784104969551003510035860238740100101002020020100354111100211091010010105036400054133994010000100101003610036100361003610036
100241003575006198632510010100101001088784104969551008010080860238740100101002020020100354111100211091010010100186400034733994010000100101003610081100361003610036
10024100357500619863251001010010100108878410496955100351003586023874010010100202002010035411110021109101001010006400034133994010000100101003610036100361003610036
1002410035750883979863251001010010100108878410496955100351003586023874010319100202002010035411110021109101001010006400034133994010000100101003610036100361003610036
10024100357500619863251001010010100108878410496955100351003586023874010010100202002010035411110021109101001010006400034133994010000100101012910036100361003610036
10024100357500619863251001010010100108878410496955100351003586023874010010100202002010035411110021109101001010006400034133994010000100101003610036100361003610036
10024100357500619863251001010010100108878410496955100351003586023874010010100202002010035411110021109101001010006400034133994010000100101003610036100361003610036
100241003575001039863251001010010100108878410496955100351003586023874010010100202002010035411110021109101001010006400034133994010000100101003610036100361003610036
10024100357500619863251001010010100108878410496955100351003586023874010010100202002010035411110021109101001010006400034133994010000100101003610036100361003610036
10024100357512046798742510010100101001088784104969551003510035860238740100101002020020100354111100211091010010100606400034733994010000100101003610036100361003610036

Test 3: Latency 1->3

Code:

  and w0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357500061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010000671013711994110000101001003610036100361003610036
10204100357500061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010000371013711994110000101001003610036100361003610036
102041003575000619877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100011571013711994110000101001003610036100361003610036
102041003575010619877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100001271013711994110000101001003610036100361003610036
10204100357500061987725101001010010100886640496955100351003585803872210100102002020010035412110201100991001010010000371013711994110000101001003610083100831003610036
102041003575000619877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100009371013711994110000101001003610036100361003610036
102041003575000619877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100009671013711994110000101001003610036100361003610036
10204100357500061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010000971013711994110000101001003610036100361003610036
10204100357500061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010000371013711994110000101001003610036100361003610036
102041003576000619877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100001271013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)033f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575619863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575619863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100364024122994010000100101003610036100361003610036
100241003576619863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575619863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575619863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575619863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100964024122994010000100101003610036100361003610036
100251003575619863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100064024122994010000100101003610036100361003610036
1002410035756198632510010100101001088784149695510035100358602387401001010020200201003541111002110910100101045364024122994010000100101003610036100361003610036
100241003575619863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100064024122994010000100101003610036100361003610036
100241003575619863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100064024122994010000100101003610036100361003610036

Test 4: throughput

Count: 8

Code:

  and w0, w8, w9
  and w1, w8, w9
  and w2, w8, w9
  and w3, w8, w9
  and w4, w8, w9
  and w5, w8, w9
  and w6, w8, w9
  and w7, w8, w9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1673

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020413390100035258010080100801004005000491030613386133863323333418010080200160200133863911802011009910080100100005110219111338380000801001338713387133871338713387
80204133861000304258010080100801004005000491030613386133863323333418010080200160200133863911802011009910080100100205110119111338380000801001338713387133871338713387
8020413386100035258010080100801004005000491030613386133863323333418010080200160200133863911802011009910080100100005110119111338380000801001338713387133871338713387
8020413386101935258010080100801004005000491030613386133863323333418010080200160200133863911802011009910080100100005110119111338380000801001338713387133871338713387
8020413386101035258010080100801004005001491030613386133863323333418010080200160200133863911802011009910080100100135110119111338380000801001338713387133871338713387
8020413386100035258010080100801004005000491030613386133863323333418010080200160200133863911802011009910080100100005110119111338380000801001338713387133871338713387
8020413386100058258010080100801004005000491030613386133863323333418010080200160200133863911802011009910080100100105110119111338380000801001338713387133871338713387
8020413386101035258010080100801004005000491030613386133863323333418010080200160200133863911802011009910080100100005110119111338380000801001338713387133871338713387
8020413386100069258010080100801004005000491030613386133863323333418010080200160200133863911802011009910080100100005110119111338380000801001338713387133871338713387
8020413386101035258010080100801004005000491030613386133863323333418010080200160200133863911802011009910080100100005110119211338380000801001338713387133871338713387

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024133861000352580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010005020319111336880000800101337213372133721337213372
80024133711000352580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010005020219221336880000800101337213372133721337213372
80024133711000352580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010065020119111336880000800101337213372133721337213372
80024133711000352580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010005020119111336880000800101337213372133721337213372
80024133711000352580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010105020119111336880000800101337213372133721337213372
80024133711000352580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010005020119221336880000800101337213372133721337213372
80024133711010352580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010005020119111336880000800101337213372133721337213372
80024133711000352580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010005020119111336880000800101337213372133721337213372
80024133711000352580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010135020119111336880000800101337213372133721337213372
80024133711000352580010800108001040005049102911337113371333033348800108002016002013371391180021109108001010135020119111336880000800101337213372133721337213372