Firestorm: LDRSB (register, 32-bit) measurements

Code:

  ldrsb w0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	3	1	1	1	1	0	0	21	1	0	2	388	3	7	7	0	25	1000	1000	1000	15480	1	403	403	225	3	261	1000	1000	2000	404	85	1	1	1001	0	1000	1000	1020	19	43	1058	1	0	1	61	1040	6	1	58	43	19	0	73	1	16	1	1	400	13	13	5	1000	404	404	404	382	404
1004	403	2	1	1	1	1	0	0	66	1	0	2	367	2	0	7	18	25	1000	1000	1000	15501	1	403	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	1019	19	43	1059	1	0	2	61	1040	6	1	19	43	19	0	73	1	16	1	1	400	13	13	5	1000	404	404	404	404	404
1004	402	3	1	1	1	1	0	1	67	1	0	2	387	3	7	9	19	25	1000	1000	1000	14533	1	402	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	1020	20	43	1059	0	0	2	60	1039	6	0	59	43	19	1	73	1	16	1	1	400	13	13	5	1000	404	404	404	404	403
1004	403	3	1	1	1	1	0	0	67	1	0	0	387	3	7	0	21	25	1000	1000	1000	15555	1	403	382	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	1020	20	43	1059	0	0	1	61	1039	0	1	59	43	19	0	73	1	16	1	1	379	13	13	5	1000	404	383	404	404	404
1004	402	3	1	1	1	0	0	0	67	0	0	3	388	3	0	7	19	25	1000	1000	1000	15555	1	402	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	1020	20	43	1059	1	0	0	60	1040	6	1	58	0	19	1	73	1	16	1	1	400	13	13	5	1000	404	404	404	404	404
1004	406	3	1	1	0	0	0	0	67	1	0	2	392	3	9	0	21	25	1000	1000	1000	15480	1	403	381	225	3	261	1000	1000	2000	402	85	1	1	1001	0	1000	1000	1020	19	43	1019	0	0	1	60	1000	0	0	19	43	19	0	73	1	16	1	1	378	13	13	5	1000	404	382	404	404	404
1004	402	3	1	1	1	1	0	0	21	1	0	3	388	3	7	7	20	25	1000	1000	1000	15597	1	403	403	204	3	260	1000	1000	2000	403	86	1	1	1001	1	1000	1000	1021	20	43	1058	1	0	1	61	1040	6	1	58	43	19	1	73	1	16	1	1	400	13	13	5	1000	403	404	404	382	404
1004	403	3	1	1	1	1	0	0	67	1	0	0	388	2	7	0	18	25	1000	1000	1000	15501	1	406	403	226	3	260	1000	1000	2000	403	86	1	1	1001	0	1000	1000	1020	19	43	1059	0	0	1	60	1040	6	1	58	43	19	1	73	1	16	1	1	400	13	13	5	1000	404	404	404	404	404
1004	403	3	1	1	1	1	0	0	67	1	0	3	388	3	7	7	19	25	1000	1000	1000	15559	1	403	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	1019	21	43	1059	1	0	1	21	1040	6	1	58	43	19	1	73	1	16	1	1	400	13	13	5	1000	404	404	383	403	404
1004	403	2	1	1	1	0	0	0	67	1	0	2	388	3	0	7	0	25	1000	1000	1000	15526	1	381	403	225	3	261	1000	1000	2000	403	85	1	1	1001	0	1000	1000	1022	20	43	1059	0	0	1	21	1039	6	1	59	45	19	2	73	1	16	1	1	400	13	13	5	1000	382	406	382	404	382

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	524	0	0	0	0	0	0	1	0	1	0	70020	69790	59713	25	40104	30100	10001	30100	10000	616041	3341470	1	49	66974	0	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	3	10003	1	1	0	2610	1	71	1	1	69814	30000	0	10	13	10000	30100	70055	70055	70055	70036	70036
40204	70054	525	0	0	0	0	0	0	1	0	0	0	70020	69782	59713	25	40104	30100	10001	30100	10000	616041	3342398	0	49	66980	0	70053	70054	64650	3	64957	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	0	0	2610	1	71	1	1	69817	30000	13	10	13	10000	30100	70055	70036	70036	70055	70036
40204	70054	524	0	0	0	0	0	0	1	0	0	0	70039	69764	59695	25	40100	30103	10001	30100	10000	616041	3342398	0	49	66971	0	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	2610	1	71	1	1	69814	30000	13	13	13	10000	30100	70055	70055	70036	70055	70055
40204	70054	525	0	0	0	0	0	0	1	0	0	0	70020	69785	59713	25	40100	30103	10001	30100	10000	616041	3341470	1	49	66971	0	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	0	0	2610	1	71	1	1	69817	30003	0	13	13	10000	30100	70036	70052	70052	70055	70036
40204	70051	525	0	0	0	0	0	0	0	0	1	0	70039	69785	59713	25	40104	30103	10001	30100	10000	616175	3342398	1	49	66971	0	70054	70054	64650	3	64938	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	0	0	0	2610	1	71	1	1	69817	30003	13	0	0	10000	30100	70036	70055	70055	70052	70055
40204	70054	525	0	0	0	0	0	0	1	0	1	0	70036	69764	59713	25	40100	30103	10001	30100	10000	616041	3342398	1	49	66955	0	70054	70035	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	2610	1	71	1	1	69814	30003	0	13	13	10000	30100	70052	70052	70055	70052	70055
40204	70035	524	0	0	0	0	0	0	1	0	0	0	70036	69764	59713	25	40104	30100	10001	30100	10000	616041	3342398	1	49	66978	0	70054	70054	64631	3	64957	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	0	10000	1	1	0	2610	1	71	1	1	69798	30000	0	0	13	10000	30100	70055	70055	70055	70060	70036
40204	70054	525	0	0	0	0	0	0	1	0	0	0	70036	69785	59713	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66974	0	70035	70035	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	2610	1	71	1	1	69817	30003	13	0	0	10000	30100	70055	70055	70036	70036	70055
40204	70035	524	0	0	0	0	0	0	1	0	0	0	70020	69785	59695	25	40104	30103	10001	30100	10000	616175	3342398	0	49	66971	0	70054	70054	64631	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	0	0	2610	1	71	1	1	69817	30003	13	0	13	10000	30100	70055	70036	70055	70055	70036
40204	70051	525	0	0	0	1	0	0	1	0	1	0	70039	69764	59713	25	40104	30103	10001	30100	10000	616041	3341470	0	49	66974	0	70035	70054	64631	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	10000	1	1	0	2610	1	71	1	1	69817	30003	13	13	13	10000	30100	70052	70055	70036	70055	70055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	19	1e	1f	22	23	3f	43	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	1	0	0	0	6	0	0	0	70032	0	0	69760	59784	25	40014	30013	10001	30010	10000	616952	3341470	1	49	66967	70047	70047	64665	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	3	0	10000	1	0	1	0	2520	6	71	4	2	69810	30003	9	0	6	10000	30010	70036	70036	70052	70131	70048
40024	70050	524	0	1	0	0	1	0	1	0	70032	0	0	69728	59725	25	40058	30013	10001	30010	10000	616982	3341470	1	49	66970	70050	70035	64653	3	64972	40010	30020	10000	60020	20000	70266	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	1	0	2520	4	71	4	4	69810	30012	6	6	6	10000	30010	70051	70048	70048	70048	70048
40024	70035	525	0	0	0	0	1	0	1	0	70038	0	0	69728	59792	25	40014	30013	10001	30010	10000	616952	3341470	1	49	66970	70050	70047	64665	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	1	0	2520	4	71	4	4	69813	30003	6	0	9	10000	30010	70048	70048	70048	70054	70048
40024	70050	525	0	0	0	0	1	0	0	0	70032	0	0	69743	59822	25	40018	30016	10001	30010	10000	617027	3342446	1	49	66975	70055	70055	64673	3	64980	40010	30020	10000	60020	20000	70055	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	2	10000	0	0	10000	1	0	1	0	2520	2	71	4	3	69810	30003	6	6	9	10000	30010	70048	70036	70036	70054	70036
40024	70047	525	0	1	0	0	1	0	0	0	70020	0	0	69760	59752	25	40014	30013	10001	30010	10000	616952	3341470	1	49	66955	70047	70035	64665	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	3	0	10000	1	0	1	0	2520	4	71	2	4	69798	30000	9	6	6	10000	30010	70036	70048	70048	70054	70048
40024	70076	525	0	0	0	0	1	0	0	0	70032	0	0	69743	59794	25	40014	30013	10001	30010	10000	616952	3342062	1	49	66967	70047	70035	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	1	0	2520	4	71	4	3	69810	30003	6	9	6	10000	30010	70036	70048	70048	70054	70051
40024	70050	525	0	0	0	0	1	0	1	0	70032	0	0	69743	59768	123	40014	30010	10001	30010	10000	616952	3342062	1	49	66955	70035	70035	64665	3	64975	40010	30020	10000	60020	20000	70151	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	1	0	2520	2	71	4	4	69810	30003	9	9	6	10000	30010	70051	70048	70144	70146	70048
40024	70047	524	0	0	0	0	1	0	0	0	70032	0	0	69760	59808	25	40014	30013	10001	30010	10000	616982	3341470	1	49	66955	70047	70047	64665	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10001	0	1	10001	1	1	1	0	2520	2	71	4	3	69818	30006	6	6	6	10000	30010	70056	70056	70056	70062	70051
40024	70047	525	0	0	0	0	1	0	0	0	70035	0	0	69728	59830	25	40014	30013	10001	30010	10000	617068	3342062	1	49	66967	70047	70035	64653	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	1	0	2520	4	71	4	2	69798	30003	0	0	9	10000	30010	70051	70051	70052	70074	70048
40024	70047	524	0	0	0	0	6	0	0	0	70035	0	0	69728	59823	25	40014	30013	10001	30010	10000	617068	3341470	1	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	0	1	0	2520	2	71	4	4	69810	30003	6	6	6	10000	30010	70036	70036	70048	70042	70040

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70048	525	0	0	1	0	1	1	1	0	1	0	0	70038	69784	59712	25	40108	30106	10002	30100	10000	616032	3342350	0	49	66967	70047	70047	64643	3	64938	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10000	0	0	0	3	10000	1	0	1	0	0	0	2610	1	71	1	1	69828	30003	0	6	0	10000	30100	70042	70054	70054	70054	70042
40204	70053	524	1	1	0	1	0	0	1	0	0	0	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616015	3341470	0	49	66967	70047	70047	64643	3	64938	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	0	1	1	1	0	0	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70054	70054	70054	70054	70054
40204	70053	524	1	0	0	0	0	1	0	0	0	0	0	70032	69735	59695	25	40104	30100	10001	30100	10000	616015	3341470	0	49	66967	70047	70047	64643	3	64950	40100	30200	10000	60200	20000	70047	35	2	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69798	30000	6	0	6	10000	30100	70048	70048	70048	70036	70048
40204	70047	524	0	0	0	0	0	0	2	0	0	0	1	70038	69784	59712	25	40104	30106	10002	30100	10057	616545	3342878	0	49	66967	70035	70047	64643	3	64938	40100	30200	10000	60200	20000	70052	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	3	10000	1	0	1	0	0	0	2610	1	71	1	1	69810	30003	0	6	6	10000	30100	70048	70048	70048	70048	70036
40204	70047	524	0	0	0	0	0	0	6	0	1	0	0	70038	69784	59712	25	40108	30106	10002	30100	10000	616032	3341769	0	49	66967	70047	70047	64643	3	64950	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	1	1	1	0	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70054	70054	70054	70054	70042
40204	70053	525	1	1	0	1	0	0	1	0	0	0	0	70020	69735	59706	25	40104	30103	10000	30100	10000	616015	3342062	0	49	66967	70047	70047	64631	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	1	1	1	0	0	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70054	70042	70054	70054	70054
40204	70053	525	1	0	0	1	0	1	1	0	1	0	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616015	3341470	0	49	66967	70047	70047	64643	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	3	0	0	10000	1	1	1	1	0	0	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70054	70054	70054	70054	70054
40204	70053	524	1	0	0	0	0	0	28	0	1	0	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616015	3342794	0	49	66973	70053	70041	64643	3	64944	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	3	1	10002	0	0	1	1	10000	0	0	0	0	0	0	2610	1	71	1	1	69810	30000	6	6	6	10000	30100	70048	70048	70048	70036	70048
40204	70047	525	0	0	0	0	0	0	0	0	1	0	0	70032	69735	59695	25	40104	30103	10001	30100	10000	616175	3342062	0	49	66973	70053	70053	64649	3	64956	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	3	1	10001	0	0	2	1	10000	1	0	1	0	0	0	2610	1	71	1	1	69798	30003	6	0	0	10000	30100	70036	70048	70048	70057	70048
40204	70035	524	0	0	0	0	0	1	2	0	0	0	1	70038	69784	59712	25	40108	30106	10002	30100	10000	616032	3342350	0	49	66955	70047	70035	64631	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	1	0	1	1	0	2610	1	71	1	1	69810	30003	6	6	6	10000	30100	70048	70048	70048	70036	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	1	0	1	0	1	1	0	0	16	0	0	0	3	70032	69748	59873	25	40014	30013	10001	30010	10000	617068	3342206	49	66969	70048	70047	64653	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	0	0	2526	15	71	16	16	69813	30003	6	6	9	10000	30010	70080	70078	70095	70051	70048
40024	70047	524	1	0	1	0	0	0	0	0	1	0	1	0	3	70032	69777	59706	25	40014	30010	10001	30010	10000	616982	3341470	49	66970	70035	70035	64665	3	64972	40010	30020	10000	60020	20000	70412	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	4	2	0	10000	0	1	0	0	2526	16	95	14	16	69798	30003	0	6	9	10000	30010	70102	70091	70076	70050	70051
40024	70035	525	1	0	1	0	0	0	0	0	574	0	0	0	3	70035	70008	59706	25	40010	30010	10000	30010	10000	616952	3341470	49	66970	70050	70050	64653	3	64975	40010	30677	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	2526	17	71	15	15	69798	30003	0	0	9	10000	30010	70053	70101	70056	70051	70051
40024	70050	525	1	0	1	1	0	0	0	0	0	0	0	0	3	70033	69761	59752	25	40014	30010	10001	30010	10000	616991	3341614	49	66970	70050	70047	64654	3	64975	40010	30020	10110	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	2526	16	71	14	15	69810	30003	9	0	9	10000	30010	70052	70054	70048	70036	70051
40024	70035	525	1	0	1	0	0	0	4	0	6	0	0	0	3	70020	69773	59863	25	40014	30010	10000	30010	10000	616982	3341470	49	66970	70050	70050	64674	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	3	10000	1	0	1	0	2526	15	71	14	15	69810	30003	6	6	0	10000	30010	70104	70080	70120	70051	70051
40024	70050	525	1	0	1	0	0	0	0	0	6	0	0	0	3	70020	69800	59706	25	40014	30010	10001	30010	10000	616982	3342302	49	66967	70047	70035	64665	3	64975	40010	30347	10055	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	1	0	0	10000	0	1	0	0	2526	16	71	16	15	69798	30003	9	0	0	10000	30010	70094	70066	70058	70054	70048
40024	70050	525	1	0	1	0	0	0	0	0	1	0	1	0	3	70035	69774	59706	25	40061	30010	10000	30010	10000	616982	3342206	49	67239	70050	70050	64668	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	2526	17	71	11	15	69813	30000	9	0	6	10000	30010	70091	70069	70062	70051	70051
40024	70047	524	1	0	1	0	0	0	0	0	1	0	0	0	3	70035	69778	59706	25	40014	30013	10001	30010	10000	617018	3352586	49	66970	70047	70035	64670	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	2526	12	71	15	16	69873	30003	6	0	6	10000	30010	70095	70096	70124	70051	70055
40024	70087	524	1	1	1	0	0	0	0	0	1	0	1	0	3	70035	69860	59706	25	40014	30013	10001	30010	10000	616952	3341470	49	66970	70050	70050	64653	3	64975	40010	30020	10000	60344	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	2526	15	71	14	16	69813	30003	9	0	9	10000	30010	70051	70056	70036	70036	70036
40024	70050	525	1	0	1	0	1	0	0	0	6	0	0	0	3	70032	69801	59709	25	40014	30013	10001	30010	10000	616982	3342206	49	66967	70047	70050	64653	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	0	1	10000	0	0	0	10000	1	1	0	0	2526	17	71	22	18	69810	30003	6	9	6	10000	30010	70094	70079	70080	70051	70051

Test 4: throughput

Count: 8

Code:

  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]
  ldrsb w0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26738	200	0	0	0	0	45	1	0	1	26712	2	12	12	16	25	80100	100	80000	100	80014	500	1167303	49	23647	0	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80000	0	39	80039	6	1	39	43	1	1	1	5118	0	16	0	0	26724	10	10	4	80000	100	26728	26728	26728	26708	26708
80204	26727	200	0	0	0	0	45	1	0	0	26712	2	1	12	16	25	80100	100	80000	100	80014	500	1167303	49	23647	0	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	39	80039	6	0	39	43	1	1	1	5118	0	16	0	0	26724	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26707	200	0	0	0	0	45	1	0	1	26692	2	12	12	28	25	80100	100	80000	100	80015	500	1177116	49	23647	0	26707	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	42	80039	6	1	39	0	1	1	1	5118	0	16	0	0	26724	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	0	0	1	0	1	26712	2	12	12	18	25	80100	100	80130	100	80015	500	1166811	49	23637	0	26730	26711	16635	6	16679	80116	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	1	100	80000	43	80039	0	39	80039	6	0	39	0	1	1	1	5118	0	16	0	0	26724	10	0	4	80000	100	26728	26728	26728	26728	26728
80204	26727	201	0	1	0	0	45	1	0	1	26712	2	12	0	16	25	80100	100	80000	100	80015	500	1177116	49	23627	0	26727	26727	16655	6	16659	80115	200	80024	200	160048	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	39	80039	6	1	0	43	1	1	1	5118	0	16	0	0	26724	10	0	0	80000	100	26708	26708	26708	26728	26708
80204	26727	200	0	0	0	0	45	1	0	0	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1167303	49	23647	0	26707	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	80039	0	39	80039	6	1	39	43	1	1	1	5118	0	16	0	0	26726	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	0	45	0	0	1	26692	0	12	12	16	25	80100	100	80000	100	80015	500	1177116	49	23647	0	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	39	80000	6	1	39	43	1	1	1	5118	0	16	0	0	26724	0	0	0	80000	100	26728	26728	26728	26732	26728
80204	26727	201	0	1	0	0	46	1	0	1	26712	2	12	12	0	25	80100	100	80000	100	80014	500	1167198	49	23647	0	26727	26727	16659	6	16659	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	42	80050	0	1	39	43	1	1	1	5118	0	16	0	0	26724	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	1	0	0	45	1	0	1	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1177116	49	23656	0	26727	26727	16655	6	16679	80116	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	1	3	80039	6	1	39	43	1	1	1	5118	0	16	0	0	26724	10	10	0	80000	100	26728	26708	26728	26728	26728
80204	26707	200	0	0	0	0	45	1	0	1	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1167303	49	23647	0	26727	26727	16655	6	16679	80116	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	80039	0	39	80039	6	1	39	43	1	1	1	5118	0	16	0	0	26724	10	10	4	80000	100	26728	26728	26728	26728	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26733	200	1	0	1	0	0	0	0	65	1	0	1	26717	2	18	18	29	25	80010	10	80000	10	80000	50	1166960	1	49	23652	26732	26735	16677	3	16712	80010	20	80000	20	160000	26733	81	1	1	80021	10	9	10	80000	10	80000	0	10	80019	21	41	80019	0	0	0	59	80038	6	1	0	39	0	0	5020	6	16	5	4	26725	10	6	2	80000	10	26741	26737	26726	26709	26709
80024	26728	200	0	0	0	0	0	0	0	41	1	0	1	26707	0	18	0	12	25	80010	10	80000	10	80000	55	1167605	1	49	23648	26708	26727	16672	3	16688	80010	20	80000	20	160000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80035	0	0	0	0	80035	6	1	35	43	0	0	5020	5	16	5	4	26719	0	6	2	80000	10	26736	26723	26723	26723	26729
80024	26722	200	0	0	0	0	0	0	0	41	1	0	1	26707	2	12	18	0	25	80010	10	80000	10	80000	50	1167605	1	49	23628	26708	26722	16667	3	16702	80010	20	80000	20	160000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80039	0	0	0	38	80039	6	1	0	0	0	0	5020	5	16	4	5	26719	6	6	2	80000	10	26754	26723	26729	26709	26728
80024	26708	200	0	0	0	0	0	0	0	41	1	0	0	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	1	49	23642	26722	26708	16667	3	16688	80010	20	80000	20	160000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80039	0	0	0	35	80035	6	1	35	43	0	0	5020	5	16	4	5	26719	6	0	4	80000	10	26727	26744	26729	26723	26728
80024	26722	200	0	0	0	0	0	1	0	41	1	0	1	26707	2	0	18	15	25	80010	10	80000	10	80000	50	1166750	1	49	23642	26722	26708	16652	3	16688	80010	20	80000	20	160000	26722	56	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	39	80035	0	0	0	0	80035	0	1	35	0	16	0	5020	5	16	4	5	26729	9	9	2	80000	10	26739	26738	26733	26734	26715
80024	26733	201	1	1	1	0	0	0	0	64	1	0	3	26717	2	18	18	16	25	80010	10	80000	10	80000	50	1170204	1	49	23652	26715	26732	16677	3	16712	80010	20	80000	20	160000	26715	81	1	1	80021	10	9	10	80000	10	80000	1	10	80019	20	42	80058	1	0	1	59	80038	0	1	57	42	19	1	5020	5	16	5	5	26729	9	9	2	80000	10	26733	26725	26734	26740	26715
80024	26714	200	1	1	1	0	1	1	0	66	1	0	1	26717	2	18	0	16	25	80010	10	80000	10	80000	50	1165822	1	49	23652	26733	26732	16677	3	16712	80010	20	80000	20	160000	26733	81	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	80057	0	0	0	21	80039	6	1	57	0	19	0	5020	4	16	4	5	26729	9	9	0	80000	10	26746	26716	26716	26734	26733
80024	26732	200	1	0	0	0	1	0	0	65	1	0	3	26717	2	0	18	15	25	80010	10	80000	10	80000	50	1167599	0	49	23653	26714	26732	16677	3	16712	80010	20	80000	20	160000	26732	81	1	1	80021	10	9	10	80000	10	80000	1	10	80019	19	42	80019	0	0	0	59	80038	6	0	57	0	19	0	5020	5	16	5	5	26729	9	0	2	80000	10	26736	26739	26733	26716	26734
80024	26733	200	1	0	1	0	0	0	0	21	0	0	3	26700	3	0	18	15	25	80010	10	80000	10	80000	50	1166960	0	49	23653	26732	26733	16677	3	16712	80010	20	80000	20	160000	26732	82	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	0	80057	1	0	1	59	80000	0	1	56	42	19	0	5020	5	16	5	5	26729	9	0	2	80000	10	26746	26733	26733	26733	26716
80024	26716	200	1	0	0	0	1	1	1	65	0	0	1	26717	2	0	18	16	25	80010	10	80000	10	80000	50	1167529	1	49	23634	26733	26732	16677	3	16712	80010	20	80000	20	160000	26715	81	1	1	80021	10	9	10	80000	10	80000	1	10	80020	18	42	80019	1	0	0	62	80037	6	0	58	0	19	1	5020	5	16	5	4	26729	9	9	0	80000	10	26733	26733	26733	26733	26716

LDRSB (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations