Firestorm: STR (register, 64-bit) measurements

Code:

  str x0, [x6, x7]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	0	3	1	0	527	16	16	0	25	1000	1000	1000	22448	0	542	542	355	3	401	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	1	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	1	0	527	16	16	1	25	1000	1000	1000	22472	0	542	542	356	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	540	1000	544	544	544	544	544
1004	543	4	9	3	1	0	527	16	16	1	25	1000	1000	1000	22448	0	542	542	355	3	400	1000	1000	3000	542	543	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	1	0	528	16	16	0	25	1000	1000	1000	22448	0	542	542	355	3	400	1000	1000	3000	543	543	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	1	0	527	16	16	1	25	1000	1000	1000	22448	0	542	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	1	0	527	16	16	0	25	1000	1000	1000	22448	0	542	542	355	3	400	1000	1000	3000	543	543	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	1	0	528	16	16	0	25	1000	1000	1000	22472	0	542	542	367	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	543	4	0	3	0	0	527	16	16	0	25	1000	1000	1000	22448	0	542	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	544	544
1004	543	4	0	3	0	0	528	16	16	0	25	1000	1000	1000	22472	0	543	543	356	3	400	1000	1000	3000	543	543	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	539	1000	543	544	544	544	544
1004	543	4	0	3	1	0	527	16	16	1	25	1000	1000	1000	22472	0	542	542	356	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	1002	2	42	73	1	16	1	1	540	1000	543	543	543	543	543

Count: 8

Code:

  str x0, [x6, x7]
  str x0, [x6, x7]
  str x0, [x6, x7]
  str x0, [x6, x7]
  str x0, [x6, x7]
  str x0, [x6, x7]
  str x0, [x6, x7]
  str x0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5e	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bb	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40052	300	1	0	0	0	0	0	19	1	0	0	1	40043	16	16	7	25	80100	100	80000	100	80007	500	1840246	0	1	49	36980	40058	40058	29976	7	30010	80107	200	80016	200	240048	40053	32011	1	1	80201	100	99	100	80000	100	80000	100	80015	14	0	0	1	80016	0	1	19	80002	0	14	0	14	0	1	1	1	5118	0	1	16	0	0	40056	0	80000	100	40053	40062	40053	40061	40053
80204	40059	300	1	0	0	0	0	0	17	1	0	0	1	40032	0	0	5	25	80100	100	80000	100	80007	500	1839718	0	0	49	36979	40052	40059	29977	7	30010	80107	200	80016	200	240048	40047	32000	1	1	80201	100	99	100	80000	100	80000	100	80014	15	36	0	0	80016	0	0	15	80002	0	16	36	14	0	1	1	1	5118	0	0	16	0	0	40054	0	80000	100	40059	40050	40060	40048	40053
80204	40047	300	1	0	1	0	0	0	21	1	0	0	1	40044	0	0	0	25	80100	100	80000	100	80007	500	1839910	0	1	49	36980	40059	40058	29967	7	29999	80107	200	80016	200	240048	40059	32000	1	1	80201	100	99	100	80000	100	80000	100	80014	15	0	0	0	80014	0	0	18	80000	0	14	0	14	1	1	1	1	5118	0	0	16	0	0	40050	0	80000	100	40048	40059	40048	40048	40048
80204	40047	300	1	0	1	0	0	0	19	0	0	0	0	40044	0	16	2	25	80100	100	80000	100	80007	500	1840323	0	1	49	36980	40047	40048	29978	7	30002	80107	200	80016	200	240048	40058	32011	1	1	80201	100	99	100	80000	100	80000	100	80014	15	36	0	0	80016	0	0	20	80002	0	16	0	14	1	1	1	1	5118	0	0	16	0	0	40055	0	80000	100	40059	40050	40060	40052	40048
80204	40060	300	1	0	0	0	0	0	19	1	0	0	1	40037	16	16	5	25	80100	100	80000	100	80006	500	1839987	0	1	49	36967	40058	40050	29969	7	30004	80107	200	80016	200	240048	40060	32004	1	1	80201	100	99	100	80000	100	80000	100	80014	15	0	0	1	80014	0	0	18	80002	0	16	36	14	0	1	1	1	5118	0	0	16	0	0	40044	0	80000	100	40052	40060	40053	40048	40048
80204	40058	300	1	0	1	0	0	0	19	0	0	0	1	40034	0	16	5	25	80100	100	80000	100	80006	500	1840294	0	0	49	36962	40042	40042	29961	7	30001	80107	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	30	0	80002	0	0	2	80002	0	2	0	0	0	1	1	1	5118	0	0	16	0	0	40037	0	80000	100	40043	40052	40043	40052	40043
80204	40051	300	0	0	0	0	0	0	3	1	0	0	0	40036	16	16	0	25	80100	100	80000	100	80007	500	1839455	0	0	49	36962	40042	40042	29961	7	29992	80107	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	0	80002	10	0	8	80002	0	2	34	0	0	1	1	1	5118	0	0	16	0	0	40037	0	80000	100	40050	40043	40041	40043	40053
80204	40042	299	0	0	0	0	0	0	3	1	0	0	0	40027	16	16	0	25	80100	100	80000	100	80007	500	1839378	0	0	49	36960	40042	40042	29959	7	29992	80106	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	2	0	80000	0	1	8	80002	0	2	0	0	0	1	1	1	5118	0	0	16	0	0	40039	0	80000	100	40043	40043	40043	40043	40059
80204	40042	299	0	0	0	0	0	0	3	0	0	0	0	40025	16	0	0	25	80100	100	80000	100	80007	500	1839378	0	0	49	36962	40051	40042	29969	7	29994	80107	200	80016	200	240048	40050	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	0	80000	0	2	2	80002	0	2	34	0	0	1	1	1	5118	0	0	16	0	0	40039	0	80000	100	40041	40041	40043	40051	40061
80204	40042	300	0	0	0	0	0	0	9	1	0	0	0	40027	16	16	0	25	80100	100	80000	100	80007	500	1839455	0	0	49	36962	40051	40042	29961	7	29994	80107	200	80016	200	240048	40050	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	0	80000	34	0	26	80002	0	2	34	0	0	1	1	1	5118	0	0	16	0	0	40037	0	80000	100	40041	40043	40043	40041	40059

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	19	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	0	0	0	0	6	0	0	40027	0	0	0	25	80010	10	80000	10	80000	50	1839856	0	49	36962	40051	40042	29985	3	30022	80010	20	80000	20	240000	40040	40050	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	0	0	2	80002	2	0	0	0	0	5020	0	3	16	4	4	40039	80000	10	40051	40041	40043	40043	40052
80024	40040	300	0	0	0	1	0	0	17	1	1	40314	0	16	8	25	80010	10	80000	10	80000	50	1840174	0	49	36967	40047	40059	29993	3	30031	80010	20	80000	20	240000	40059	40058	1	1	80021	10	9	10	80000	10	80000	10	80014	14	36	0	0	80016	0	1	18	80002	16	36	14	0	0	5020	0	6	16	6	7	40056	80000	10	40053	40060	40054	40060	40043
80024	40042	300	0	0	0	0	0	0	3	1	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1840244	0	49	36967	40047	40047	29985	3	30032	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	0	0	0	80002	2	34	0	0	0	5020	0	6	16	4	4	40037	80000	10	40050	40043	40043	40041	40051
80024	40042	299	0	0	0	0	0	0	3	1	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1840316	0	49	36978	40052	40052	29987	3	30038	80010	20	80000	20	240000	40053	40058	1	1	80021	10	9	10	80000	10	80000	10	80015	15	0	0	2	80016	0	2	17	80002	16	36	14	0	0	5020	0	3	16	6	4	40056	80000	10	40060	40054	40049	40048	40059
80024	40052	300	1	1	0	1	0	0	19	1	0	40034	16	16	0	25	80010	10	80000	10	80000	50	1839692	0	49	36967	40060	40052	29986	3	30038	80010	20	80000	20	240000	40050	40053	1	1	80021	10	9	10	80000	10	80000	10	80014	14	36	2	0	80076	0	0	27	80000	16	0	14	1	0	5020	0	3	16	3	4	40044	80000	10	40054	40049	40048	40048	40052
80024	40059	300	1	1	0	1	0	144	3	1	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1840174	0	49	36980	40058	40059	29994	3	30030	80010	20	80000	20	240000	40058	40058	1	1	80021	10	9	10	80000	10	80000	10	80014	15	35	0	1	80016	0	2	20	80002	16	36	14	1	0	5020	0	3	16	3	4	40054	80000	10	40059	40048	40060	40053	40060
80024	40047	300	1	0	0	0	0	0	19	1	1	40043	16	15	5	25	80010	10	80000	10	80000	50	1842761	0	49	36972	40047	40050	29982	3	30032	80010	20	80000	20	240000	40060	40051	1	1	80021	10	9	10	80000	10	80000	10	80015	15	36	0	0	80016	0	0	17	80002	16	36	14	2	0	5020	0	6	16	4	7	40047	80000	10	40060	40053	40059	40060	40059
80024	40052	300	1	1	0	1	0	6	19	1	1	40036	16	16	2	25	80010	10	80000	10	80000	50	1840220	0	49	36972	40061	40051	29982	3	30027	80010	20	80000	20	240000	40060	40047	1	1	80021	10	9	10	80000	10	80000	10	80014	14	36	2	0	80016	0	0	19	80000	16	40	0	0	0	5020	0	4	16	4	4	40039	80000	10	40041	40043	40043	40043	40052
80024	40042	300	0	0	0	0	0	0	3	0	0	40027	16	16	9	25	80010	10	80000	10	80000	50	1840174	0	49	36972	40049	40052	29987	3	30027	80010	20	80000	20	240000	40050	40052	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	0	0	8	80002	2	0	0	0	0	5020	0	4	16	3	4	40039	80000	10	40043	40043	40043	40043	40043
80024	40049	299	0	0	0	0	0	0	9	1	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1840199	0	49	36973	40060	40052	29982	3	30038	80010	20	80000	20	240000	40050	40053	1	1	80021	10	9	10	80000	10	80000	10	80014	14	0	0	2	80016	0	0	16	80002	16	36	14	1	0	5020	0	4	16	3	9	40056	80000	10	40053	40058	40054	40059	40048

STR (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations