Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMP (sxth, 32-bit)

Test 1: uops

Code:

  cmp w0, w1, sxth
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)033a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb access (a0)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
100470952661000304252000200010004087717097094982135611000100020007097811100110004177422446842000710710710710710
100470952891000304252000200010004087717097094982135611000100020007097811100110000077422446842000710710710710710
100470952661000304252000200010004087717097094982535611000100020007097811100110000077422446842000710710710710710
100470952661000304252000200010004087717097094982535611000100020007097811100110000077422446842000710710710710710
100470952661000304252000200010004087717097094982535611000100020007097811100110000077422446842000710710710710710
100470962661000304252000200010004087717097094982535611000100020007097811100110000077422446842000710710710710710
100470952661000304252000200010004087717097094982135611000100020007097811100110000077422446842000710710710710710
100470952661000304252000200010004087717097094982535611000100020007097811100110000077422446842000710710710710710
100470952951000304252000200010004087717097094982535611000100020007097811100110000077422446842000710710710710710
1004709521101000304252000200010004087717097094982535611000100020007097811100110000077422446842000710710710710710

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmp w0, w1, sxth
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)181e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035225000000611000029893253010030100201001956198049269553003530035273693274782010020200302003003514511202011009910020100101000000613101331332995430000101003003630036300363003630036
2020430035225000000611000029893253010030100201001956198049269553003530035273693274782010020200302003003514511202011009910020100101000000613101231322995430000101003003630036300363003630036
2020430035225000000611000029893253010030100201001956198149269553003530035273693274782010020200302003003514511202011009910020100101000000613101231232995430000101003003630036300363003630036
2020430035225000000611000029893253010030100201001956198049269553003530035273693274782010020200302003003514511202011009910020100101000000913101231322995430000101003003630036300363003630036
20204300352250000006110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000004513101331332995430000101003003630036300363003630036
2020430035225000000611000029893253010030100201001956198049269553003530035273693274782010020200302003003514511202011009910020100101000000613101231322995430000101003003630036300363003630036
2020430035225000000611000029893253010030100201001956198049269553003530035273693274782010020200302003003514511202011009910020100101000000013101331332995430000101003003630036300363003630036
2020430035225000000166100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000011413101331322995430000101003003630036300363003630036
2020430035225000000611000029893253010030100201001956198049269553003530035273693274782010020200302003003514511202011009910020100101000004013101231222995430000101003003630036300363003630036
202043003522500001806110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000210313101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)030918191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002430035225000000611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100000012706335132995830000100103003630036300363003630036
200243003522400000061100002989125300103001020010195628914926955300353003527391327525200102002030020300351451120021109102001010010000001270123313112995830000100103003630036300363003630036
20024300352250000002741000029891253001030010200101956289149269553003530035273911627498200102002030020300351451120021109102001010010000001270123311122995830000100103003630036301253003630036
20024300352250000006110000298912530010300102001019562891492695530035300352739132749820010200203002030035145112002110910200101001000000127013331362995830000100103003630036300363003630036
20024300352250020006110000298912530010300102001019562891492695530035300352739132749820010200203002030035145112002110910200101001000156011270143312132995830000100103003630036300363003630036
2002430035225000120061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010200001270133313132995830022100103003630036300363003630036
200243003522400000096410000298912530010300272001019562891492695530035300352739132749820010200203002030035145112002110910200101001001231001270123313132995830000100103003630036300363003630036
200243003522510000061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010000001270123313132995830000100103003630036300363003630036
20024300352250000006110000298912530010300102001019562891492695530035300352739132749820010200203002030035145112002110910200101001000000127013336112995830000100103003630036300363003630036
200243003522600012006110000299012530010300102001019562891492695530035300352739132749820010200203002030035145112002110910200101001000000127017331262995830000100103003630036300363003630036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmp w0, w1, sxth
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202043003522506110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000100013101231222995430000101003003630036300363003630036
202043003522506110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000000013101231222995430000101003003630036300363003630036
202043003522506110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000000013101231222995430000101003003630036300363003630036
202043003522506110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000103013101231222995430000101003003630036300363003630036
202043003522506110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000000013101231222995430000101003003630036300363003630036
202043003522514461100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100002503013101231223001630000101003003630172300363003630036
202043003522566110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000000013101231222995430000101003003630036300363003630036
202043003522506110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000000013101231222995430000101003003630036300363003630036
202043003522506110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000203013101231222995430000101003003630036300363003630036
202043003522506110000298932530100301002010019561980492695530035300352738132747820350202003020030035145112020110099100201001010000000013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)0318191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024300352250000061100242989125300103001020010195628949269553003530035273913274982001020020300203003514511200211091020010100100011541270133122995830000100103003630036300363003630036
20024300352250000061100002989125300103001020010195628949269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
20024300352250000061100002989125300103001020010195628949269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
20024300352250000061100002989125300103001020010195628949269553003530035273913274982001020020300203003514511200211091020010100100001270133122995830000100103003630036300363003630036
20024300352250000061100002989125300103001020010195628949269553003530035273913274982001020020300203003514511200211091020010100100101270133212995830000100103003630036300363003630036
20024300352250000061100002989125300103001020010195628949269553003530035273913274982001020020300203003514511200211091020010100100101270133112995830000100103003630036300363003630036
20024300352250000061100002989125300103001020010195628949269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
20024300352250000061100002989125300103001020010195628949269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
2002430035225004470061100002989125300103001020010195628949269553003530035273913274982001020020300203003514511200211091020010100100001270133212995830000100103003630036300363003630036
20024300352250000061100002989125300103001020010195628949269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036

Test 4: throughput

Count: 8

Code:

  cmp w0, w1, sxth
  cmp w0, w1, sxth
  cmp w0, w1, sxth
  cmp w0, w1, sxth
  cmp w0, w1, sxth
  cmp w0, w1, sxth
  cmp w0, w1, sxth
  cmp w0, w1, sxth
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802045345740006180000487412516010016010080100344000549503305341053410432982050343360801008020016020053410781180201100991008010010000511022411533921600001005341153411534115341153411
80204534104000618000048741251601001601008010034400054950330534105341043298206034336080100802001602005341078118020110099100801001000234511012411533921600001005341153411534115341153411
80204534104002423380000487412516010016010080100344000598503305341053410432982037343360801008020016020053410781180201100991008010010000511012411533921600001005341153411534115346453411
802045341040006180000487412516010016023080100344000549503305341053410432982060343360801008020016020053410781180201100991008010010010511012411533921600001005341153411534115341153411
8020453410402072680000487412516010016010080100344000549503305341053410432982063343360801008020016020053410781180201100991008010010006511012411533921600001005341153411534115341153411
802045341040036180000487412516010016010080100344000549503305341053410432982063343360801008020016020053410781180201100991008010010043511012411533921600001005341153411534115341153411
802045341040006180000487412516010016010080100344000549503305341053458432982060343360801008020016020053410781180201100991008010010000511012411533921600001005341153411534115341153411
802045341040006180000487412516010016010080100344000549503305341053410432982050343360801008020016020053410781180201100991008010010000511012411533921600001005341153411534115341153411
80204534104000104080000487412516010016010080100344000549503305341053410432982063343360801008020016020053410781180201100991008010010000511012411533921600001005341153411536295341153411
802045341040006180000487412516010016010080100344000549503305341053410432982060343360801008020016020053410781180201100991008010010000511012411533921600001005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03mmu table walk data (08)091e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? int retires (ef)f5f6f7f8fd
800245340240000006318000047946251600101600108001034381300495030005338053380432902562343352800108002016002053380781180021109108001010000502022422533591600000105338153381533815338153381
800245338040000001038000047946251600101600108001034381301495030005338053380432902707343352800108002016002053380781180021109108001010000502022422533591600000105338153381533815338153381
800245338040000006180000479462516001016001080010343813004950300353380533804329025623433528001080020160020533807811800211091080010101200502022422533591600000105338153381533815338153381
80024533804000000618000047946251600101600108001034381301495030005338053380432902707343352800108002016002053380781180021109108001010000502022422533591600000105338153381533815338153381
80024533804000000618000047946251600101600108001034381300495030005338053380432902562343352800108002016002053380781180021109108001010000502022422533591600000105338153381533815338153381
80024533804000000618000047946251600101600108001034381300495030005338053380432902562343352800108002016002053380781180021109108001010000502021722533591600000105338153381533815338153381
800245338039900006180000479462516001016001080010343813004950300053380533804329027073433528001080020160020533807811800211091080010101200502022422533591600000105338153381533815338153381
80024533804000000618000047946251600101600108001034381300495030005338053380432902707343352800108002016002053380781180021109108001010000502022422533591600000105338153381533815338153381
80024533804000000618000047946251600101600108001034381300495030005338053380432902562343352800108002016002053380781180021109108001010000502022422533591600000105338153381533815338153420
80024533804000000618000047946251600101600108001034381300495030005338053380432902707343352800108002016002053380781180021109108001010000502022422533591600000105338153381533815338153381