Firestorm: PACGA measurements

Code:

  pacga x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	57	0	0	0	0	0	0	251	5824	25	1000	1000	1000	178330	1	49	3949	0	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	57	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	0	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	56	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	0	7029	7029	6623	7	6818	1000	1042	2086	7068	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	56	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	0	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	57	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	0	7029	7029	6623	3	6818	1000	1000	2086	7029	870	1	1	1001	1000	0	1	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	56	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	0	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	56	0	0	0	0	12	0	61	5824	25	1000	1000	1000	178330	1	49	3949	0	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	1	4	3880	4	111	1	109	1	1	6826	1006	1000	7148	7109	7107	7109	7108
1004	7109	58	0	1	3	2	144	176	1333	5797	66	1009	1009	1076	178524	1	49	4027	0	7107	7068	6645	7	6846	1056	1083	2250	7107	870	3	1	1001	1000	7	0	0	1773	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	56	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	0	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	56	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	0	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	3	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->2

Code:

  pacga x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	562	0	1	0	0	0	0	88	89	59828	25	10100	10106	10101	1807949	1	49	66949	70029	70029	68549	7	68731	10101	10216	20232	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	0	0	13015	0	1	1	1	719	2	280	0	1	70752	10000	10100	70030	70030	70030	70030	70030
10204	70029	562	0	0	0	0	0	12	0	89	59828	25	10100	10100	10101	1807834	0	49	66949	70029	70029	68549	7	68731	10101	10216	20232	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	24	0	0	0	1	1	1	719	0	16	2	0	69881	10000	10100	70030	70030	70030	70030	70030
10204	70067	563	0	0	0	0	0	0	88	61	59824	25	10100	10100	10100	1807830	0	49	66949	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	0	0	12	0	0	0	0	710	1	79	1	1	69794	10000	10100	70069	70030	70030	70030	70030
10204	70029	562	0	0	0	0	0	0	0	61	59824	25	10100	10100	10100	1807830	0	49	66949	70186	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69859	10000	10100	70030	70030	70030	70030	70030
10204	70029	563	0	0	0	1	0	0	0	89	59824	47	10105	10100	10100	1807830	0	49	66949	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	30	0	3	0	0	0	0	710	1	79	1	1	69794	10000	10100	70030	70030	70069	70030	70030
10204	70029	562	0	0	0	0	0	0	0	89	59824	25	10100	10100	10100	1807830	0	49	66949	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	0	0	9	0	0	0	0	710	1	81	1	1	69794	10000	10100	70030	70030	70030	70069	70030
10204	70029	563	0	0	0	0	0	12	0	61	59824	25	10100	10100	10100	1807830	0	49	66949	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69794	10000	10100	70030	70030	70030	70030	70030
10204	70029	562	0	0	0	0	0	0	0	103	59824	25	10100	10100	10100	1807830	0	49	66949	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	0	0	3	0	0	0	0	710	1	79	1	1	69794	10000	10100	70030	70030	70030	70030	70030
10204	70029	563	0	0	0	0	0	0	0	61	59824	25	10100	10100	10100	1807830	0	49	66949	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	0	0	9	0	0	0	0	710	0	79	1	1	69794	10000	10100	70030	70030	70030	70030	70030
10204	70029	563	0	0	1	2	0	0	0	232	59824	25	10124	10100	10100	1807830	0	49	66949	70029	70067	68480	7	68674	10130	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	2	0	0	0	6	0	0	0	0	710	1	79	1	1	69794	10000	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	544	0	0	0	0	0	0	0	61	59824	25	10010	10010	10010	1807380	0	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	1	640	4	79	4	4	69801	10000	10010	70030	70030	70030	70030	70030
10025	70029	562	0	0	0	0	0	0	0	61	59824	25	10010	10010	10010	1807380	0	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	640	3	79	4	4	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	563	0	0	0	0	0	12	0	61	59824	25	10010	10010	10010	1807380	1	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	640	4	79	4	4	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	543	0	0	0	0	0	0	0	61	59824	25	10010	10010	10010	1807380	0	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	640	3	79	4	4	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	543	0	0	0	0	0	0	0	726	59824	25	10010	10010	10010	1807380	0	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	0	3	0	0	0	640	4	79	3	4	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	543	0	0	0	0	0	0	0	61	59824	25	10010	10010	10010	1807380	1	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	0	3	0	0	0	640	4	79	3	4	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	543	0	0	0	0	0	12	0	61	59824	25	10010	10010	10010	1807380	1	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	640	4	79	4	3	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	543	0	0	0	0	0	0	0	61	59824	25	10010	10010	10010	1807380	0	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	640	4	79	3	4	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	543	0	0	0	0	0	0	0	506	59824	25	10010	10010	10010	1807380	0	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	640	3	79	4	4	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	543	0	0	0	0	0	0	0	103	59824	25	10010	10010	10010	1807380	0	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	1	0	640	4	79	4	3	69801	10000	10010	70030	70030	70030	70030	70030

Test 3: Latency 1->3

Code:

  pacga x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	543	0	726	59824	25	10100	10100	10100	1807830	1	49	66949	0	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	12	0	710	1	79	1	1	69794	10000	10100	70030	70030	70030	70030	70030
10204	70029	543	0	61	59824	25	10100	10100	10100	1807830	1	49	66949	0	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	710	1	79	1	4	69794	10000	10100	70030	70030	70030	70030	70030
10204	70029	543	0	61	59824	25	10100	10100	10100	1807830	1	49	66949	0	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	710	1	79	1	1	69794	10000	10100	70030	70030	70030	70030	70030
10204	70029	543	12	751	59824	25	10100	10100	10100	1807830	1	49	66949	0	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	1	0	0	710	1	79	1	1	69794	10000	10100	70030	70030	70030	70030	70030
10204	70029	543	3	61	59824	25	10100	10100	10100	1807830	1	49	66949	0	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	710	1	79	1	1	69794	10000	10100	70030	70030	70030	70030	70030
10204	70029	542	0	61	59824	25	10100	10100	10100	1807830	1	49	66949	0	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	710	1	79	1	4	69794	10023	10100	70030	70109	70070	70030	70030
10204	70029	543	45	89	59824	25	10100	10100	10100	1807830	1	49	66949	0	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	710	1	79	1	4	69794	10000	10100	70030	70030	70030	70030	70030
10204	70029	542	0	61	59824	25	10100	10100	10100	1807830	1	49	66949	0	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	1	710	1	79	1	1	69794	10000	10100	70030	70030	70030	70030	70030
10204	70029	543	0	61	59824	25	10100	10100	10100	1807830	1	49	66949	0	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	0	0	710	1	79	1	1	69794	10000	10100	70030	70030	70030	70030	70030
10204	70029	543	12	61	59824	25	10100	10100	10100	1807830	1	49	66949	0	70029	70029	68480	3	68674	10100	10200	20200	70029	856	1	1	10201	100	99	100	10100	100	0	3	0	710	1	79	1	1	69794	10000	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	562	0	0	0	0	0	0	0	0	61	59824	25	10010	10010	10010	1807380	1	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	79	0	0	0	640	2	79	2	2	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	563	0	1	0	0	0	0	0	0	589	59815	46	10010	10014	10010	1807477	1	49	66988	0	70029	70068	68502	3	68696	10010	10020	20020	70029	870	2	1	10021	10	9	10	10010	10	2	0	0	83	1945	2	0	656	2	79	2	2	69801	10000	10010	70030	70030	70030	70069	70030
10024	70029	563	0	0	0	0	0	0	0	0	426	59824	25	10010	10010	10040	1807483	0	49	66949	0	70029	70029	68514	3	68696	10010	10020	20106	70029	870	2	1	10021	10	9	10	10010	10	1	0	0	68	0	0	0	640	2	79	2	2	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	562	0	0	0	0	0	0	0	0	61	59824	25	10010	10010	10010	1807380	1	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	141	0	0	0	640	2	79	2	2	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	562	0	0	0	0	0	0	0	0	61	59824	25	10010	10010	10038	1807380	1	49	66949	0	70029	70029	68502	15	68800	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	80	6	0	0	640	2	79	2	2	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	562	0	0	0	0	0	0	0	0	61	59824	25	10010	10010	10010	1807380	1	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	3	12	1858	0	0	654	2	79	2	2	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	562	0	0	0	0	0	0	0	0	61	59824	25	10010	10010	10010	1807380	1	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	87	0	0	0	640	2	79	2	2	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	563	0	0	0	0	0	0	0	0	131	59824	25	10010	10010	10010	1807380	1	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	52	0	0	0	640	2	79	2	2	69801	10000	10010	70030	70030	70030	70030	70069
10024	70029	563	0	0	0	5	2	0	0	0	61	59824	25	10010	10010	10010	1807380	1	49	66949	0	70029	70029	68502	3	68696	10010	10020	20020	70029	870	1	1	10021	10	9	10	10010	10	0	0	0	73	0	0	0	640	2	79	2	2	69801	10000	10010	70030	70030	70030	70030	70030
10024	70029	563	0	0	0	0	0	12	0	0	61	59824	25	10010	10010	10010	1807380	1	49	66949	0	70029	70069	68502	3	68696	10010	10020	20020	70068	870	2	1	10021	10	9	10	10010	10	0	0	0	34	0	0	0	640	2	79	2	2	69801	10000	10010	70030	70030	70030	70030	70030

Test 4: throughput

Count: 8

Code:

  pacga x0, x8, x9
  pacga x1, x8, x9
  pacga x2, x8, x9
  pacga x3, x8, x9
  pacga x4, x8, x9
  pacga x5, x8, x9
  pacga x6, x8, x9
  pacga x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
80204	80052	621	0	0	0	35	25	80100	80100	80100	400500	0	0	49	76955	80035	80035	69966	3	69984	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	3	0	5110	0	0	4	41	1	1	80024	80000	0	0	80100	80036	80036	80036	80036	80036
80204	80035	620	0	0	0	91	25	80100	80100	80100	400500	0	0	49	76955	80035	80035	69966	3	69984	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	0	0	1	25	1	1	80024	80000	0	0	80100	80036	80036	80036	80036	80036
80204	80035	620	0	12	0	84	25	80100	80100	80100	400500	1	0	49	76955	80035	80035	69966	3	69984	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	3	0	5110	0	0	1	25	1	1	80024	80000	0	0	80100	80036	80036	80036	80036	80036
80204	80035	620	0	0	0	100	25	80100	80100	80100	400500	0	0	49	76955	80035	80035	69966	3	69984	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	0	0	1	25	2	1	80024	80000	0	0	80100	80036	80036	80036	80036	80036
80204	80035	620	0	0	88	35	25	80100	80100	80100	400500	0	0	49	76955	80035	80035	69966	3	69984	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	1	0	0	0	5110	0	0	1	25	1	1	80024	80000	0	0	80100	80036	80036	80036	80036	80036
80204	80035	621	0	0	0	63	25	80100	80100	80100	400500	0	0	49	76955	80035	80035	69966	3	69984	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	0	0	1	25	1	1	80024	80000	0	0	80100	80036	80036	80036	80036	80036
80204	80035	621	0	0	0	35	25	80100	80100	80100	400500	0	0	49	76955	80035	80035	69966	3	69984	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	0	0	1	25	1	1	80024	80000	0	0	80100	80036	80036	80036	80036	80036
80204	80035	621	0	6	0	700	34	80100	80100	80100	400500	0	0	49	76955	80035	80035	69966	3	69984	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	0	0	1	25	1	1	80024	80000	0	0	80100	80036	80036	80036	80036	80036
80204	80035	620	0	12	0	784	25	80100	80100	80100	400500	0	0	49	76955	80035	80035	69966	3	69984	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	0	0	1	25	1	1	80024	80000	0	0	80100	80036	80036	80036	80036	80036
80204	80035	620	0	0	0	700	25	80100	80100	80100	400500	0	0	49	76955	80035	80035	69966	3	69984	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	3	0	5110	0	0	1	25	1	1	80024	80000	0	0	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss instruction (0a)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	80050	620	0	0	0	133	25	80010	80010	80010	400050	0	49	76955	0	80035	80035	69988	3	70006	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	303	0	5020	0	0	5	25	0	0	5	5	80026	80000	0	0	80010	80036	80036	80036	80036	80036
80025	80035	620	0	0	3	756	25	80010	80010	80010	400050	0	49	76955	0	80035	80035	69988	3	70006	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	219	0	5020	0	0	6	25	0	0	6	3	80026	80000	0	0	80010	80036	80036	80036	80036	80036
80024	80035	620	0	0	0	755	25	80010	80010	80012	400050	0	49	76955	0	80035	80035	69988	3	70006	80010	80020	160128	80035	164	1	1	80021	10	9	10	80010	10	0	168	0	5020	0	0	5	25	0	0	5	12	80026	80000	0	0	80010	80036	80036	80036	80036	80036
80024	80035	620	0	0	0	130	25	80010	80010	80010	400490	0	49	76955	0	80035	80035	69988	3	70006	80010	80020	160020	80080	164	1	1	80021	10	9	10	80010	10	0	114	0	5020	0	0	5	25	0	0	5	5	80026	80000	0	0	80010	80036	80036	80036	80036	80036
80024	80035	621	0	0	0	91	25	80010	80010	80010	400050	0	49	76955	0	80035	80035	69988	3	70006	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	330	0	5020	0	0	3	25	0	1	5	3	80026	80000	0	0	80010	80036	80036	80036	80036	80036
80024	80035	620	0	0	0	105	25	80010	80010	80010	400050	0	49	76955	0	80035	80035	69988	3	70006	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	249	0	5020	0	0	3	25	0	0	3	6	80026	80000	0	0	80010	80036	80036	80036	80036	80036
80024	80035	620	0	0	66	63	25	80010	80010	80010	400050	0	49	76955	0	80035	80035	69988	3	70006	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	1	258	0	5020	7	0	5	25	0	0	5	5	80026	80000	0	0	80010	80036	80036	80036	80036	80036
80024	80035	620	0	0	42	168	25	80010	80010	80010	400050	0	49	76955	3	80035	80035	69988	3	70006	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	1	435	0	5020	0	0	3	25	0	0	3	5	80026	80000	0	0	80010	80036	80036	80036	80036	80036
80024	80035	620	0	0	0	35	25	80010	80010	80010	400496	0	49	76955	0	80035	80035	69988	3	70006	80010	80020	160020	80080	164	1	1	80021	10	9	10	80010	10	0	126	2	5020	0	0	5	25	0	0	3	5	80026	80000	0	14	80010	80036	80036	80036	80036	80036
80024	80035	620	0	1	12	35	25	80010	80010	80010	400050	0	49	76955	0	80035	80035	69988	3	70006	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	237	0	5020	0	0	3	25	0	0	3	6	80026	80000	0	0	80010	80036	80036	80036	80036	80036

PACGA

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations