Firestorm: CINV (32-bit) measurements

Code:

  cinv w0, w0, hi

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	0	82	917	25	1000	1022	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	2	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  cinv w0, w0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	0	147	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	1	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10298	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	1	0	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	0	747	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	3	0	0	103	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9920	25	10100	10100	10100	647749	1	49	6955	10035	10035	8656	3	8753	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	4	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	156	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	168	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	84	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	6	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	613	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	1	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Chain cycles: 1

Code:

  cinv w0, w1, hi
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	1	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	1	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	2	3	1310	1	28	1	1	19992	20100	10100	20036	20036	20081	20036	20036
20204	20035	150	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	0	0	1310	2	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	1	0	0	0	726	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	1	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	2	0	0	49	3	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	149	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	1	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	1	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	4	0	1310	1	28	1	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	1	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20126	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	823	1291	3	27	5	3	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20079	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	4	27	5	7	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	6	1270	3	27	3	3	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	4	27	4	5	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	4	27	4	4	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	4	27	4	4	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	2	27	4	2	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	4	27	5	4	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	3	27	3	3	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	4	27	4	4	19995	20010	10010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  cinv w0, w8, hi
  cinv w1, w8, hi
  cinv w2, w8, hi
  cinv w3, w8, hi
  cinv w4, w8, hi
  cinv w5, w8, hi
  cinv w6, w8, hi
  cinv w7, w8, hi

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3344

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26764	200	0	1	18	693	27	80118	80118	80124	479916	0	49	23660	26740	26740	16679	6	16689	80124	80232	240296	26740	66	1	1	80201	100	99	100	80100	80100	1	1	1	5118	1	16	1	1	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	201	1	1	18	28	27	80118	80118	80124	479916	0	49	23660	26740	26740	16679	6	16689	80124	80232	240296	26740	66	1	1	80201	100	99	100	80100	80100	1	1	1	5118	1	16	1	1	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	1	1	15	28	27	80118	80118	80124	479916	0	49	23660	26740	26740	16679	6	16689	80124	80232	240296	26740	66	1	1	80201	100	99	100	80100	80100	1	1	1	5180	1	16	1	1	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	1	1	0	28	27	80118	80118	80124	479916	0	49	23660	26740	26740	16679	6	16689	80193	80232	240296	26740	66	1	1	80201	100	99	100	80100	80100	1	1	1	5118	1	16	1	2	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	1	1	0	64	33	80115	80115	80121	479097	0	49	23672	26752	26751	16676	9	16686	80121	80230	240290	26751	66	1	1	80201	100	99	100	80100	80100	2	2	2	5128	2	26	2	2	26748	80015	80100	26752	26753	26752	26752	26752
80204	26752	200	0	0	0	64	33	80115	80115	80121	479097	0	49	23671	26751	26751	16676	9	16686	80121	80230	240290	26751	66	1	1	80201	100	99	100	80100	80100	2	2	2	5128	2	26	2	2	26749	80015	80100	26752	26752	26752	26752	26752
80204	26751	200	0	0	15	64	34	80115	80115	80121	479097	0	49	23671	26752	26751	16676	9	16686	80121	80230	240290	26752	66	1	1	80201	100	99	100	80100	80100	2	2	2	5129	3	26	2	2	26748	80015	80100	26753	26753	26752	26752	26752
80204	26752	201	0	0	27	64	33	80115	80115	80121	479097	0	49	23671	26751	26751	16676	9	16686	80121	80230	240290	26751	66	1	1	80201	100	99	100	80100	80100	2	2	2	5128	2	26	2	2	26748	80015	80100	26752	26753	26752	26752	26752
80204	26751	201	0	0	0	64	33	80115	80115	80121	479097	0	49	23671	26751	26752	16676	9	16686	80121	80230	240290	26751	66	1	1	80201	100	99	100	80100	80100	2	2	2	5129	2	26	2	2	26748	80015	80100	26752	26752	26753	26752	26753
80204	26751	200	0	0	78	64	34	80115	80115	80121	479097	0	49	23672	26751	26752	16676	9	16686	80121	80230	240290	26751	66	1	1	80201	100	99	100	80100	80100	2	2	2	5129	2	26	2	2	26748	80015	80100	26752	26752	26752	26752	26752

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	26724	200	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	0	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	5020	3	18	1	1	26702	80000	0	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	36	25	80010	80010	80010	472059	1	49	23626	0	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	5020	1	18	1	1	26702	80000	0	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	36	25	80010	80010	80010	472059	1	49	23626	0	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	5020	1	18	1	1	26702	80000	0	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	36	25	80010	80010	80010	472059	1	49	23626	0	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	5020	1	18	1	1	26702	80000	0	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	0	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	5020	1	18	1	1	26702	80000	0	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	0	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	5020	1	18	1	1	26702	80000	0	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	36	25	80010	80010	80010	472059	1	49	23626	0	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	5020	1	18	1	1	26702	80000	0	80010	26707	26707	26707	26707	26707
80024	26706	200	1	0	0	0	36	25	80010	80010	80010	472059	1	49	23626	0	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	5020	1	18	1	1	26702	80000	0	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	0	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	5020	1	18	1	1	26702	80000	0	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	0	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	5020	1	18	1	1	26702	80000	0	80010	26707	26707	26707	26707	26707

CINV (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations