Firestorm: STRB (post-index) measurements

Code:

  strb w0, [x6], #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1040	8	0	0	18	5	0	0	24	11	0	1025	19	9	4	0	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1030	0	40	3	18	1000	1	14	6	1	1016	0	59	73	2	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	4	22	0	0	0	0	1025	9	2	15	1	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1044	0	72	0	0	1000	0	0	0	0	1008	0	72	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	6	5	0	0	0	0	0	1025	0	1	0	0	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1038	0	80	5	27	1000	0	28	14	6	1025	0	56	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	6	5	0	0	0	0	0	1025	0	0	1	0	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1046	0	80	2	14	1000	0	14	12	0	1014	1	64	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	9	4	21	0	0	5	0	1025	17	3	3	0	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1028	0	80	7	28	1001	0	14	12	6	1014	0	48	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	4	16	1	0	0	0	1025	11	3	2	0	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1022	0	72	0	14	1000	0	14	6	0	1018	0	56	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	0	3	22	0	0	7	4	1025	11	1	2	1	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1015	0	48	6	15	1008	1	14	8	0	1016	0	64	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	6	4	0	0	0	0	12	1025	0	0	0	1	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1038	0	96	0	18	1000	0	14	12	6	1014	0	69	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	6	4	21	0	0	0	0	1025	0	0	0	1	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1018	0	66	5	14	1000	0	16	12	0	1000	0	61	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	6	4	18	1	0	7	0	1025	11	4	2	0	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1018	0	80	5	14	1000	0	14	8	0	1014	0	48	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 2->2

Code:

  strb w0, [x6], #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	20	22	23	24	29	3a	3c	3e	3f	40	44	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10209	10040	75	1	0	1	0	2211	91	845	3	0	0	544	88	0	252	10025	807	0	130	168	45	25	20100	10100	10000	10100	10000	522127	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10947	8	1355	413	0	677	10255	287	0	932	72	897	10907	24	1355	7	0	710	1	17	1	1	10037	10000	4	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	0	0	2109	107	847	2	0	0	544	81	0	248	10025	804	0	147	157	40	25	20100	10100	10000	10100	10000	522131	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10903	7	1420	393	0	681	10270	276	2	936	78	879	10890	20	1300	7	0	710	1	17	1	1	10037	10000	0	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	0	0	2037	97	861	2	0	0	536	91	0	304	10025	789	0	167	186	40	25	20100	10100	10000	10100	10000	522109	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10941	7	1452	391	0	682	10260	263	0	936	70	876	10933	23	1400	7	0	710	1	17	1	1	10037	10000	5	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	77	1	0	0	0	2208	98	846	2	0	0	552	79	0	264	10025	763	0	150	118	43	25	20100	10100	10000	10100	10000	522157	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10901	7	1497	395	0	660	10263	308	0	932	90	954	10935	25	1191	7	0	710	1	17	1	1	10037	10000	0	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	1	1	0	2229	85	851	2	0	0	520	84	0	232	10025	797	0	153	152	36	25	20100	10100	10000	10100	10000	522077	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10943	7	1557	374	0	704	10257	300	2	864	80	941	10902	28	1362	7	1	710	1	17	1	1	10037	10000	0	0	10000	10100	10041	10041	10093	10078	10041
10204	10040	76	1	0	1	0	2154	94	825	2	0	0	536	86	0	260	10025	808	0	158	136	40	25	20100	10100	10000	10100	10000	522151	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10903	7	1386	393	1	698	10247	279	0	932	78	913	10929	27	1312	7	1	710	1	17	1	1	10037	10000	1	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	1	0	2064	97	820	2	0	0	560	80	0	216	10025	761	0	145	176	49	25	20100	10100	10000	10100	10000	522051	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10917	7	1334	409	0	682	10241	270	0	924	94	935	10910	31	1210	7	0	710	1	17	1	1	10037	10000	5	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	1	0	2226	102	849	2	0	0	496	75	0	228	10025	796	0	180	179	31	25	20100	10100	10000	10100	10000	522147	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10912	8	1522	416	0	644	10257	298	0	914	70	896	10943	22	1281	7	1	710	1	17	1	1	10037	10000	9	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	0	0	2235	89	845	2	0	0	528	81	0	188	10025	792	0	158	187	31	25	20100	10100	10000	10100	10000	522155	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10926	7	1431	412	0	697	10236	308	0	888	78	883	10912	25	1277	7	0	710	1	17	1	1	10037	10000	0	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	0	0	2175	93	814	2	0	0	536	94	0	208	10025	783	0	185	176	39	25	20100	10100	10000	10100	10000	522149	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10888	8	1398	397	0	672	10251	295	0	958	82	979	10917	22	1222	7	1	710	1	17	1	1	10037	10000	0	0	10000	10100	10041	10041	10041	10041	10041

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10029	10040	75	1	1	0	2424	78	823	1	744	78	1	168	10025	774	106	109	37	25	20010	10010	10000	10010	10000	521081	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10902	0	1386	379	0	659	10262	264	0	924	40	820	10914	13	1155	0	0	640	3	16	2	2	10037	10000	3	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	0	0	2208	86	858	1	744	68	1	156	10025	764	88	112	24	25	20010	10010	10000	10010	10000	521073	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10916	7	1317	380	0	673	10255	255	0	902	42	856	10903	23	1256	7	0	640	3	16	2	2	10037	10000	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	1	0	2241	85	793	1	744	72	2	160	10025	758	124	129	32	25	20010	10010	10000	10010	10000	521121	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10918	0	1347	348	0	702	10263	295	0	906	50	869	10908	16	1246	0	0	640	2	16	3	3	10037	10000	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	0	0	2343	87	776	1	744	44	1	120	10025	764	137	124	32	25	20010	10010	10000	10010	10000	521121	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10897	8	1321	378	0	665	10250	287	1	874	40	899	10914	19	1173	7	1	640	2	16	2	2	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	0	0	2142	94	807	1	736	75	0	152	10025	784	75	145	27	25	20010	10010	10000	10010	10000	521049	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10900	7	1496	382	0	644	10250	280	1	928	46	867	10948	18	1170	7	0	640	3	16	2	2	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	0	0	0	2328	76	806	1	752	68	0	100	10025	807	123	127	20	25	20010	10010	10000	10010	10000	521049	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10922	7	1429	410	0	674	10268	284	0	894	36	878	10896	22	1197	7	0	640	3	16	2	2	10037	10000	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	0	0	2331	95	821	1	720	77	1	92	10025	764	137	124	45	25	20010	10010	10000	10010	10000	521129	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10916	0	1363	373	0	653	10262	261	0	908	36	804	10906	13	1183	0	0	640	3	16	3	3	10037	10000	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	0	1	2292	102	797	1	696	68	1	116	10025	761	112	104	37	25	20010	10010	10000	10010	10000	521073	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10926	0	1426	384	0	660	10258	253	0	894	32	829	10895	19	1249	0	0	640	4	16	2	2	10037	10000	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	0	0	0	2235	80	802	1	760	72	1	116	10025	788	141	102	36	25	20010	10010	10000	10010	10000	521089	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10875	7	1353	396	0	621	10280	278	0	860	46	795	10884	21	1164	7	2	640	3	16	3	2	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	0	1	2211	88	780	1	728	73	2	116	10025	813	124	84	39	25	20010	10010	10000	10010	10000	521129	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10906	0	1371	385	0	670	10265	269	0	890	40	786	10933	19	1089	0	0	640	2	16	3	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041

Test 3: throughput

Count: 8

Code:

  strb w0, [x6], #8
  strb w0, [x7], #8
  strb w0, [x8], #8
  strb w0, [x9], #8
  strb w0, [x10], #8
  strb w0, [x11], #8
  strb w0, [x12], #8
  strb w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80209	40476	303	1	1	1	2175	396	850	1	736	110	140	40418	815	1969	1981	91	25	160854	80806	80005	80100	80000	407803	1856876	0	287	49	37365	40450	40522	30327	3	30496	160100	200	80000	200	160000	40506	93	1	1	80201	100	99	100	80000	100	80000	100	80970	20	3963	487	14	917	80280	274	0	938	42	1184	81164	243	4144	27	0	5110	1	17	1	1	40485	80627	80000	80100	40435	40382	40463	40444	40482
80204	40355	302	2	0	0	1857	372	801	1	712	103	128	40419	795	2008	1946	83	25	163880	84359	80000	80100	80000	423444	1856684	1	1172	49	37304	40491	40442	30291	3	30391	160100	200	80000	200	160000	40432	82	1	1	80201	100	99	100	80000	100	80000	100	80951	27	5065	499	12	899	80281	281	0	917	40	1153	81115	274	5237	28	2	5110	1	17	1	1	40420	80939	80000	80100	40436	40464	40409	40402	40424
80204	40432	302	1	1	0	2085	373	816	1	752	114	100	40370	809	2172	1844	100	25	163788	81591	80000	80100	80000	407887	1855772	0	154	49	37357	40388	40362	30382	3	30429	160100	200	80000	200	160000	40401	85	1	1	80201	100	99	100	80000	100	80000	100	80937	14	4337	490	10	835	80248	285	0	917	40	1231	81090	278	4638	14	0	5110	1	16	1	1	40433	80400	80000	80100	40489	40415	40425	40386	40440
80204	40462	303	1	0	1	1974	367	800	1	720	97	132	40398	789	2118	2114	107	25	165327	80889	80000	80100	80000	404793	1861243	0	432	49	37407	40479	40486	30397	3	30457	160100	200	80000	200	160000	40442	91	1	1	80201	100	99	100	80000	100	80000	100	80919	15	4385	458	12	907	80273	281	2	897	26	1366	81166	251	4364	14	0	5110	1	17	1	1	40390	80325	80000	80100	40402	40385	40428	40454	40404
80204	40401	302	1	0	1	2064	365	820	1	712	92	124	40341	789	2106	1983	99	25	160698	83631	80045	80100	80000	409029	1856468	0	381	49	37343	40491	40401	30448	3	30361	160100	200	80000	200	160000	40381	83	1	1	80201	100	99	100	80000	100	80000	100	80913	14	4302	528	6	910	80266	285	0	871	30	1164	81145	234	4079	14	1	5110	1	16	1	1	40404	81893	80000	80100	40350	40577	40420	40371	40419
80204	40391	303	1	0	0	2826	369	816	1	680	105	112	40401	775	1972	2048	101	25	160802	80747	80000	80100	80000	402332	1854596	0	1804	49	37306	40411	40434	30298	3	30451	160100	200	80000	200	160000	40437	85	1	1	80201	100	99	100	80000	100	80000	100	80919	14	4666	525	6	858	80274	268	0	935	42	1227	81181	245	4324	14	0	5110	1	17	1	1	40458	83381	80000	80100	40426	40509	40367	40454	40422
80204	40401	302	1	0	0	1989	340	797	1	752	108	108	40443	816	1863	2060	95	25	160710	85538	80055	80100	80000	414047	1856396	0	283	49	37454	40475	40409	30318	3	30375	160100	200	80000	200	160000	40481	91	1	1	80201	100	99	100	80000	100	80000	100	80902	15	4032	547	4	926	80245	278	0	922	44	1177	81156	264	4160	14	0	5110	1	17	1	1	40402	80578	80000	80100	40440	40483	40404	40427	40396
80204	40469	304	1	0	1	2424	372	790	1	728	103	160	40413	819	2077	1821	104	69	163248	80491	80120	80444	80000	424185	1861784	1	208	49	37357	40414	40419	30362	3	30380	160100	200	80000	200	160000	40426	92	1	1	80201	100	99	100	80000	100	80000	100	81027	14	4371	531	67	870	80279	266	2	877	42	1985	81190	275	4143	14	0	5110	1	17	1	1	40615	81044	80000	80100	40649	40412	40747	40350	40484
80204	40369	303	1	0	0	2178	363	846	1	720	112	100	40429	789	1956	2053	107	25	162707	83459	80050	80100	80000	401362	1856588	0	356	49	37349	40388	40452	30279	3	30371	160100	200	80000	200	160000	40351	85	1	1	80201	100	99	100	80000	100	80000	100	80913	14	4515	526	7	932	80259	274	0	863	28	1174	81163	256	4159	14	0	5110	1	16	1	1	40425	80893	80000	80100	40425	40465	40456	40405	40524
80204	40402	303	1	1	0	2028	363	796	1	720	113	132	40458	824	1935	2028	97	25	164413	80795	80001	80100	80000	401312	1855340	0	287	49	37396	40393	40456	30369	3	30371	160100	200	80000	200	160000	40389	83	1	1	80201	100	99	100	80000	100	80000	100	80923	14	4534	499	9	898	80273	267	0	911	42	1189	81134	264	4406	14	1	5110	1	17	1	1	40485	80683	80000	80100	40440	40433	40387	40378	40415

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80029	40470	303	2	1	2	1	2124	367	806	1	712	107	148	40329	796	1899	1974	100	25	160524	86082	80000	80010	80000	404028	1858672	1	170	49	37373	40482	40412	30539	3	30480	160010	20	80000	20	160000	40400	75	1	1	80021	10	9	10	80000	10	80000	10	80885	15	4566	500	12	883	80257	286	0	932	36	1220	81134	225	4350	0	0	5020	4	16	4	4	40409	85416	80000	80010	40383	40544	40374	40431	40479
80024	40402	303	0	0	0	0	2088	409	804	1	688	110	112	40389	757	2022	2049	101	25	160541	80321	80000	80010	80000	400759	1855696	1	2751	49	37336	40454	40397	30368	3	30522	160010	20	80000	20	160000	40606	75	1	1	80021	10	9	10	80000	10	80000	10	80914	0	4322	502	12	908	80265	279	0	924	32	1282	81165	255	4798	0	0	5020	3	16	4	4	40456	80500	80000	80010	40445	40502	40339	40445	40463
80024	40469	304	0	0	0	0	2130	406	804	1	744	115	104	40370	767	1986	2142	83	25	161184	82438	80000	80010	80000	401957	1857688	0	148	49	37292	40439	40402	30338	3	30522	160010	20	80000	20	160000	40419	75	1	1	80021	10	9	10	80000	10	80000	10	80868	0	4859	474	10	888	80256	282	0	914	52	1225	81167	254	4345	0	0	5022	3	16	4	3	40434	80276	80000	80010	40451	40437	40396	40384	40464
80024	40390	303	0	0	0	0	2070	338	776	1	744	112	140	40391	807	2007	2169	109	25	160575	80313	80000	80010	80000	404093	1858456	1	184	49	37303	40397	40447	30352	3	30377	160010	20	80000	20	160000	40329	75	1	1	80021	10	9	10	80000	10	80000	10	80888	0	4479	515	9	899	80248	276	0	910	40	1224	81103	267	4266	0	0	5020	3	17	4	3	40424	80814	80000	80010	40468	40436	40497	40533	40474
80024	40385	302	0	0	0	0	2175	392	769	1	704	107	140	40489	793	1960	2014	75	25	160642	87878	80000	80010	80000	422759	1855604	1	2300	49	37488	40407	40565	30350	3	30441	160010	20	80600	20	160000	40397	85	1	1	80021	10	9	10	80000	10	80000	10	80935	14	4738	519	2	857	80276	318	0	895	38	1244	81157	283	4126	14	1	5020	3	16	4	4	40416	84992	80000	80010	40372	40468	40465	40458	40413
80024	40421	303	1	1	0	0	2193	383	822	1	736	110	140	40364	790	2156	1967	102	25	160490	81758	80000	80010	80000	402055	1858432	1	168	49	37397	40381	40409	30386	3	30385	160010	20	80000	20	160000	40396	75	1	1	80021	10	9	10	80000	10	80000	10	80904	14	4407	503	19	882	80272	289	0	892	42	1247	81141	283	4393	14	2	5020	4	17	4	3	40393	80109	80000	80010	40376	40492	40522	40330	40584
80024	40419	303	1	0	0	0	2157	344	827	1	776	114	212	40431	802	2132	1910	81	25	160481	80315	80000	80010	80000	401977	1861517	1	155	49	37302	40460	40584	30429	3	30473	160010	20	80000	20	160000	40511	90	1	1	80021	10	9	10	80000	10	80000	10	80968	14	4751	501	3	906	80261	295	0	926	34	1335	81085	247	4979	14	0	5020	4	16	4	4	40403	86010	80000	80010	40533	40405	40496	40434	40353
80024	40447	303	1	0	0	0	2076	399	823	1	728	115	248	40433	767	1960	1967	78	25	160458	80254	80086	80010	80000	400756	1857736	1	199	49	37387	40534	40430	30410	3	30351	160010	20	80000	20	160000	40398	75	1	1	80021	10	9	10	80000	10	80000	10	80889	0	4502	477	11	906	80272	291	0	911	42	1253	81162	261	4380	14	0	5020	3	17	4	3	40374	80404	80000	80010	40464	40394	40472	40499	40476
80024	40406	302	1	0	0	1	2091	344	821	1	720	114	136	40428	811	2026	2122	102	25	160469	80293	80047	80010	80000	410306	1855460	1	170	49	37299	40521	40445	30441	3	30414	160010	20	80000	20	160000	40361	85	1	1	80021	10	9	10	80000	10	80000	10	80925	0	4640	527	8	869	80253	282	0	893	30	1300	81109	250	4812	0	0	5020	3	16	4	4	40468	80527	80000	80010	40468	40458	40500	40478	40381
80024	40402	303	1	0	0	0	2433	373	845	1	704	117	88	40417	796	2051	2097	86	25	160465	86106	80000	80010	80000	400419	1856181	1	134	49	37328	40403	40490	30338	3	30394	160010	20	80000	20	160000	40492	92	1	1	80021	10	9	10	80000	10	80000	10	80913	14	4452	501	5	914	80266	280	0	931	34	1348	81161	264	4258	14	1	5020	4	18	4	4	40477	80425	80000	80010	40445	40443	40487	40439	40421

STRB (post-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations