Firestorm: PRFM (register, PLIL1STRM) measurements

Code:

  prfm plil1strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1565	12	34	16	33	2442	1604	898	25	1000	1000	1000	69861	0	1580	1591	1294	3	1442	1000	1000	1000	1579	1601	1	1	1001	232	2262	2264	3265	0	2443	2260	1000	73	1	16	1	1	1502	1000	1621	1595	1610	1594	1604
1004	1619	11	34	18	32	2444	1579	884	25	1000	1000	1000	69854	0	1608	1611	1314	3	1448	1000	1000	1000	1583	1602	1	1	1001	242	2263	2281	3304	0	2461	2284	1000	73	1	16	1	1	1492	1000	1591	1602	1656	1618	1596
1004	1603	12	33	17	32	2441	1560	887	25	1000	1000	1000	69590	0	1572	1578	1304	3	1434	1000	1000	1000	1608	1593	1	1	1001	256	2279	2306	3299	0	2461	2262	1000	73	1	16	1	1	1506	1000	1623	1570	1569	1588	1595
1004	1575	12	34	17	34	2442	1558	905	25	1000	1000	1000	68400	1	1575	1611	1287	3	1431	1000	1000	1000	1595	1558	1	1	1001	221	2276	2273	3255	0	2455	2265	1000	73	1	16	1	1	1491	1000	1545	1579	1600	1565	1615
1004	1571	12	33	17	33	2447	1576	869	25	1000	1000	1000	69445	0	1570	1606	1285	3	1455	1000	1000	1000	1560	1601	1	1	1001	250	2265	2310	3250	0	2459	2249	1000	73	1	16	1	1	1506	1000	1598	1602	1624	1579	1624
1004	1623	12	32	17	32	2461	1593	877	25	1000	1000	1000	70077	0	1597	1615	1304	3	1480	1000	1000	1000	1621	1598	1	1	1001	250	2258	2258	3292	0	2448	2253	1000	73	1	16	1	1	1510	1000	1592	1592	1566	1618	1621
1004	1621	11	34	16	33	2489	1566	878	25	1000	1000	1000	69418	0	1565	1577	1326	3	1411	1000	1000	1000	1566	1566	1	1	1001	247	2279	2264	3274	1	2467	2299	1000	73	1	16	1	1	1483	1000	1611	1585	1609	1566	1565
1004	1627	12	34	17	33	2440	1591	852	25	1000	1000	1000	70432	0	1565	1629	1286	3	1433	1000	1000	1000	1575	1555	1	1	1001	236	2281	2280	3279	0	2442	2267	1000	73	1	16	1	1	1491	1000	1616	1616	1601	1596	1580
1004	1602	12	33	18	34	2441	1578	880	25	1000	1000	1000	68933	0	1575	1600	1310	3	1484	1000	1000	1000	1569	1599	1	1	1001	240	2291	2263	3282	0	2443	2309	1000	73	1	16	1	1	1490	1000	1578	1574	1580	1587	1576
1004	1578	12	34	17	32	2488	1579	860	25	1000	1000	1000	70227	0	1595	1570	1268	3	1451	1000	1000	1000	1605	1573	1	1	1001	232	2262	2266	3270	0	2471	2282	1000	73	1	16	1	1	1477	1000	1600	1618	1590	1616	1566

Test 2: throughput

Code:

  prfm plil1strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5787

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15824	117	1	343	180	1	344	24486	1	15685	9826	25	20220	10224	10000	10100	10000	132151	740200	0	31	49	12731	15692	15726	13118	3	13139	20100	10200	10000	10200	10000	15738	159	1	1	20201	100	99	2469	100	10100	100	22849	22721	32893	0	0	24385	22708	10000	1312	2	16	2	3	15714	10096	10000	10100	15757	15828	15745	15766	15930
20204	15779	118	1	350	181	1	342	24424	1	15712	9727	25	20214	10220	10000	10100	10000	133359	733484	1	33	49	12744	15718	15888	12979	3	13185	20100	10200	10000	10200	10000	15722	154	1	1	20201	100	99	2548	100	10100	100	22822	22809	32858	0	0	24468	22761	10000	1312	2	16	3	3	15578	10087	10000	10100	15784	15889	15858	15767	15606
20204	15642	117	1	340	178	1	340	24534	1	15775	9676	25	20244	10229	10000	10100	10000	132797	736417	0	34	49	12724	15784	15740	13060	3	13291	20100	10200	10000	10200	10000	15785	149	1	1	20201	100	99	2511	100	10100	100	22945	22750	32775	0	0	24567	22844	10000	1312	3	16	3	3	15691	10096	10000	10100	15727	15687	15758	15714	15741
20204	15654	119	1	342	179	1	337	24586	1	15774	9645	25	20211	10226	10000	10100	10000	132261	733753	0	35	49	12742	15844	15749	13017	3	13281	20100	10200	10000	10200	10000	15758	156	1	1	20201	100	99	2482	100	10100	100	22664	22717	32807	0	0	24345	22753	10000	1312	3	16	3	2	15575	10120	10000	10100	15707	15764	15805	15846	15936
20204	15868	118	1	339	177	1	343	24409	1	15719	9832	25	20226	10199	10000	10100	10000	132793	740408	0	27	49	12618	15755	15765	13019	3	13150	20100	10200	10000	10200	10000	15756	150	1	1	20201	100	99	2467	100	10100	100	22892	22826	32942	1	0	24341	22784	10000	1312	3	17	2	3	15495	10111	10000	10100	15808	15729	15804	15691	15939
20204	15651	118	1	342	176	1	337	24589	1	15633	9836	25	20214	10193	10000	10100	10000	132860	730634	0	31	49	12641	15724	15622	13079	3	13207	20100	10200	10000	10200	10000	15752	153	1	1	20201	100	99	2588	100	10100	100	22938	22896	32801	0	0	24483	22548	10000	1312	3	16	3	2	15643	10099	10000	10100	15806	15848	15718	15814	15818
20204	15753	118	1	351	181	1	346	24503	1	15766	9704	25	20179	10193	10000	10100	10000	133771	737951	1	27	49	12717	15699	15761	13063	3	13241	20100	10200	10000	10200	10000	15752	148	1	1	20201	100	99	2476	100	10100	100	22761	22853	32894	2	0	24470	22877	10000	1312	2	16	3	2	15600	10099	10000	10100	15783	15800	15801	15830	15884
20204	15717	119	1	343	174	1	341	24581	1	15752	9829	25	20205	10214	10000	10100	10000	132781	737957	1	40	49	12725	15735	15835	13025	3	13090	20100	10200	10000	10200	10000	15681	155	1	1	20201	100	99	2432	100	10100	100	22845	22784	32677	0	0	24806	22787	10000	1312	3	16	3	3	15651	10093	10000	10100	15724	15865	15846	15713	15775
20204	15782	118	1	340	187	1	338	24530	1	15717	9932	25	20205	10208	10000	10100	10000	132655	741968	0	27	49	12734	15816	15739	13023	3	13281	20100	10200	10000	10200	10000	15637	143	1	1	20201	100	99	2418	100	10100	100	22843	22758	32803	0	0	24605	22824	10000	1312	3	16	3	2	15591	10114	10000	10100	15760	15640	15653	15698	15714
20204	16057	117	1	350	178	1	343	24684	1	15798	9685	25	20199	10214	10000	10100	10000	131422	741294	0	49	49	12745	15890	15767	12979	3	13242	20100	10200	10000	10200	10000	15687	143	1	1	20201	100	99	2385	100	10100	100	22765	22794	32808	0	0	24484	22739	10000	1312	3	17	2	3	15828	10147	10000	10100	15676	15875	15837	15915	15774

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5797

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	16017	119	337	180	342	0	24240	0	15933	9753	25	20163	10142	10000	10010	10000	132848	744856	0	52	49	12669	15764	15713	13069	3	13230	20010	10020	10000	10020	10000	15656	143	2	1	20021	10	9	2462	10	10010	10	22700	22626	32761	1	3	24267	22685	10000	1270	1	15	1	1	15574	10126	10000	10010	15764	15791	15921	15799	15715
20024	15806	119	341	177	339	0	24367	0	15691	9754	25	20148	10154	10000	10010	10000	133864	735480	1	43	49	12583	15703	15691	13048	3	13310	20010	10020	10000	10020	10000	15706	142	1	1	20021	10	9	2534	10	10010	10	22745	22666	32928	1	0	24427	22813	10000	1270	1	16	1	1	15657	10150	10000	10010	15760	15932	15890	15535	15789
20024	15822	120	342	180	342	0	24517	108	15723	9804	25	20163	10118	10061	10010	10000	134833	748162	0	41	49	12695	15744	15744	13136	3	13192	20010	10020	10000	10020	10000	15770	144	1	1	20021	10	9	2356	10	10010	10	22609	22706	32738	0	0	24461	22767	10000	1270	1	16	1	1	15639	10132	10000	10010	15737	15914	15688	15626	15726
20024	15834	119	338	184	340	0	24535	0	15750	9780	25	20151	10130	10000	10010	10000	135484	738892	0	44	49	12801	15862	15817	13095	3	13398	20010	10020	10000	10020	10000	15749	144	1	1	20021	10	9	2504	10	10010	10	22874	22826	32633	0	0	24387	22753	10000	1270	1	16	1	1	15609	10129	10000	10010	15767	15697	15920	15842	15670
20024	15753	119	339	182	335	0	24375	0	15822	9827	25	20160	10139	10000	10010	10000	133139	743013	1	39	49	12669	15834	15883	13142	3	13287	20010	10020	10000	10020	10000	15658	142	1	1	20021	10	9	2440	10	10010	10	22705	22563	32627	0	0	24595	22659	10000	1270	1	16	2	1	15650	10120	10000	10010	15782	15803	15910	15819	15728
20024	15816	118	344	180	348	0	24511	0	15831	9817	25	20133	10127	10000	10010	10000	133638	739303	0	48	49	12645	15723	15724	13041	3	13280	20010	10020	10000	10020	10000	15760	143	1	1	20021	10	9	2384	10	10010	10	22833	22880	32821	1	0	24439	22718	10000	1270	1	16	1	1	15611	10132	10000	10010	15758	15849	15830	15807	15935
20024	15776	120	346	183	332	0	24426	0	15843	9930	25	20181	10154	10000	10010	10000	135102	744950	0	48	49	12673	15757	15717	13053	3	13188	20010	10020	10000	10020	10000	15821	143	1	1	20021	10	9	2637	10	10010	10	22750	22967	32798	0	0	24661	22639	10000	1270	1	16	1	1	15604	10129	10000	10010	15790	15798	15856	15803	15792
20024	15726	117	340	180	336	0	24523	0	15778	9771	25	20142	10166	10000	10010	10000	132675	734850	0	43	49	12752	15705	15734	13075	3	13246	20010	10020	10000	10020	10000	15924	143	1	1	20021	10	9	2662	10	10010	10	22851	22709	32838	0	0	24400	22703	10000	1270	1	16	1	1	15606	10171	10000	10010	15792	15766	15881	15812	15960
20024	15871	119	340	177	344	0	24539	0	15826	9726	25	20145	10166	10000	10010	10000	135668	738159	0	40	49	12799	15822	15782	13094	3	13171	20010	10020	10000	10020	10000	15598	145	1	1	20021	10	9	2404	10	10010	10	22681	22580	32704	0	0	24567	22710	10000	1270	2	16	1	1	15631	10141	10000	10010	15678	15722	15553	15816	15763
20024	15788	120	348	183	341	0	24421	0	15769	9714	25	20166	10151	10000	10010	10000	134025	737149	0	48	49	12717	15694	15759	13044	3	13359	20010	10020	10000	10020	10000	15652	143	1	1	20021	10	9	2550	10	10010	10	22638	22791	32566	0	0	24435	22732	10000	1270	1	16	1	1	15756	10141	10000	10010	15887	15697	15725	15822	15971

Test 3: throughput

Code:

  prfm plil1strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.3533

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	13581	101	379	378	379	25463	13516	7887	25	10100	100	10000	100	10000	500	633502	0	49	10475	13530	13553	12088	7	12284	10100	200	10024	200	10016	13487	10667	1	1	10201	100	99	36	100	100	100	23762	23703	33738	0	0	25479	23758	10000	1	1	1	717	1	16	13430	10000	100	13593	13506	13598	13530	13483
10204	13505	102	381	378	378	25546	13485	7852	25	10100	100	10000	100	10007	500	632531	1	49	10472	13499	13508	12066	7	12252	10100	200	10016	200	10016	13551	10694	1	1	10201	100	99	32	100	100	100	23702	23688	33675	2	2	25456	23718	10000	1	1	1	717	0	16	13475	10000	100	13566	13492	13457	13512	13533
10204	13575	102	378	378	379	25496	13515	7867	25	10146	100	10000	100	10000	500	628335	1	49	10473	13552	13456	12082	6	12246	10100	200	10008	200	10008	13509	10682	1	1	10201	100	99	66	100	100	100	23714	23777	33600	0	0	25483	23714	10000	1	1	1	719	0	16	13469	10000	100	13542	13500	13572	13508	13484
10204	13534	102	377	376	378	25642	13447	7795	25	10100	100	10000	100	10004	500	634395	0	49	10470	13519	13532	12104	6	12251	10100	200	10016	200	10008	13541	10720	1	1	10201	100	99	60	100	100	100	23705	23715	33713	0	0	25474	23811	10000	1	1	1	718	0	16	13445	10000	100	13504	13487	13456	13530	13525
10204	13530	101	380	377	380	25582	13528	7813	25	10100	100	10000	100	10000	500	629139	1	49	10479	13524	13487	12164	6	12264	10104	200	10008	200	10008	13530	10679	1	1	10201	100	99	37	100	100	100	23711	23736	33705	0	0	25441	23770	10000	1	1	1	717	0	16	13442	10000	100	13545	13564	13595	13489	13515
10204	13502	101	380	379	380	25516	13538	7809	25	10100	100	10000	100	10000	500	629360	0	49	10421	13517	13531	12087	6	12254	10107	200	10016	200	10008	13527	10707	1	1	10201	100	99	56	100	100	100	23847	23715	33696	0	0	25586	23791	10000	1	1	1	717	0	16	13492	10000	100	13676	13538	13542	13599	13528
10204	13505	101	380	376	380	25469	13520	7814	25	10100	100	10000	100	10000	500	630876	1	49	10413	13503	13534	12091	6	12245	10100	200	10016	200	10008	13545	10744	1	1	10201	100	99	51	100	100	100	23719	23683	33714	0	0	25532	23639	10000	1	1	1	718	0	16	13440	10000	100	13550	13539	13473	13581	13531
10204	13557	101	380	379	379	25441	13453	7807	25	10100	100	10000	100	10000	500	632360	1	49	10445	13570	13548	12167	7	12208	10100	200	10016	200	10016	13541	10683	1	1	10201	100	99	32	100	100	100	23686	23687	33761	0	0	25520	23630	10000	1	1	1	717	0	16	13439	10000	100	13549	13521	13470	13560	13537
10204	13522	101	379	379	379	25546	13509	7794	25	10100	100	10000	100	10008	500	630627	0	49	10399	13522	13549	12148	6	12214	10100	200	10024	200	10008	13571	10666	1	1	10201	100	99	47	100	100	100	23733	23764	33727	9	0	25595	23676	10000	1	1	1	718	0	16	13438	10000	100	13485	13518	13548	13525	13620
10204	13586	101	378	378	379	25569	13486	7769	25	10100	100	10000	100	10000	500	631330	1	49	10442	13504	13533	12096	6	12245	10100	200	10016	200	10008	13544	10706	1	1	10201	100	99	52	100	100	100	23647	23798	33735	0	0	25580	23811	10000	1	1	1	719	0	16	13454	10000	100	13552	13542	13564	13521	13563

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5488

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15546	116	294	147	287	23900	0	15489	9520	25	10010	10	10000	10	10000	50	724933	1	49	12422	15511	15412	14030	3	14339	10010	20	10000	20	10000	15431	15440	1	1	10021	10	9	2606	10	10	10	22260	22097	32248	0	23828	22188	10000	0	0	640	2	16	2	2	15323	10000	10	15446	15501	15565	15404	15524
10024	15534	116	290	147	293	23958	0	15518	9549	25	10010	10	10000	10	10000	50	725048	1	49	12435	15388	15571	14058	3	14213	10010	20	10000	20	10000	15501	15431	1	1	10021	10	9	2502	10	10	10	22222	22234	32138	0	23906	22188	10000	0	0	640	2	16	2	2	15371	10000	10	15481	15504	15426	15553	15468
10024	15484	116	290	145	292	23937	0	15446	9553	25	10010	10	10000	10	10000	50	729346	1	49	12425	15437	15504	14059	3	14244	10010	20	10000	20	10000	15412	15411	1	1	10021	10	9	2525	10	10	10	22111	22194	32253	1	23952	22175	10000	0	0	640	2	16	2	2	15384	10000	10	15481	15467	15491	15498	15440
10024	15381	115	290	147	292	23925	0	15491	9510	25	10010	10	10000	10	10000	50	727722	1	49	12432	15398	15470	14072	3	14238	10010	20	10000	20	10000	15481	15433	1	1	10021	10	9	2550	10	10	10	22222	22192	32239	0	23920	22165	10000	0	0	640	2	16	2	2	15507	10000	10	15497	15398	15428	15479	15458
10024	15545	116	291	144	291	23958	0	15478	9587	25	10010	10	10000	10	10000	50	728128	1	49	12335	15510	15556	14122	3	14213	10010	20	10000	20	10000	15419	15402	1	1	10021	10	9	2571	10	10	10	22174	22136	32175	0	23884	22217	10000	0	0	640	2	16	2	2	15336	10000	10	15414	15484	15469	15485	15479
10024	15539	117	290	145	295	23893	0	15366	9521	25	10010	10	10000	10	10000	50	724984	1	49	12393	15416	15409	14061	3	14236	10010	20	10000	20	10000	15463	15484	1	1	10021	10	9	2565	10	10	10	22132	22174	32170	0	23864	22209	10000	0	0	640	2	16	2	2	15340	10000	10	15528	15454	15526	15462	15500
10024	15422	115	290	146	290	23881	0	15434	9561	25	10010	10	10000	10	10000	50	724324	1	49	12411	15478	15467	13946	3	14167	10010	20	10000	20	10000	15456	15408	1	1	10021	10	9	2618	10	10	10	22219	22182	32174	0	23890	22141	10000	0	0	640	2	16	2	2	15394	10000	10	15473	15462	15420	15474	15453
10024	15488	116	294	147	291	23957	0	15455	9606	25	10010	10	10000	10	10000	50	723833	1	49	12395	15545	15449	14005	3	14218	10010	20	10000	20	10000	15497	15468	1	1	10021	10	9	2471	10	10	10	22141	22238	32181	0	23904	22231	10000	0	0	640	2	16	2	2	15333	10000	10	15430	15475	15515	15482	15446
10024	15445	116	294	145	291	23837	0	15427	9547	25	10010	10	10000	10	10000	50	726419	1	49	12400	15456	15507	13982	3	14161	10010	20	10000	20	10000	15510	15437	1	1	10021	10	9	2476	10	10	10	22201	22227	32191	0	23968	22164	10000	0	0	640	2	16	2	2	15384	10000	10	15473	15504	15514	15565	15505
10024	15458	116	292	146	294	23862	0	15527	9555	25	10010	10	10000	10	10000	50	726309	1	49	12391	15440	15464	14033	3	14204	10010	20	10000	20	10000	15450	15405	1	1	10021	10	9	2518	10	10	10	22251	22194	32157	0	23862	22191	10000	0	0	640	2	16	2	2	15379	10000	10	15492	15479	15454	15448	15465

PRFM (register, PLIL1STRM)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations