Firestorm: LDR (literal, 32-bit) measurements

Code:

  ldr w0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	24	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	379	3	0	0	0	1	16	10	1	0	0	0	365	0	0	0	0	4	25	1000	1000	1000	14358	1	388	381	203	3	244	1000	1000	380	62	1	1	1001	1000	1000	1003	0	0	32	1010	7	0	12	4	18	1028	12	1	10	16	73	1	16	1	1	376	4	3	2	1000	388	375	382	381	382
1004	379	3	0	0	0	0	0	0	0	0	0	0	365	0	0	0	0	4	25	1000	1000	1000	14411	1	374	374	197	3	239	1000	1000	374	62	1	1	1001	1000	1000	1000	0	0	0	1010	13	0	0	0	10	1012	6	1	10	16	73	1	16	1	1	377	6	3	2	1000	392	382	382	381	387
1004	387	3	0	0	0	0	16	0	1	0	0	0	366	0	0	0	0	9	25	1000	1000	1000	14769	1	380	380	203	3	238	1000	1000	381	56	1	1	1001	1000	1000	1000	0	0	16	1022	0	0	0	0	10	1010	0	0	10	32	73	1	16	1	1	383	7	4	2	1000	382	382	381	388	388
1004	380	3	0	0	0	0	16	0	0	0	0	0	365	0	0	0	0	3	25	1000	1000	1000	14852	1	374	374	203	3	232	1000	1000	380	62	1	1	1001	1000	1000	1000	0	0	32	1020	0	0	0	0	10	1032	6	1	11	16	73	1	16	1	1	371	0	3	2	1000	382	382	382	381	381
1004	387	3	0	0	0	0	16	5	0	0	0	0	364	0	0	0	0	3	25	1000	1000	1000	14322	1	380	379	214	3	237	1000	1000	380	62	1	1	1001	1000	1000	1000	12	0	32	1010	0	0	0	0	10	1035	6	1	40	32	73	1	16	1	1	377	4	3	2	1000	381	388	382	381	382
1004	387	3	0	0	0	0	109	0	1	0	0	0	366	0	0	0	0	4	25	1000	1000	1000	14617	1	381	380	203	3	238	1000	1000	387	62	1	1	1001	1000	1000	1010	0	0	32	1010	0	1	9	0	10	1012	6	0	10	16	73	1	16	1	1	377	6	3	2	1000	380	382	382	381	380
1004	380	3	0	0	0	0	32	0	0	0	0	4	365	0	0	0	0	4	25	1000	1000	1000	14850	1	379	380	203	3	245	1000	1000	381	62	1	1	1001	1000	1000	1007	0	0	32	1010	0	0	0	0	10	1025	12	1	20	16	73	1	16	1	1	377	6	3	2	1000	381	388	382	381	375
1004	381	3	0	0	0	0	0	7	0	0	0	0	365	0	0	0	0	0	25	1000	1000	1000	14358	1	380	381	203	3	239	1000	1000	374	62	1	1	1001	1000	1000	1000	0	0	0	1022	24	0	5	10	0	1045	6	1	20	0	73	1	16	1	1	371	6	6	2	1000	390	382	375	381	382
1004	381	3	0	0	0	0	16	0	0	0	0	0	359	0	0	0	0	4	25	1000	1000	1000	14411	1	380	380	210	3	237	1000	1000	386	56	1	1	1001	1000	1000	1000	0	0	16	1010	0	0	0	0	10	1042	12	0	10	16	73	1	16	1	1	376	6	3	2	1000	381	382	382	381	398
1004	386	2	0	0	0	0	32	0	0	0	0	0	366	4	0	0	0	6	25	1000	1000	1000	14411	1	381	380	202	3	238	1000	1000	380	62	1	1	1001	1000	1000	1000	0	1	32	1010	0	0	4	0	10	1010	6	1	10	16	73	1	16	1	1	377	6	3	2	1000	381	388	382	382	381

Count: 8

Code:

  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3352

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	23	24	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26744	201	58	0	0	0	0	0	48	0	0	0	0	0	130	0	26699	0	1	0	0	7	25	80100	100	80000	100	80000	500	1167233	1	49	23644	0	26715	26723	16646	3	16672	80100	200	80000	200	26724	64	1	1	80201	100	99	100	80000	100	80000	0	100	80131	277	0	32	0	80020	455	0	82	0	84	80087	12	3	30	32	419	389	5110	2	16	2	2	26728	0	10	7	6	80000	100	26723	26725	26721	26719	26873
80204	26724	200	39	24	0	0	0	0	16	0	0	0	0	0	200	0	26709	0	0	0	0	7	25	80100	100	80000	100	80000	500	1167356	1	49	23638	0	26724	26717	16639	3	16681	80100	200	80000	200	26718	64	1	1	80201	100	99	100	80000	100	80000	0	100	80356	5	2	32	0	80010	73	0	396	0	93	80104	6	2	12	32	441	140	5110	2	16	2	2	26711	0	8	9	5	80000	100	26717	26717	26717	26717	26716
80204	26821	201	1	47	0	0	0	0	22	0	0	0	0	0	1	0	26709	6	1	0	0	7	25	80100	100	80000	100	80000	500	1167200	1	49	23644	0	26718	26723	16639	3	16684	80100	200	80000	200	26714	64	1	1	80201	100	99	100	80000	100	80000	0	100	80508	30	3	32	0	80011	652	2	445	8	104	80079	6	1	10	32	124	128	5110	2	16	2	2	26713	0	10	9	5	80000	100	26725	26715	26717	26717	26717
80204	26828	200	17	55	0	0	0	0	16	0	17	0	0	0	1	0	26701	0	0	0	0	5	25	80100	100	80000	100	80000	500	1167239	1	49	23645	0	26725	26716	16639	3	16681	80100	200	80000	200	26723	73	1	1	80201	100	99	100	80000	100	80000	0	100	80073	12	1	32	0	80020	460	0	36	0	70	80287	12	1	10	32	374	141	5110	2	16	2	2	26712	0	10	0	0	80000	100	26716	26725	26716	26716	26717
80204	26729	200	74	0	0	0	0	0	16	0	8	0	0	0	168	0	26701	0	1	0	0	12	25	80100	100	80000	100	80000	500	1167631	1	49	23636	0	26733	26715	16639	3	16673	80100	200	80000	200	26722	73	1	1	80201	100	99	100	80000	100	80000	0	100	80442	180	2	16	0	80010	469	0	437	0	60	80187	6	1	21	16	455	350	5110	2	16	2	2	26714	0	10	7	5	80000	100	26716	26717	26717	26717	26715
80204	26821	200	52	80	0	0	0	0	33	0	5	0	0	0	3	0	26698	0	0	0	0	7	25	80100	100	80000	100	80000	500	1166929	1	49	23636	0	26715	26716	16637	3	16672	80100	200	80000	200	26722	64	1	1	80201	100	99	100	80000	100	80000	0	100	80380	121	0	16	0	80033	293	0	77	0	116	80271	6	1	10	16	64	384	5110	2	16	2	2	26719	0	10	9	5	80000	100	26727	26717	26717	26717	26719
80204	26723	200	0	0	0	0	0	0	199	0	5	1	0	0	100	0	26701	0	0	0	0	5	25	80100	100	80000	100	80000	500	1173996	1	49	23636	0	26716	26716	16631	3	16674	80100	200	80000	200	26724	64	1	1	80201	100	99	100	80000	100	80000	0	100	80377	136	0	16	0	80010	69	1	79	0	73	80184	6	1	21	16	115	316	5141	2	16	2	2	26711	0	10	7	5	80000	100	26716	26717	26717	26717	26718
80204	26839	200	35	15	0	0	0	0	18	0	4	0	0	0	0	0	26703	0	2	0	0	0	25	80100	100	80000	100	80000	500	1166610	1	49	23644	0	26723	26715	16638	3	16680	80100	200	80000	200	26715	64	1	1	80201	100	99	100	80000	100	80000	0	100	80300	197	1	32	0	80010	448	1	175	6	122	80165	6	1	10	16	398	357	5110	2	16	2	2	26711	0	0	9	0	80000	100	26716	26716	26719	26717	26710
80204	26834	201	29	6	0	0	0	0	22	0	0	0	0	0	115	0	26701	6	1	0	0	8	25	80100	100	80000	100	80000	500	1167681	1	49	23642	0	26716	26717	16637	3	16681	80100	200	80000	200	26716	64	1	1	80201	100	99	100	80000	100	80000	1	100	80115	148	0	16	0	80010	454	0	388	6	104	80078	6	2	10	16	80	101	5110	2	16	2	2	26711	0	10	7	5	80000	100	26719	26716	26710	26708	26717
80204	26822	200	53	51	1	0	0	0	16	0	4	0	0	0	0	0	26702	0	0	0	0	0	25	80100	100	80000	100	80000	500	1166799	1	49	23638	0	26710	26707	16639	3	16674	80100	200	80000	200	26721	64	1	1	80201	100	99	100	80000	100	80000	0	100	80419	0	1	0	0	80024	77	0	66	8	107	80087	12	1	10	16	463	333	5110	2	16	2	2	26713	0	10	9	5	80000	100	26716	26717	26719	26708	26719

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3358

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26896	202	1	0	1	0	0	0	364	76	1	0	0	6	88	26808	0	16	117	29	98	25	80010	10	80000	10	80000	50	1190365	1	0	49	23814	26851	26861	16823	3	16832	80010	20	80000	20	27215	74	1	1	80021	10	9	0	10	80000	10	80000	0	10	80225	0	13	464	0	80297	198	3	205	62	317	80430	158	20	287	285	9	48	5020	0	0	4	16	4	5	26861	11	13	14	80000	10	26884	26898	26879	26863	26850
80024	26883	201	0	0	2	0	0	0	403	118	1	0	0	8	116	26870	71	6	60	28	89	25	80010	10	80000	10	80000	50	1173838	1	0	49	23821	26833	26862	16778	3	16856	80010	20	80000	20	27024	74	1	1	80021	10	9	0	10	80000	10	80000	0	10	80174	5	11	339	0	80261	145	1	196	22	338	80579	120	20	226	365	65	276	5020	0	0	3	16	4	3	26866	10	12	12	80000	10	26845	26842	26892	26895	26866
80024	26878	202	0	0	0	0	0	0	350	143	0	0	0	34	0	26907	0	18	89	63	129	25	80010	10	80000	10	80000	50	1175610	1	0	49	23806	26888	26853	16820	3	16878	80010	20	80000	20	26988	69	1	1	80021	10	9	0	10	80000	10	80000	0	10	80165	0	5	329	0	80261	188	1	183	20	333	80415	118	16	262	365	6	168	5020	0	0	4	16	9	6	26836	8	8	9	80000	10	26845	26818	26856	26854	26832
80024	26818	201	0	0	0	0	0	0	392	102	1	0	0	7	100	26849	160	16	56	28	108	25	80010	10	80000	10	80000	50	1174100	1	0	49	23829	26990	26861	16788	3	16818	80010	20	80000	20	27208	69	1	1	80021	10	9	0	10	80000	10	80000	0	10	80135	4	17	378	0	80290	170	2	135	20	341	80422	95	14	293	302	12	139	5020	0	0	3	16	6	7	26889	8	18	13	80000	10	26903	26888	26881	26929	26875
80024	26879	201	0	1	1	4	0	0	496	122	0	0	0	12	88	26831	111	10	51	70	101	25	80010	10	80000	10	80000	50	1171999	1	0	49	23826	26846	26838	16789	3	16838	80010	20	80000	20	26976	69	1	1	80021	10	9	0	10	80000	10	80000	0	10	80223	8	23	387	0	80276	262	2	240	22	286	80524	150	24	364	314	96	172	5020	0	0	6	16	3	6	26886	19	9	10	80000	10	26824	26833	26849	26842	26866
80024	26847	201	0	0	0	2	0	0	339	87	1	0	0	10	56	26862	106	15	83	57	105	25	80010	10	80000	10	80000	50	1172998	1	0	49	23809	26860	26857	16797	3	16824	80010	20	80000	20	26970	75	1	1	80021	10	9	1	10	80000	10	80000	0	10	80170	0	15	408	0	80215	242	5	189	66	301	80509	110	23	234	314	20	137	5020	0	0	3	16	3	4	26870	13	13	10	80000	10	26874	26853	26866	26871	26864
80024	26882	201	0	0	1	2	0	0	484	147	0	0	0	15	84	26860	110	17	57	67	76	25	80010	10	80000	10	80000	50	1175148	1	0	49	23755	26847	26834	16774	3	16853	80010	20	80000	20	27000	74	1	1	80021	10	9	1	10	80000	10	80000	0	10	80120	0	5	380	0	80389	277	2	161	26	314	80490	123	22	271	290	58	5	5020	0	0	7	16	7	4	26863	18	20	9	80000	10	26825	26847	26826	26844	26835
80024	26827	201	0	0	1	0	0	0	528	126	1	0	0	9	48	26827	77	16	141	70	99	25	80010	10	80000	10	80000	50	1170112	1	0	49	23755	26869	26868	16839	3	16841	80010	20	80000	20	26968	69	1	1	80021	10	9	0	10	80000	10	80000	0	10	80171	22	6	348	0	80278	133	5	117	18	450	80389	113	20	264	374	5	90	5020	0	0	4	16	7	6	26904	14	10	4	80000	10	26888	26878	26892	26884	26868
80024	26878	201	0	3	0	0	0	0	417	97	1	0	0	10	68	26843	119	21	42	38	82	25	80010	10	80000	10	80000	50	1171967	1	0	49	23747	26866	26841	16798	3	16853	80010	20	80000	20	26993	69	1	1	80021	10	9	0	10	80000	10	80000	0	10	80198	0	16	370	0	80263	102	4	183	0	316	80449	95	20	363	310	83	19	5020	0	0	3	16	6	7	26861	6	3	9	80000	10	26847	26898	26912	26897	26845
80024	26873	201	0	0	0	0	0	0	436	122	1	0	0	9	60	26846	113	16	65	95	86	25	80010	10	80000	10	80000	50	1180408	1	0	49	23775	26875	26840	16806	3	16860	80010	20	80000	20	26976	74	1	1	80021	10	9	0	10	80000	10	80000	0	10	80181	1	21	428	0	80251	140	4	215	0	379	80481	98	15	242	333	57	138	5020	0	0	7	16	7	6	26861	18	17	7	80000	10	26881	26871	26885	26849	26893

LDR (literal, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations