Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (literal, 32-bit)

Test 1: uops

Code:

  ldr w0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)0e0f1e2022243a3e3f404346494f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5b6bbl1d cache miss ld nonspec (bf)cfd5map dispatch bubble (d6)ddfetch restart (de)e0eaebec? ldst retires (ed)f5f6f7f8fd
100437930001161010003650000425100010001000143581388381203324410001000380621110011000100010030032101070124181028121101673116113764321000388375382381382
10043793000000000036500004251000100010001441113743741973239100010003746211100110001000100000010101300010101261101673116113776321000392382382381387
100438730000160100036600009251000100010001476913803802033238100010003815611100110001000100000161022000010101000103273116113837421000382382381388388
100438030000160000036500003251000100010001485213743742033232100010003806211100110001000100000321020000010103261111673116113710321000382382382381381
1004387300001650000364000032510001000100014322138037921432371000100038062111001100010001000120321010000010103561403273116113774321000381388382381382
1004387300001090100036600004251000100010001461713813802033238100010003876211100110001000101000321010019010101260101673116113776321000380382382381380
1004380300003200004365000042510001000100014850137938020332451000100038162111001100010001007003210100000101025121201673116113776321000381388382381375
1004381300000700003650000025100010001000143581380381203323910001000374621110011000100010000001022240510010456120073116113716621000390382375381382
1004381300001600000359000042510001000100014411138038021032371000100038656111001100010001000001610100000101042120101673116113766321000381382382381398
100438620000320000036640006251000100010001441113813802023238100010003806211100110001000100001321010004010101061101673116113776321000381388382382381

Test 2: throughput

Count: 8

Code:

  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4
  ldr w0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3352

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f202223243a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a5ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5b6bbl1d cache miss ld nonspec (bf)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
802042674420158000004800000130026699010072580100100800001008000050011672331492364402671526723166463166728010020080000200267246411802011009910080000100800000100801312770320800204550820848008712330324193895110216222672801076800001002672326725267212671926873
802042672420039240000160000020002670900007258010010080000100800005001167356149236380267242671716639316681801002008000020026718641180201100991008000010080000010080356523208001073039609380104621232441140511021622267110895800001002671726717267172671726716
8020426821201147000022000001026709610072580100100800001008000050011672001492364402671826723166393166848010020080000200267146411802011009910080000100800000100805083033208001165224458104800796110321241285110216222671301095800001002672526715267172671726717
80204268282001755000016017000102670100005258010010080000100800005001167239149236450267252671616639316681801002008000020026723731180201100991008000010080000010080073121320800204600360708028712110323741415110216222671201000800001002671626725267162671626717
8020426729200740000016080001680267010100122580100100800001008000050011676311492363602673326715166393166738010020080000200267227311802011009910080000100800000100804421802160800104690437060801876121164553505110216222671401075800001002671626717267172671726715
8020426821200528000003305000302669800007258010010080000100800005001166929149236360267152671616637316672801002008000020026722641180201100991008000010080000010080380121016080033293077011680271611016643845110216222671901095800001002672726717267172671726719
8020426723200000000199051001000267010000525801001008000010080000500117399614923636026716267161663131667480100200800002002672464118020110099100800001008000001008037713601608001069179073801846121161153165141216222671101075800001002671626717267172671726718
80204268392003515000018040000026703020002580100100800001008000050011666101492364402672326715166383166808010020080000200267156411802011009910080000100800000100803001971320800104481175612280165611016398357511021622267110090800001002671626716267192671726710
802042683420129600002200000115026701610082580100100800001008000050011676811492364202671626717166373166818010020080000200267166411802011009910080000100800001100801151480160800104540388610480078621016801015110216222671101075800001002671926716267102670826717
80204268222005351100016040000026702000002580100100800001008000050011667991492363802671026707166393166748010020080000200267216411802011009910080000100800000100804190100800247706681078008712110164633335110216222671301095800001002671626717267192670826719

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3358

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f1e2022292b3a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a5ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5b6bbl1d cache miss ld nonspec (bf)c2c3cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
8002426896202101000364761006882680801611729982580010108000010800005011903651049238142685126861168233168328001020800002027215741180021109010800001080000010802250134640802971983205623178043015820287285948502000416452686111131480000102688426898268792686326850
8002426883201002000403118100811626870716602889258001010800001080000501173838104923821268332686216778316856800102080000202702474118002110901080000108000001080174511339080261145119622338805791202022636565276502000316432686610121280000102684526842268922689526866
80024268782020000003501430003402690701889631292580010108000010800005011756101049238062688826853168203168788001020800002026988691180021109010800001080000010801650532908026118811832033380415118162623656168502000416962683688980000102684526818268562685426832
80024268182010000003921021007100268491601656281082580010108000010800005011741001049238292699026861167883168188001020800002027208691180021109010800001080000010801354173780802901702135203418042295142933021213950200031667268898181380000102690326888268812692926875
800242687920101140049612200012882683111110517010125800101080000108000050117199910492382626846268381678931683880010208000020269766911800211090108000010800000108022382338708027626222402228680524150243643149617250200061636268861991080000102682426833268492684226866
800242684720100020033987100105626862106158357105258001010800001080000501172998104923809268602685716797316824800102080000202697075118002110911080000108000001080170015408080215242518966301805091102323431420137502000316342687013131080000102687426853268662687126864
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80024268782010300004179710010682684311921423882258001010800001080000501171967104923747268662684116798316853800102080000202699369118002110901080000108000001080198016370080263102418303168044995203633108319502000316672686163980000102684726898269122689726845
80024268732010000004361221009602684611316659586258001010800001080000501180408104923775268752684016806316860800102080000202697674118002110901080000108000001080181121428080251140421503798048198152423335713850200071676268611817780000102688126871268852684926893