Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMADDL

Test 1: uops

Code:

  smaddl x0, w0, w1, x2
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004303323006119222510001000100081440040303330332760328911000100030003033380111001100000732161129391000100030343034303430343034
1004303323036119222510001000100081440040303330332760328911000100030003033380111001100009731161129391000100030343034303430343034
1004303323006119222510001000100081440040303330332760328911000100030003033380111001100003731161129511000100030343034303430343034
1004303324006119222510001000100081440040303330332760328911000100030003033380111001100000731161129391000100030343034303430343034
10043033220025119222510001000100081440040303330332760328911000100030003033380111001100000731161129391000100030343034303430343034
10043033220061192225100010001000814400403033303327603289110001000300030333801110011000012731161129391000100030343034303430343034
1004303323006119222510001000100081440040303330332760328911000100030003033380111001100000731161129391000100030343034303430343034
1004303322006119222510001000100081440040303330332760328911000100030003033380111001100000731161129391000100030343034303430343034
10043033230011419222510001000100081440040303330332760328911000100030003033380111001100000731161129391000100030343034303430343034
10043033220013919222510001000100081440040303330332760328911000100030003033380111001100000731161129391000100030343034303430343034

Test 2: Latency 1->2

Code:

  smaddl x0, w0, w1, x2
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03mmu table walk data (08)093f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020430033224106119922251010010100101008289401492695330033300332861032874110100102003020030033374111020110099100101001003101140710116112993910000101003003430034300343003430034
10204300332250061199222510100101001010082894004926953300333003328610328741101001020030200300333741110201100991001010010000000710116112993910000101003003430034300343003430034
10204300332250061199222510100101001010082894014926953300333003328610328741101001020030200300333741110201100991001010010000000710116112993910000101003003430034300343003430034
10204300332240061199222510100101001010082894014926953300333003328610328741101001020030200300333741110201100991001010010000000710116112993910000101003003430034300343003430034
10204300332250061199222510100101001010082894004926953300333003328610328741101001020030200300333741110201100991001010010002000710116112999810000101003003430034300343003430034
102043003322500611992225101001010010100828940049269533003330033286103287411010010200302003003337411102011009910010100100025030710116112993910000101003003430034300343003430034
10204300332250061199222510100101001010082894004926953300333003328610328741101001020030200300333741110201100991001010010000000710116112993910000101003003430034300343003430034
10204300332250061199222510100101001010082894004926953300333003328610328741101001020030200300333741110201100991001010010000000710116112993910000101003003430034300343003430034
102043003322500103199222510100101001010082894004926953300333003328610328741101001020030200300333741110201100991001010010002030710116112993910000101003003430034300343003430034
10204300332250061199222510100101001010082894014926953300333003328610328741101001020030200300333741110201100991001010010004000710116112993910000101003003430034300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)18191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024300332250000000611992225100101001010010828490049269533003330033286323287631001010020300203003338011100211091010010100000640316342993910000100103003430034300343003430034
1002430033225000000061199222510010100101001082849014926953300333003328632328763100101002030020300333801110021109101001010026210640416432993910000100103003430034300343003430034
1002430033225000000053619922251001010010100108284901492695330033300622863232876310010100203002030033380111002110910100101003400640316342993910000100103003430034300343003430034
10024300332250000000611992225100101001010010828891149269533003330033286323287631001010020300203003338011100211091010010100100640316342993910000100103003430034300343003430034
100243003322400000006119922251001010010100108284900492695330033300332863232876310010100203002030033380111002110910100101004100640316432993910000100103003430034300343003430034
100243003322500000006119922251001010010100108284901492695330033300332863232876310010100203002030033380111002110910100101003900640416432993910000100103003430034300343003430034
100243003322500000006119922251001010010100108284900492695330033300332863232876310010100203002030033380111002110910100101003200640316442993910000100103003430034300343003430034
100243003322400000006119922251001010010100108284900492695330033300332863232876310010100203002030033380111002110910100101005600640316442993910000100103003430034300343003430034
1002430033225000000056019922251001010010100108284901492695330033300332863232876310010100203002030033380111002110910100101000450640416222993910000100103003430034300343003430034
100243003322400000006119922251001010010100108284900492695330033300332863232876310010100203002030033380111002110910100101002290640416442993910000100103003430034300343003430034

Test 3: Latency 1->3

Code:

  smaddl x0, w1, w0, x2
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ec? int retires (ef)f5f6f7f8fd
10204300332250000273199222510100101001010082894014926953030033300332861762873610100102083022430033374111020110099100101001000001117180160029950100000101003003430034300343003430034
10204300332250000170199222510100101001010082894014926953030033300332861772875910100102083022430033374111020110099100101001000001117180160029950100000101003003430034300343003430034
1020430033225000084199222510100101001010082894014926953030033300332861772873610100102083022430033374111020110099100101001000001117170160029949100000101003003430034300343003430034
10204300332250000193199222510100101001010082894014926953030033300332861762873710100102083022430033374111020110099100101001000001117170160029950100000101003003430034300343003430034
10204300332250000170199222510100101001010082894014926953030033300332861762873710100102083020030033374111020110099100101001000000007101161129939100000101003003430034300343003430034
10204300332240000170199222510100101001010082894014926953030033300332861032874110100102003020030033374111020110099100101001000000007101161129939100000101003003430034300343003430034
102043003322500001701992225101001010010100828940149269530300333003328610328741101001020030200300333741110201100991001010010000180007101161129939100000101003003430034300343003430034
10204300332250000149199222510100101001010082894014926953030033300332861032874110100102003020030033374111020110099100101001000000007101161129939100000101003003430034300343003430034
10204300332250000170199222510100101001010082894014926953030033300332861032874110100102003020030033374111020110099100101001000000007101161129939100000101003003430034300343003430034
1020430033225000061199222510100101001010082894014926953030033300332861032874110100102003020030033374111020110099100101001000000007101161129939100000101003003430034300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)033f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100243003322566199222510010100101001082849014926953030033300332863232876310010100203002030033380111002110910100101030640216222993910000100103003430034300343003430034
100243003322561199222510010100101001082849014926953030033300332863232876310010100203002030033380111002110910100101020640216222993910000100103003430034300343003430034
100243003322561199222510010100101001082849014926953030033300332863232876310010100203002030033380111002110910100101000640216222993910000100103003430034300343003430034
100243003322461199222510010100101001082849014926953030033300332863232876310010100203002030033380111002110910100101010640216222993910000100103003430034300343003430034
1002430033224611992211010010100101001082849014926953030033300332864732876310010100203020030033380111002110910100101060640216222993910000100103003430034300343003430034
100243003322561199222510010100101001082849004926953030033300332863232876310010100203002030033380111002110910100101010640216222993910000100103003430034300343003430034
100243003322561199222510010100101001082849004926953030033300332863232876310010100203002030033380111002110910100101000640216222993910000100103003430034300343003430034
100243003322461199222510010100101001082849004926953030033300332863232876310010100203002030033380111002110910100101000640216222993910000100103003430034300343003430034
1002430033224611992225100101001010010828490049269530300333003328632328763100101002030020300333801110021109101001010539640216222993910000100103003430034300343003430034
100243003322561199222510033100101001082849004926953030033300332863232876310010100203002030033380111002110910100101079640216222993910000100103003430034300343003430034

Test 4: Latency 1->4

Code:

  smaddl x0, w1, w2, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102041003776000009225101001010010100704981496957100371003787143874510100102003020010037162111020110099100101001000007100116111003310000101001003810038100381003810038
102041003775000004825101001010010100704981496957100371003787143874510100102003020010037162311020110099100101001000007100116111003310000101001003810038100381003810038
102041003775011004825101001010010100704981496957100371003787143874510100102003020010037162111020110099100101001000007100116111003310000101001003810038100381003810038
102041003776000009025101001010010100704981496957100371003787143874510100102003020010037162111020110099100101001000007100116111003310000101001003810038100381003810038
102041003776000004825101001010010100704981496957100371003787143874510100102003020010037162111020110099100101001000007100116111003310000101001003810038100381003810038
102041003775000004825101001010010100704981496957101831003787143874510100102003020010037162111020110099100101001000007100116131003310000101001003810038100381003810038
102041003775000004825101001010010100704981496957100371003787143874510100102003020010037162111020110099100101001000007100116111003310000101001003810038100381003810038
1020410037760000047625101001010010100704981496957100371003787143874510100102003020010037162111020110099100101001000007100116111003310000101001003810038100381003810038
102041003775000004825101001010010100704981496957100371003787143874510100102003020010037162111020110099100101001001007100116111003310000101001003810038100381003810038
102041003775100004825101001010010100704981496957100371003787143874510100102003020010037162111020110099100101001000007100116111003310000101001003810038100381003810038

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0037

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003775004825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101003640216221003310000100101003810038100381003810038
100241003775004825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101006640216221003310000100101003810038100381003810038
100241003775004825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038
100241003775004825100101001010010700480496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038
1002410037750048251001010010100107004814969571003710037873638767100101002030020100371641110021109101001010310640216221003310000100101003810038100381003810038
100241003775004825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101003640216221003310000100101003810038100381003810038
100241003775004825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038
100241003775004825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038
100241003775004825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101003640216221003310000100101003810038100381003810038
100241003776004825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038

Test 5: throughput

Count: 8

Code:

  smaddl x0, w8, w9, x9
  smaddl x1, w8, w9, x9
  smaddl x2, w8, w9, x9
  smaddl x3, w8, w9, x9
  smaddl x4, w8, w9, x9
  smaddl x5, w8, w9, x9
  smaddl x6, w8, w9, x9
  smaddl x7, w8, w9, x9
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020480035599000236258010080100801004005001497695580035800356996436999380100802002402008003516411802011009910080100100000000005110216228003180000801008003680036800368003680036
802048003559900046258010080100801004005001497695580035800356996436999380100802002402008003516411802011009910080100100000000005110216228003180000801008003680036800368003680036
8020480035599000711258010080100801004005001497695580035800356996436999380100802002402008003516411802011009910080100100000000005110216118003180000801008003680036800368003680036
802048003560000046258010080100801004005001497695580035800356996436999380100802002402008003516411802011009910080100100000000005110116228003180000801008003680036800368003680036
8020480035599000426258010080100801004005001497695580035800356996436999380100802002402008003516411802011009910080100100000000005110216228003180000801008003680036800368003680036
802048003559900046258010080100801004005001497695580035800356996436999380100802002402008003516411802011009910080100100000000005110116228003180000801008003680036800368003680036
802048003560000046258010080100801004005001497695580035800356996436999380100802002402008003516411802011009910080100100000000005110116228003180000801008003680036800368003680036
802048003559900046258010080100801004005001497695580035800356996436999380100802002402008003516411802011009910080100100000000005110216218003180000801008003680036800368003680036
802048003560000067258012180100801004005001497695580035800356996436999380188802002402008003516411802011009910080100100200000005110216228003180000801008003680036800368003680036
802048003559900046258010080100801004005001497695580035800356996436999380100802002402008003516411802011009910080100100000000005110216118003180000801008003680036800368003680036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? int retires (ef)f5f6f7f8fd
800248003559900004625800108001080010400050497695580035800356998637001580010800202400208003516411800211091080010100000050209163480032800000800108003680036800368003680036
800248003560000004625800108001080010400050497695580035800356998637001580054800202400208003516411800211091080010100000050204164280032800000800108003680036800368003680036
800248003559900004625800108001080010400050497695580035800356998637001580010800202400208003516411800211091080010100000050202162480032800000800108003680036800368003680036
800248003560000004625800108001080010400050497695580035800356998637001580010800202400208003516411800211091080010100000050204164280032800000800108003680036800368003680036
800248003559900004625800108001080010400050497695580035800356998637001580010800202400208003516411800211091080010100000050202162480032800000800108003680036800368003680036
800248003559900004625800108001080010400050497695580035800356998637001580010800202400208003516411800211091080010100000050204164280032800000800108003680036800368003680036
800248003559900004625800108001080010400050497695580035800356998637001580010800202400208003516411800211091080010100000050204164280032800000800108003680036800368003680036
800248003560000004625800108001080010400050497695580035800357002237001580010800202404168012616421800211091080010100032050342162480032800000800108003680036800368003680036
800248003559900004625800108001080010400050497695580035800356998637001580010800202400208003516411800211091080010100000050202162480032800000800108003680036801268003680036
800248003559910121084625800108001080010400050497695580035800356998637001580010800202400208003516411800211091080010100100050202162480032800000800108003680036800368003680036