Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SBFIZ (64-bit)

Test 1: uops

Code:

  sbfiz x0, x0, #3, #7
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03181e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10041035700618622510001000100016916010351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035703618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035800618622510001000100016916010351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035800828622510001000100016916010351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035810618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
100410358001198622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035700618622510001000100016916010351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035800618622510001000100016916010351035728386810001000100010354111100110000073141119371000100010361036103610361036
100410358001038622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
100410358012618622510001000100016916010351035728386810001000100010354111100110000073141119371000100010361036103610361036

Test 2: Latency 1->2

Code:

  sbfiz x0, x0, #3, #7
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102041003576014598772510100101001011787686149695510035100358607787341011710240102401003541111020110099100101001000011172001600996510000101001003610036100361003610036
10204100357506198772510100101001011787686149695510035100358607787341011710200102001003541111020110099100101001000000071013711994110000101001003610036100361003610036
102041003575039798772510100101001010088664149695510035100358580387221010010200102001003541111020110099100101001000000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664149695510035100358580387221010010200102001003541111020110099100101001000000071013711994110000101001003610036100361003610036
102041003575075098772510100101001010088664149695510035100358580387221010010200102001003541111020110099100101001001000071013711994110000101001003610036100361003610036
10204100357596198772510100101001010088664149695510035100358580387221010010200102001003541111020110099100101001000000071013711994110000101001003610036100361003610036
102041003575041598772510100101001010088664149695510035100358580387221010010200102001003541111020110099100101001000000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664149695510035100358580387221010010200102001003541111020110099100101001000000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664049695510035100358580387221010010200102001003541111020110099100101001000000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664049695510035100358580387221010010200102001003541111020110099100101001000000071013711994110000101001003610036100361007410036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024100357501039863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064034122994010000100101003610036100361003610036
1002410035750619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
10024100357501779863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
1002410035750619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100364024122994010000100101003610036100361003610036
1002410035750619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010101064024122994010000100101003610036100361003610036
10024100357501039863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
1002410035750619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
1002410035750619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
1002410035750619863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100064024122994010000100101003610036100361003610036
10024100357501039863251001010010100108878414969551003510035860238740100101002010020100354111100211091010010100364024122994010000100101003610036100361003610036

Test 3: throughput

Count: 8

Code:

  sbfiz x0, x8, #3, #7
  sbfiz x1, x8, #3, #7
  sbfiz x2, x8, #3, #7
  sbfiz x3, x8, #3, #7
  sbfiz x4, x8, #3, #7
  sbfiz x5, x8, #3, #7
  sbfiz x6, x8, #3, #7
  sbfiz x7, x8, #3, #7
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1674

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802041339010100000000282780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010000000001115119016001338780036801001339113391133911339113391
802041339010000000000282780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010000000001115119016001338780036801001339113391133911339113391
802041339010000000000282780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010000000001115119016001338780036801001339113391133911339114511
8020413390100000000002827801368013680148400710149103101339013390332663336801488026480264133903911802011009910080100100000460301115119016001338780036801001339113391133911339113391
8020413390100000000002002780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000001115119016001338780036801001339113391133911339113391
802041339010000000000282780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010000000001115119016001338780036801001339113391133911339113391
802041339010100000000282780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010000000001115119016001338780036801001339113391133911339113391
802041339010100000000282780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010000000001115119016001338780036801001339113391133911339113391
802041339010000000000282780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010000000001115119016001338780036801001339113391133911339113391
802041339010000000000512780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010000000001115119016001338780036801001339113391133911339113391

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)03mmu table walk data (08)091e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? int retires (ef)f5f6f7f8fd
80024133901000205625800108001080010400050049102911337113371333033348800108002080020133713911800211091080010102020502100081900055133688000000800101337213372133721337213372
80024133711001003525800108001080010400050049102911337113371333033348800108002080020133713911800211091080010100000502100061900044133688000000800101337213372133721337213372
80024133711000093525800108001080010400050049102911337113371333033348800108002080020133713911800211091080010100000502000031900044133688000000800101337213372133721337213372
80024133711000003525800108001080010400050149102911337113371333033348800108002080020133713911800211091080010100000502100061900044133688000000800101337213372133721337213372
80024133711000003525800108001080010400050049102911337113371333033348800108002080020133713911800211091080010100000502100081900055133688000000800101337213372133721337213372
800241337110000027525800108001080010400050049102911337113371333033348800108002080020133713911800211091080010100000502100081900035133688000000800101337213372133721337213372
800241337110000011925800108001080010400050049102911337113371333033348800108002080020133713911800211091080010100000502100061900044133688000002800101337213372133721337213372
80024133711000009825800108001080010400050049102911337113371333033348800108002080020133713911800211091080010100000502000071900043133688000000800101337213372133721337213372
80024133711000009825800108001080010400050049102911337113371333033348800108002080020133713911800211091080010100000502100071900055133688000000800101337213372133721337213372
800241337110000041525800108001080010400050049102911337113371333033348800108002080020133713911800211091080010100000502000071900055133688000000800101337213372133721337213372