Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUBS (register, lsr, 32-bit)

Test 1: uops

Code:

  subs w0, w0, w1, lsr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004203515061100018622520002000100012623512035203517293186610001000200020354111100110000000733433319202000100020362036203620362036
1004203516061100018622520002000100012623512035203517293186610001000200020354111100110000020733433319202000100020362036203620362036
1004203515061100018622520002000100012623502035203517293186610001000200020354111100110000000733433319202000100020362036203620362036
1004203515061100018622520002000100012623502035203517293186610001000200020354111100110000000733433319202000100020362036203620362036
1004203515061100018622520002000100012623502035203517293186610001000200020354111100110000000733433319202000100020362036203620362036
10042035153661100018622520002000100012623502035203517293186610001000200020354111100110000000733433319202000100020362036203620362036
1004203516061100018622520002000100012623502035203517293186610001000200020354111100110000000733433319202000100020362036203620362036
1004203515061100018622520002000100012623512035203517293186610001000200020354111100110000000733433319202000100020362036203620362036
1004203515061100018622520002000100012623512035203517293186610001000200020354111100110000000733433319202000100020362036203620362036
1004203515061100018622520002000100012623502035203517293186610001000200020354111100110000000733433319202000100020362036203620362036

Test 2: Latency 1->2

Code:

  subs w0, w0, w1, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)033f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515061100001986225201002010010100130512114916955200352003518581031872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
1020420035150611000019862252010020100101001305121149169552003520035185810318720101001020020200200354111102011009910010100100190710239221992220000101002003620036200362007120036
102042003515061100001986225201002010010100130512104916955200352003518581031872010100102002020020035411110201100991001010010006710239221992220000101002003620036200362003620036
1020420035150611000019862252010020100103511305121149169552003520035185810318720101001020020200200354111102011009910010100100520710239221992220000101002003620036200362003620036
102042003515061100001986225201002010010100130512104916955200352003518581031872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
1020420035150611000019862252010020100101001305121149169552003520035185810318720101001020020200200354111102011009910010100100012710239221992220000101002003620036200362003620036
102042003515061100001986225201002010010100130512104916955200352003518581031872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
102042003515061100001986225201002010010100130512104916955200352003518581031872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
1020420035150611000019862252010020100101001305121049169552003520035185810318720101001020020200200354111102011009910010100100021710239221992220000101002003620036200362003620036
102042003515061100001986225201002010010100130512114916955200352003518581031872010100102002020020035411110201100991001010010003710239221992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515002511000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101000270640341221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000243640241221993020000100102003620036200362003620036
1002420035150061100001986225200102001010010130522914916955200352003518603318740100101002020020200354111100211091010010100023153640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229149169552003520035186033187401001010020200202003580111002110910100101000270640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101000210640241221993020000100102003620036200362003620036
1002420035150061100001986225200102001010010130753804916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
1002420035150061100001986225200102001010010130522904916955200352003518603318740100101002020020200354111100211091010010100036640241221993020000100102003620036200362003620036
1002420035150061100001986225200102001010010130522914916955200352003518603318740100101002020020200354111100211091010010100026640241221993020000100102003620036200362003620036
1002420035150061100001986225200102001010010130522914916955200352003518603318740100101002020020200354111100211091010010100000640241221993020000100102003620036200362003620036
100242003515006110000198622520010200101001013052291491695520035200351860331874010010100202002020035411110021109101001010000144640241221993020000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  subs w0, w1, w0, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cdcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020420035150000000006110000198622520100201001010013051210049169550200352003518581318720101001020020200200354111102011009910010100100000000071000139111992220000101002003620036200362003620036
1020420035150000000006110000198622520100201001010013051210049169550200352003518581318720101001020020200200354111102011009910010100100000000071000139111992220000101002003620036200362003620036
1020420035150000000006110000198622520100201001010013051210049169550200352003518581318720101001020020200200354111102011009910010100100000000071000139111992220000101002003620036200362003620036
1020420035150000000006110000198622520100201001010013051211049169550200352003518581318720101001020020200200354111102011009910010100100000000071000139111992220000101002003620036200362003620036
1020420035157000000006110000198622520180201001010013051211049169550200352003518581318720101001020020200200354111102011009910010100100000700071000139211995320000101002003620036200362003620036
1020420035150000000006110000198622520100201001010013051210049169550200352003518581318720101001020020200200354111102011009910010100100000000071000139111992220000101002003620036200362003620036
10204200351500000000061100001986225201002010010100130512110491695502003520035185813187201010010200202002003541111020110099100101001000000180071000139111992220000101002003620036200362003620036
1020420035150000000006110000198622520100201001010013051210049169550200352003518581318720101001020020200200354111102011009910010100100000800071000139111992220000101002003620036200362003620036
1020420035150000000006110000198624620133201001010013051211049169550200352003518581318720101001020020200200354111102011009910010100100000730071000139111992220000101002003620036200362003620036
1020420035150000001200103100001986225201002010010100130512110491695502008020035185817187201010010288202002008041111020110099100101001000001000071000139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515006110000198622520010200101001013052291491695520035200351860331874010010100202002020035411110021109101001010260640241221993020000100102003620036200362003620036
100242003515006110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010263640241221993020000100102003620036200362003620083
10024200351490611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
1002420035150061100001986225200102001010010130522904916955200352003518603318740100101002020020200354111100211091010010100120640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
100242003515005361000019862252001020010100101305229149169552008120035186033187401001010020200202003541111002110910100101000640241221993020000100102008320036200362003620036
1002420035150061100001986225200102001010010130522914916955200352003518603318740100101002020020200354111100211091010010101180640241221993020000100102003620036200362003620036
10025200351500611000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101036640241221993020000100102003620036200362003620036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs w0, w1, w2, lsr #17
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035225061100002989925301913010020107195624004926955300353003527391827485201072022430236300358511202011009910020100101002201111319162998330000201003003630036300363003630036
2020430035225082100002989925301003010020107195658104926955300353003527391827485201072022430236300358511202011009910020100101000001111319162998230000201003003630036300363003630036
2020430035225061100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101000001111319162998330000201003003630036300363003630036
20204300352250103100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101000001111320162998330000201003003630036300363003630036
2020430035225061100002989925301003010020107195624014926955300353003527391727486201072022430236300358511202011009910020100101000001111320162998330000201003003630036300363003630036
2020430035225061100002989925301003010020107195624014926955300353003527391827485201072022430236300358511202011009910020100101000001111319162998230000201003003630036300363003630036
2020430035225061100002989925301003010020107195624014926955300353003527391727486201072022430236300358511202011009910020100101000001111319162998230000201003003630036300363003630036
2020430035225061100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101000001111320162998230000201003003630036300363003630036
2020430035225061100002989925301003010020107195624004926955300353003527391827485201072022430236300358511202011009910020100101000001111319162998330000201003003630036300363003630036
20204300352250726100002989925301003010020107195624014926955300353003527391827486201072022430236300358511202011009910020100101000001111319162998230000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024300352250061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100102831270333112995930000200103003630036300363003630036
2002430035225006110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010961270133112995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100100151270133112995930000200103003630036300363003630036
20024300352240061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100103401270133112995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100104101270133112995930000200103003630036300363003630036
2002430035224006110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010451141270133112995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628914926955300353006727391327498200102002030020300358511200211091020010100104201270133112995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100100151270133112995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100103801270133112995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100103501270233112995930000200103003630036300363003630036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs w0, w1, w2, lsr #17
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204300352250726100002989925301003010020107195624004926955300353003527391827486201072022430236300358511202011009910020100101000201111320162998230000201003003630036300363003630036
2020430035225061100002989925301003010020107195624004926955300353003527391827485201072022430236300358511202011009910020100101000201111320162998230000201003006830036300363003630036
2020430035225061100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101000001111336162998230000201003003630036300363003630036
2020430035225061100002989925301003010020107195624004926955300353003527391827485201072022430236300358511202011009910020100101000001111320162998330000201003003630036300363003630036
2020430035225061100002989925301003010020107195624004926955300353003527391827485201072022430236300358511202011009910020100101000001111319162998330000201003003630036300363003630036
2020430035225061100002989925301003010020107195624004926955300353003527391727485201072022430236300358511202011009910020100101000001111320162998230000201003003630036300363003630036
2020430035225061100002989925301003010020107195624004926955300353003527391827485201072022430236300358511202011009910020100101000101111320162998230000201003003630036300363003630036
20204300352250251100002989925301003010020107195624004926955300353003527391827485201072022430236300358511202011009910020100101000001111319162998330000201003003630036300363003630036
2020430035225061100002989925301003010020107195624004923915300353003527391827486201072022430236300358511202011009910020100101000831111319162998330000201003003630036300363003630036
20204300352250156100002989925301003010020107195624004926955300353003527391827485201072022430236300358511202011009910020100101000001111320162998330000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024300352240000611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001003001270133112995930000200103003630036300363003630036
200243003522500012611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001004001270133112995930000200103003630036300363003630036
200243003522500004231000629899483003230010200101956289149269553003530035273913274982008620020300203012585112002110910200101001004001270133112995930000200103003630036300363003630036
200243003522500001031000029895253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001003001270133112995930000200103003630036300363003630036
2002430035225000126110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010010001270133112995930000200103003630036300363003630036
200243003522500304411000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001002001270133112995930000200103003630036300363003630036
200243003522400006110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010038601270133112995930000200103003630036300363003630036
20024300352250000611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001000001270133112995930000200103003630036300363003630036
20024300352250000611000029891253001030010200101956289149269553003530035273913274982001020020300203003585112002110910200101001001601270133112995930000200103003630036300363003630036
2002430035225000072610000298912530010300102001019562890982695530035300352739132749820010200203002030035851120021109102001010010027301270133112995930000200103003630036300363003630036

Test 6: throughput

Count: 8

Code:

  subs w0, w8, w9, lsr #17
  subs w1, w8, w9, lsr #17
  subs w2, w8, w9, lsr #17
  subs w3, w8, w9, lsr #17
  subs w4, w8, w9, lsr #17
  subs w5, w8, w9, lsr #17
  subs w6, w8, w9, lsr #17
  subs w7, w8, w9, lsr #17
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802045344940024579800004874125160100160100801003440005149503305341053410432983024343360801008020016020053410391180201100991008010010000051101241153390160000801005341153411534115341153411
8020453410399082800004874125160100160100801003440005149503305341053410432983024343360801008020016020053410391180201100991008010010000051101241153390160000801005341153411534115341153411
80204534104000996800004874125160100160100801003440005149503305341053410432983024343360801008020016020053410391180201100991008010010000051101241153390160000801005341153411534115341153411
80204534104000191800004874125160100160100801003440005149503305341053410432983024343360801008020016020053410391180201100991008010010000051101241153390160000801005341153411534115341153411
80204534104000170800004874125160100160100801003440005149503305341053410432982909343360801008020016020053410391180201100991008010010000051101241153390160000801005341153411534115341153411
802045341040001708000048741251601001601008010034400050495033053410534104329829091843360801008020016020053410391180201100991008010010003051101241153390160000801005341153411534115341153411
80204534104000170800004874125160100160100801003440005049503305341053410432983024343360801008020016020053410391180201100991008010010000051101241153390160000801005341153411534115341153411
802045341040001414800004874125160100160100801003440005049503305341053410432983024343360801008020016020053410391180201100991008010010000051101241153390160000801005341153411534115341153411
802045341040001236800004874125160100160100801003440005149503305341053410432983024343360801008020016020053410391180201100991008010010000051101241153390160000801005341153411534115341153411
80204534104000487800004874125160100160100801003440005149503305341053410432983024343360801008020016060053410391180201100991008010010000051101241153390160000801005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)ea? int retires (ef)f5f6f7f8fd
800245340140000618000047946251600101600108001034381300149503005338053380432903251343352800108002016002053380391180021109108001010305020224011533601600000800105338153381533815338153381
800245338040000618000047946251600101600108001034381300149503005338053380432903251343352800108002016002053380391180021109108001010305020124011533601600000800105338153381533815338153381
800245338040000618000047946251600101600108001034381300149503005338053380432902749343352800108002016002053380391180021109108001010505020124011533601600000800105338153381533815338153381
800245338040000618000047946251600101600108001034381300149503005338053380432902936343352800108002016002053380391180021109108001010065020124022533601600000800105338153381533815338153381
800245338039900618000047946251600101600108001034381300149503005338053380432903251343352800108002016002053380392180021109108001010505020124022533601600000800105338153381533815338153381
800245338039900618000047946251600101600108001034381300149503005338053380432903251343352800108002016002053380391180021109108001010205020124011533601600000800105338153381533815338153381
8002453380399006180000479462516001016001080010343813001495030053380533804329032513433528001080020160020533803911800211091080010105305074124011533601600000800105338153381533815338153381
800245338039900618000047946411600101600108001034381300149503005338053380432903251343352800108002016002053380391180021109108001010205020124011533601600000800105338153381533815338153381
800245338039900618000047946251600101600108001034381300149503005338053380432902936343352800108002016002053380391180021109108001010305020124011533601600000800105338153381533815338153381
800245338040000618000047946251600101600108001034381300149503005338053380432903251343352800108002016002053380391180021109108001010205020124011533601600000800105338153381533815338153381