Firestorm: PRFM (register, PSTL2STRM) measurements

Code:

  prfm pstl2strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1577	12	32	15	31	2404	1581	872	25	1000	1000	1000	68904	1	1594	1574	1272	3	1433	1000	1000	1000	1588	1569	1	1	1001	242	2235	2224	3232	0	0	0	2412	2250	1000	0	73	1	16	1	1	1515	1000	1616	1574	1622	1611	1597
1004	1614	12	31	16	31	2409	1575	871	25	1000	1000	1000	68914	1	1595	1611	1307	3	1506	1000	1000	1000	1574	1600	1	1	1001	266	2229	2261	3246	0	0	0	2391	2253	1000	0	73	1	16	1	1	1510	1000	1608	1611	1597	1619	1607
1004	1614	12	30	16	30	2408	1605	858	25	1000	1000	1000	68625	1	1598	1623	1315	3	1487	1000	1000	1000	1588	1570	1	1	1001	212	2239	2233	3247	2	0	0	2433	2251	1000	0	73	1	16	1	1	1507	1000	1599	1600	1623	1586	1628
1004	1624	11	30	15	32	2423	1613	865	25	1000	1000	1000	67859	1	1596	1573	1315	3	1443	1000	1000	1000	1582	1576	1	1	1001	215	2229	2261	3300	0	0	0	2450	2259	1000	0	73	1	16	1	1	1543	1000	1618	1602	1604	1585	1619
1004	1564	12	30	16	32	2413	1600	884	25	1000	1000	1000	68662	1	1605	1591	1312	3	1456	1000	1000	1000	1593	1592	1	1	1001	260	2235	2248	3229	0	0	0	2400	2241	1000	0	73	1	16	1	1	1561	1000	1625	1615	1611	1613	1626
1004	1601	12	31	17	30	2442	1559	885	25	1000	1000	1000	70324	1	1604	1581	1309	3	1463	1000	1000	1000	1582	1601	1	1	1001	237	2233	2250	3241	0	0	0	2420	2281	1000	0	73	1	16	1	1	1504	1000	1612	1628	1589	1583	1623
1004	1597	12	31	15	32	2410	1594	869	25	1000	1000	1000	69534	1	1570	1628	1294	3	1451	1000	1000	1000	1590	1597	1	1	1001	217	2259	2253	3260	0	0	0	2441	2241	1000	0	73	1	16	1	1	1513	1000	1625	1611	1612	1604	1622
1004	1574	12	31	16	31	2399	1574	888	25	1000	1000	1000	68586	1	1571	1632	1301	3	1449	1000	1000	1000	1578	1594	1	1	1001	260	2235	2243	3253	0	0	2	2399	2260	1000	0	73	1	24	1	1	1531	1000	1618	1629	1605	1606	1610
1004	1592	12	32	16	32	2411	1566	859	25	1000	1000	1000	69095	1	1591	1577	1290	3	1445	1000	1000	1000	1586	1607	1	1	1001	250	2246	2246	3246	0	0	0	2406	2261	1000	0	73	1	16	1	1	1490	1000	1581	1612	1597	1621	1615
1004	1622	12	32	15	33	2436	1600	882	25	1000	1000	1000	70186	1	1605	1579	1291	3	1485	1000	1000	1000	1596	1580	1	1	1001	223	2229	2253	3225	0	0	0	2413	2256	1000	0	73	1	16	1	1	1504	1000	1569	1576	1590	1615	1598

Test 2: throughput

Code:

  prfm pstl2strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5708

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15748	117	362	185	358	24642	15658	9740	25	20220	10193	10000	10100	10000	131638	728005	35	49	12696	15558	15602	12983	3	13137	20100	10200	10000	10200	10000	15571	148	1	1	20201	100	99	2167	100	10100	100	23100	22815	32964	0	24588	22979	10000	1310	1	17	1	1	15521	10093	10000	10100	15745	15634	15784	15635	15745
20204	15669	117	357	177	362	24838	15615	9741	25	20190	10217	10000	10100	10000	132760	735816	36	49	12654	15709	15657	12997	3	13051	20100	10200	10000	10200	10000	15611	148	1	1	20201	100	99	2331	100	10100	100	22895	22858	33027	0	24709	22982	10000	1310	1	16	1	1	15485	10129	10000	10100	15837	15652	15739	15717	15690
20204	15677	117	365	180	363	24756	15618	9708	25	20166	10229	10000	10100	10000	132373	730682	35	49	12603	15687	15707	13002	3	13192	20100	10200	10000	10200	10000	15647	155	1	1	20201	100	99	2320	100	10100	100	22941	22881	32944	0	24925	22826	10000	1310	1	17	1	1	15569	10114	10000	10100	15628	15735	15741	15667	15671
20204	15733	117	366	187	365	24712	15843	9660	25	20200	10214	10000	10100	10000	131966	734687	42	49	12576	15710	15727	12968	3	13141	20100	10200	10000	10200	10000	15646	146	1	1	20201	100	99	2313	100	10100	100	23086	22849	33089	0	24816	22908	10000	1310	1	16	1	1	15752	10105	10000	10100	15736	15667	15684	15598	15715
20204	15663	117	356	184	358	24711	15603	9777	25	20214	10211	10000	10100	10000	132135	734219	42	49	12568	15593	15625	13234	3	13158	20100	10321	10000	10200	10000	15657	152	1	1	20201	100	99	2288	100	10100	100	22808	22888	32907	0	24706	22934	10000	1310	1	16	1	1	15572	10087	10000	10100	15732	15668	15735	15658	15783
20204	15720	117	365	180	361	24905	15729	9747	25	20205	10232	10000	10100	10000	132799	736336	34	49	12575	15607	15625	12973	3	13230	20100	10200	10000	10200	10000	15646	154	1	1	20201	100	99	2270	100	10100	100	22946	23025	32950	0	24701	22950	10000	1310	1	16	1	1	15655	10105	10000	10100	15761	15745	15664	15768	15675
20204	15612	118	362	184	358	24935	15741	9651	25	20232	10211	10000	10100	10000	132648	739411	41	49	12532	15750	15630	12970	3	13195	20100	10200	10000	10200	10000	15610	148	1	1	20201	100	99	2281	100	10100	100	23093	23101	32892	0	24879	23082	10000	1310	1	16	1	1	15522	10123	10000	10100	15583	15694	15613	15737	15603
20204	15724	117	361	187	364	24583	15765	9724	25	20226	10211	10000	10100	10000	132032	730800	31	49	12486	15762	15797	13013	3	13255	20100	10200	10000	10200	10000	15760	141	1	1	20201	100	99	2326	100	10100	100	22742	23131	32994	0	24698	22888	10000	1310	1	16	1	1	15456	10099	10000	10100	15607	15699	15735	15697	15859
20204	15713	117	359	188	359	24728	15577	9800	25	20190	10232	10000	10100	10000	132373	734260	44	49	12582	15591	15706	12908	3	13167	20100	10200	10000	10200	10000	15677	156	1	1	20201	100	99	2405	100	10100	100	22742	22948	33025	0	24698	22835	10000	1310	1	17	1	1	15544	10150	10000	10100	15671	15616	15839	15678	15745
20204	15708	116	358	178	356	24427	15557	9776	25	20244	10205	10000	10100	10000	131918	732772	38	49	12592	15672	15612	12920	3	13151	20100	10200	10000	10200	10000	15574	148	1	1	20201	100	99	2283	100	10100	100	22851	22978	33104	0	24892	22851	10000	1310	1	17	1	1	15486	10108	10000	10100	15735	15690	15725	15636	15645

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5570

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15493	116	362	198	370	24811	15586	9674	25	20127	10157	10000	10010	10000	130664	733651	1	38	49	12265	15555	15657	12892	3	13137	20010	10020	10000	10020	10000	15766	155	1	1	20021	10	9	2199	10	10010	10	23137	23340	33189	0	24757	23248	10000	1270	2	16	1	1	15393	10147	10000	10010	15505	15577	15676	15464	15628
20024	15631	117	370	200	367	24982	15567	9555	25	20175	10163	10000	10010	10000	129664	727494	1	46	49	12415	15643	15434	12904	3	13101	20010	10020	10000	10020	10000	15647	158	1	1	20021	10	9	2148	10	10010	10	23016	23253	33004	0	24767	23280	10000	1270	1	16	1	1	15483	10135	10000	10010	15607	15560	15450	15577	15540
20024	15437	117	369	194	364	24908	15518	9719	25	20127	10124	10000	10010	10000	131609	731405	1	46	49	12382	15582	15584	12898	3	13038	20010	10020	10000	10020	10000	15576	156	1	1	20021	10	9	2184	10	10010	10	23079	23009	33309	0	24709	23183	10000	1271	1	16	1	1	15301	10141	10000	10010	15607	15632	15419	15546	15527
20024	15513	116	365	199	358	24857	15642	9565	25	20181	10124	10000	10010	10000	129883	734827	1	48	49	12502	15467	15471	13051	3	13145	20010	10020	10000	10020	10000	15502	154	1	1	20021	10	9	2227	10	10010	10	23046	23307	33113	0	24959	22917	10000	1270	1	16	1	1	15506	10141	10000	10010	15649	15595	15513	15680	15569
20024	15625	117	362	194	364	24899	15468	9771	25	20169	10160	10000	10010	10000	131590	731764	1	42	49	12345	15507	15445	12885	3	13064	20245	10020	10000	10020	10000	15523	154	1	1	20021	10	9	2214	10	10010	10	23031	22968	33316	0	25059	23178	10000	1271	1	16	2	1	15428	10144	10000	10010	15588	15553	15549	15555	15467
20024	15400	117	372	202	368	25004	15501	9746	25	20145	10151	10000	10010	10000	129924	731088	1	45	49	12492	15540	15495	12835	3	13046	20010	10020	10000	10020	10000	15623	163	1	1	20021	10	9	2282	10	10010	10	23403	23137	33148	1	24948	23006	10000	1270	1	15	1	1	15355	10153	10000	10010	15682	15553	15563	15511	15581
20024	15488	119	365	201	366	24930	15594	9567	25	20145	10142	10000	10010	10000	131686	725022	1	51	49	12463	15626	15597	13063	3	12985	20010	10020	10000	10020	10000	15546	157	1	1	20021	10	9	2173	10	10010	10	23322	23112	33299	0	24886	23147	10000	1270	1	16	1	1	15461	10144	10000	10010	15591	15448	15670	15603	15581
20024	15693	117	366	195	366	24739	15507	9512	25	20154	10145	10000	10010	10000	131188	736412	1	37	49	12352	15600	15682	12908	3	13045	20010	10020	10000	10020	10000	15716	155	1	1	20021	10	9	2204	10	10010	10	23050	23130	33006	0	24720	23050	10000	1270	1	16	1	1	15441	10156	10000	10010	15656	15468	15549	15686	15714
20024	15536	117	369	197	370	24726	15604	9543	25	20160	10175	10000	10010	10000	131566	725443	1	43	49	12520	15527	15622	12972	3	12975	20010	10020	10000	10020	10000	15560	163	1	1	20021	10	9	2224	10	10010	10	23105	23216	33186	0	24784	23119	10000	1270	1	15	1	1	15395	10102	10000	10010	15514	15523	15685	15555	15556
20024	15622	116	366	197	370	24788	15604	9543	25	20163	10142	10000	10010	10000	131555	731741	1	32	49	12526	15499	15567	13072	3	13185	20010	10020	10000	10020	10000	15530	156	1	1	20021	10	9	2161	10	10010	10	23345	23051	32925	0	24831	23297	10000	1270	1	16	1	1	15500	10126	10000	10010	15683	15486	15429	15669	15517

Test 3: throughput

Code:

  prfm pstl2strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5437

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15489	116	335	173	336	24563	15477	9466	25	10100	100	10000	100	10000	500	719543	1	49	12435	15488	15454	14041	7	14128	10100	200	10016	200	10008	15449	12254	1	1	10201	100	99	2516	100	100	100	22728	22760	32726	0	0	24564	22876	10000	0	1	1	1	719	16	0	15417	0	10000	100	15452	15453	15470	15367	15419
10204	15423	115	334	174	339	24566	15469	9504	54	10100	102	10059	100	10000	500	725972	1	49	12476	15401	15509	14011	7	14130	10100	200	10024	200	10024	15472	12261	1	1	10201	100	99	2593	100	100	100	22675	22720	32745	0	0	24444	22739	10000	0	1	1	1	719	16	0	15347	0	10000	100	15511	15510	15433	15413	15376
10204	15427	116	333	170	330	24464	15411	9467	25	10100	100	10000	100	10000	500	722577	1	49	12356	15462	15451	14005	7	14174	10100	200	10016	200	10016	15437	12151	1	1	10201	100	99	2577	100	100	100	22682	22838	32799	0	0	24566	22876	10000	0	1	1	1	719	16	0	15373	0	10000	100	15464	15444	15480	15402	15474
10204	15398	115	334	173	341	24612	15373	9502	25	10100	100	10000	100	10000	500	724873	1	49	12324	15476	15450	13978	7	14157	10103	200	10008	200	10008	15436	12243	1	1	10201	100	99	2613	100	100	100	22775	22754	32700	0	0	24575	22739	10000	0	1	1	1	719	16	0	15267	0	10000	100	15446	15457	15550	15449	15353
10204	15415	115	328	173	335	24524	15383	9443	25	10100	100	10000	100	10006	500	725290	1	49	12439	15463	15409	14023	6	14092	10103	200	10008	200	10008	15463	12184	1	1	10201	100	99	2597	100	100	100	22650	22819	32760	0	0	24588	22825	10000	0	1	1	1	717	16	0	15389	0	10000	100	15424	15493	15488	15389	15505
10204	15481	115	337	172	336	24545	15489	9427	25	10100	100	10000	100	10000	500	724035	1	49	12302	15466	15461	14065	6	14089	10100	200	10008	200	10008	15301	12238	1	1	10201	100	99	2549	100	100	100	22805	22739	32797	0	0	24542	22839	10000	0	1	1	1	718	16	0	15370	0	10000	100	15381	15413	15412	15376	15425
10204	15451	117	335	172	336	24591	15383	9472	25	10100	100	10000	100	10003	500	723080	1	49	12326	15425	15423	13986	7	14076	10100	200	10016	200	10008	15459	12212	1	1	10201	100	99	2626	100	100	100	22766	22682	32789	0	0	24639	22803	10000	0	1	1	1	717	16	0	15384	0	10000	100	15486	15448	15455	15481	15521
10204	15416	115	336	176	337	24553	15391	9473	25	10100	100	10000	100	10002	500	722209	1	49	12506	15524	15390	13997	7	14156	10100	200	10008	200	10008	15496	12200	1	1	10201	100	99	2551	100	100	100	22830	22683	32818	0	0	24542	22753	10000	0	1	1	1	718	16	0	15348	0	10000	100	15425	15573	15487	15485	15443
10204	15382	116	339	173	341	24601	15458	9523	25	10100	100	10000	100	10002	500	721963	1	49	12402	15479	15501	13920	6	14139	10100	200	10008	200	10008	15469	12220	1	1	10201	100	99	2552	100	100	100	22700	22771	32731	0	0	24437	22802	10000	0	1	1	1	717	16	0	15319	0	10000	100	15478	15401	15404	15358	15356
10204	15527	115	334	176	327	24522	15440	9458	25	10100	100	10000	100	10000	500	722030	1	49	12376	15401	15532	14016	6	14184	10100	200	10016	200	10016	15437	12155	1	1	10201	100	99	2552	100	100	100	22753	22729	32855	0	0	24598	22741	10000	0	1	1	1	717	16	0	15362	0	10000	100	15502	15499	15513	15379	15507

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5562

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15548	117	293	148	297	23984	15521	9475	25	10010	10	10000	10	10000	50	728652	1	49	12476	15545	15511	14150	3	14228	10010	20	10000	20	10000	15488	15494	1	1	10021	10	9	2728	10	10	10	22366	22257	32338	0	24047	22291	10000	0	640	2	16	2	2	15388	10000	10	15545	15607	15552	15497	15593
10024	15587	116	290	148	302	23973	15618	9601	25	10010	10	10000	10	10000	50	728246	1	49	12516	15520	15574	14089	3	14309	10010	20	10000	20	10000	15493	15513	1	1	10021	10	9	2702	10	10	10	22251	22287	32363	0	23875	22260	10000	0	640	2	16	2	2	15450	10000	10	15557	15526	15591	15557	15581
10024	15475	116	295	148	297	24022	15577	9689	25	10010	10	10000	10	10000	50	729636	1	49	12516	15579	15528	14187	3	14368	10010	20	10000	20	10000	15534	15528	1	1	10021	10	9	2675	10	10	10	22345	22270	32303	0	24027	22254	10000	0	640	2	16	2	2	15491	10000	10	15574	15586	15432	15616	15567
10024	15602	117	294	145	294	24024	15559	9793	25	10010	10	10000	10	10000	50	727146	1	49	12455	15574	15546	14089	3	14323	10010	20	10000	20	10000	15571	15484	1	1	10021	10	9	2682	10	10	10	22322	22282	32328	0	24016	22275	10000	0	640	2	16	2	2	15410	10000	10	15538	15575	15579	15568	15656
10024	15574	116	295	148	297	24000	15596	9692	25	10010	10	10000	10	10000	50	727506	1	49	12449	15573	15537	14171	3	14332	10010	20	10000	20	10000	15496	15552	1	1	10021	10	9	2674	10	10	10	22213	22301	32326	0	23939	22316	10000	0	640	2	16	2	2	15385	10000	10	15606	15662	15551	15594	15524
10024	15582	116	294	148	297	23970	15588	9584	25	10010	10	10000	10	10000	50	728798	1	49	12475	15578	15549	14187	3	14328	10010	20	10000	20	10000	15527	15550	1	1	10021	10	9	2651	10	10	10	22277	22348	32281	0	23939	22245	10000	0	640	2	16	2	2	15495	10000	10	15661	15463	15625	15580	15679
10024	15531	117	296	148	294	24262	15658	9539	25	10010	10	10000	10	10000	50	729125	1	49	12480	15664	15534	14052	3	14262	10010	20	10000	20	10000	15524	15507	1	1	10021	10	9	2745	10	10	10	22269	22302	32206	0	23997	22268	10000	0	640	2	16	2	2	15429	10000	10	15598	15538	15519	15542	15546
10024	15544	116	297	147	298	23969	15542	9624	25	10010	10	10000	10	10000	50	725594	1	49	12558	15676	15604	14211	3	14270	10010	20	10000	20	10000	15474	15509	1	1	10021	10	9	2742	10	10	10	22297	22332	32247	0	24063	22260	10000	0	640	2	16	2	2	15458	10000	10	15553	15524	15560	15577	15482
10024	15531	116	291	147	294	23938	15568	9606	25	10010	10	10000	10	10000	50	732208	1	49	12455	15568	15546	14124	3	14232	10010	20	10000	20	10000	15574	15533	1	1	10021	10	9	2649	10	10	10	22268	22279	32262	1	24003	22315	10000	0	640	2	16	2	2	15440	10000	10	15625	15580	15497	15604	15486
10024	15593	117	296	147	299	23993	15596	9625	25	10010	10	10000	10	10000	50	730126	1	49	12454	15544	15623	14146	3	14343	10010	20	10000	20	10000	15536	15491	1	1	10021	10	9	2728	10	10	10	22287	22332	32194	0	24018	22312	10000	0	640	2	16	2	2	15395	10000	10	15627	15661	15463	15581	15626

PRFM (register, PSTL2STRM)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations