Firestorm: CLREX measurements

Code:

  clrex

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3a	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	82	83	flush restart other nonspec (84)	85	inst all (8c)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	4755	36	0	0	0	0	4740	3558	25	1000	1000	1000	219584	0	49	1675	4755	4755	4307	3	4613	1000	1000	4755	4755	1	1	1001	1000	0	0	73	1	16	1	1	4586	1000	4756	4756	4756	4756	4756
1004	4755	36	0	0	0	0	4740	3558	25	1000	1000	1000	219584	1	49	1675	4755	4755	4307	3	4613	1000	1000	4755	4755	1	1	1001	1000	0	0	73	1	16	1	1	4586	1000	4756	4756	4756	4756	4756
1004	4755	35	0	0	0	0	4740	3558	25	1000	1000	1000	219584	0	49	1675	4755	4755	4307	3	4613	1000	1000	4755	4755	1	1	1001	1000	0	114	73	1	16	1	1	4586	1000	4756	4756	4756	4756	4756
1004	4755	35	0	0	0	0	4740	3558	25	1000	1000	1000	219584	1	49	1675	4755	4755	4307	3	4613	1000	1000	4755	4755	1	1	1001	1000	0	0	73	1	16	1	1	4586	1000	4756	4756	4756	4756	4756
1004	4755	35	0	0	0	0	4740	3558	40	1000	1000	1000	219584	1	49	1675	4755	4755	4307	3	4613	1000	1000	4755	4755	1	1	1001	1000	0	0	73	1	16	1	1	4586	1000	4756	4756	4756	4756	4756
1004	4755	36	0	0	0	0	4740	3558	25	1000	1000	1000	219584	1	49	1675	4755	4755	4307	3	4613	1000	1000	4755	4755	1	1	1001	1000	0	0	73	1	16	1	1	4586	1000	4756	4756	4756	4756	4756
1004	4755	36	0	0	0	0	4740	3558	25	1000	1000	1000	219584	1	49	1675	4755	4755	4307	3	4613	1000	1000	4755	4755	1	1	1001	1000	0	3	73	1	16	1	1	4586	1000	4756	4756	4756	4756	4756
1004	4755	35	0	0	0	0	4740	3558	25	1000	1000	1000	219584	1	49	1675	4755	4755	4307	3	4613	1000	1000	4755	4755	1	1	1001	1000	13	3	73	1	16	1	1	4586	1000	4756	4756	4756	4756	4756
1004	4755	36	0	0	0	0	4740	3558	25	1000	1000	1000	219584	1	49	1675	4755	4755	4307	3	4613	1000	1000	4755	4755	1	1	1001	1000	0	0	73	1	16	1	1	4586	1000	4756	4756	4756	4756	4756
1004	4755	36	0	0	0	0	4740	3558	25	1000	1000	1000	219584	1	49	1675	4755	4755	4307	3	4613	1000	1000	4755	4755	1	1	1001	1000	0	0	73	1	16	1	1	4586	1000	4756	4756	4756	4756	4756

Test 2: throughput

Code:

  clrex
  add x6, x6, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.9755

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	49755	372	0	0	0	0	0	0	49740	7	39558	25	20100	10100	10000	10100	10000	71159	2370584	0	49	46675	49755	49755	46907	3	47213	20100	10200	10000	10200	49755	242	1	1	20201	100	99	100	10100	100	0	0	0	0	10000	6	0	0	0	1310	1	16	1	1	49586	10000	10000	10100	49756	49756	49756	49756	49756
20204	49755	373	0	0	0	0	0	0	49740	7	39558	25	20100	10100	10000	10100	10000	71159	2370584	0	49	46675	49755	49755	46907	3	47213	20100	10200	10000	10200	49755	242	1	1	20201	100	99	100	10100	100	0	0	0	0	10000	50	0	6	0	1310	1	16	1	1	49586	10000	10000	10100	49756	49756	49756	49756	49756
20204	51879	372	0	0	0	0	0	0	49740	7	39558	25	20100	10100	10000	10100	10000	71159	2370584	0	49	46675	49755	49755	46907	3	47213	20100	10200	10000	10200	49755	242	1	1	20201	100	99	100	10100	100	0	0	0	0	10000	71	0	0	0	1310	1	16	1	1	49586	10000	10000	10100	49756	49756	49756	49756	49756
20204	49755	372	0	0	0	0	0	0	49740	7	39558	25	20100	10100	10000	10100	10000	71159	2370584	0	49	46675	49755	49755	46907	3	47213	20100	10200	10000	10200	49755	242	1	1	20201	100	99	100	10100	100	0	0	0	0	10000	68	0	0	0	1310	1	16	1	1	49586	10000	10000	10100	49756	49756	49756	49756	49756
20204	49755	373	0	0	0	0	0	0	49740	7	39558	25	20100	10100	10000	10100	10000	71159	2370584	0	49	46675	49755	49755	46907	3	47213	20100	10200	10000	10200	49755	242	1	1	20201	100	99	100	10100	100	0	0	0	0	10000	67	0	0	0	1310	1	16	1	1	49586	10000	10000	10100	49756	49756	49756	49756	49756
20204	49755	373	0	0	0	0	0	0	49740	7	39558	25	20100	10100	10000	10100	10000	71159	2370584	0	49	46675	49755	49755	46907	3	47213	20100	10200	10000	10200	49755	242	1	1	20201	100	99	100	10100	100	0	0	0	0	10000	81	0	6	0	1310	1	16	1	1	49586	10000	10000	10100	49756	49756	49756	49756	49756
20204	49755	373	0	0	0	0	0	0	49740	7	39558	25	20100	10100	10000	10100	10000	71159	2370584	0	49	46675	49755	49755	46907	3	47213	20100	10200	10000	10200	49755	242	1	1	20201	100	99	100	10100	100	0	0	0	0	10000	68	0	0	0	1310	1	16	1	1	49586	10000	10000	10100	49756	49756	49756	49756	49756
20204	49755	373	0	0	0	0	0	0	49740	7	39558	25	20100	10100	10000	10100	10000	71159	2370584	0	49	46675	49755	49755	46907	3	47213	20100	10200	10000	10200	49755	242	1	1	20201	100	99	100	10100	100	0	0	0	0	10000	72	0	0	0	1310	1	16	1	1	49586	10000	10000	10100	49756	49756	49756	49756	49756
20204	49755	372	0	0	0	0	0	0	49740	7	39558	25	20100	10100	10000	10100	10000	71159	2370584	0	49	46675	49755	49755	46907	3	47213	20100	10200	10000	10200	49755	242	1	1	20202	100	99	100	10100	100	0	0	0	0	10000	79	0	0	0	1310	1	16	1	1	49586	10000	10000	10100	49756	49756	49756	49756	49756
20204	49755	372	0	0	0	0	0	0	49740	8	39558	25	20100	10100	10000	10100	10000	71159	2370584	0	49	46675	49755	49755	46907	3	47213	20100	10200	10000	10200	49755	242	2	1	20201	100	99	100	10100	100	0	0	0	0	10000	72	0	0	0	1310	1	16	1	1	49586	10000	10000	10100	49756	49756	49756	49756	49756

1000 unrolls and 10 iterations

Result (median cycles for code): 4.9755

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	49755	372	0	0	0	0	0	0	0	0	0	0	49740	2	39558	25	20010	10010	10000	10010	10000	70851	2370584	0	49	46675	49755	49755	46929	3	47235	20010	10020	10000	10020	49755	247	1	1	20021	10	9	10	10010	10	0	0	0	0	10000	0	0	0	0	1270	3	16	3	3	49586	10000	10000	10010	49756	49756	49756	49756	49756
20024	49755	372	0	0	0	0	0	0	0	0	0	0	49740	2	39558	25	20010	10010	10000	10010	10000	70851	2370584	0	49	46675	49755	49755	46929	3	47235	20010	10020	10000	10020	49755	247	1	1	20021	10	9	10	10010	10	0	0	0	0	10000	0	0	0	0	1270	3	16	3	3	49586	10000	10000	10010	49756	49756	49756	49756	49756
20024	49755	372	0	0	0	0	0	0	0	0	0	0	49740	2	39558	25	20010	10010	10000	10010	10000	70851	2370584	0	49	46675	49755	49755	46929	3	47235	20010	10020	10000	10020	49755	247	1	1	20021	10	9	10	10010	10	0	0	0	0	10000	0	0	0	0	1270	3	16	3	3	49586	10000	10000	10010	49756	49756	49756	49756	49756
20024	49755	373	0	0	0	0	0	0	0	0	0	0	49740	2	39558	25	20010	10010	10000	10010	10000	70851	2370584	0	49	46675	49755	49755	46929	3	47235	20010	10020	10000	10020	49755	247	1	1	20021	10	9	10	10010	10	0	0	0	0	10000	0	0	0	0	1270	3	16	3	3	49586	10000	10000	10010	49756	49756	49756	49756	49756
20024	49755	372	0	0	0	0	0	0	0	0	0	0	49740	2	39558	25	20010	10010	10000	10010	10000	70851	2370584	0	49	46675	49755	49755	46929	3	47235	20010	10020	10000	10020	49755	247	1	1	20021	10	9	10	10010	10	0	0	0	0	10000	0	0	0	0	1270	3	16	4	3	49586	10000	10000	10010	49756	49756	49756	49756	49756
20024	49755	373	0	0	0	0	0	0	0	30	0	0	49740	2	39558	25	20010	10010	10000	10010	10000	70851	2370584	0	49	46675	49755	49755	46929	3	47235	20010	10020	10000	10020	49755	247	1	1	20021	10	9	10	10010	10	0	0	0	0	10000	0	0	0	0	1270	3	16	4	3	49586	10000	10000	10010	49756	49756	49756	49756	49756
20024	49755	373	0	0	0	0	0	0	0	0	0	0	49740	2	39558	25	20010	10010	10000	10010	10000	70851	2370584	0	49	46675	49755	49755	46929	3	47235	20010	10020	10000	10020	49755	247	1	1	20021	10	9	10	10010	10	0	0	0	0	10000	0	0	0	0	1270	3	16	3	3	49586	10000	10000	10010	49756	49756	49756	49756	49756
20024	49755	373	0	0	0	0	0	0	0	0	0	0	49740	2	39558	25	20010	10010	10000	10010	10000	70851	2370584	0	49	46675	49755	49755	46929	3	47235	20010	10020	10000	10020	49755	247	1	1	20021	10	9	10	10010	10	0	0	0	0	10000	0	0	0	0	1270	3	16	4	4	49586	10000	10000	10010	49756	49756	49756	49756	49756
20024	49755	372	0	0	0	0	0	0	0	0	0	0	49740	2	39558	25	20010	10010	10000	10010	10000	70851	2370584	0	49	46675	49755	49755	46929	3	47235	20010	10020	10000	10020	49508	247	1	1	20021	10	9	10	10010	10	0	0	0	0	10000	0	0	0	0	1270	3	16	3	3	49586	10000	10000	10010	49756	49756	49756	49756	49756
20024	49755	372	0	0	0	0	0	0	0	3	0	0	49740	2	39558	25	20010	10010	10000	10010	10000	70851	2370584	0	49	46675	49755	49755	46929	3	47235	20010	10020	10000	10020	49755	247	1	1	20021	10	9	10	10010	10	0	0	0	0	10000	0	0	0	0	1270	3	16	4	3	49586	10000	10000	10010	49756	49756	49756	49756	49756

Test 3: throughput

Code:

  clrex

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.9755

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	49755	373	0	0	0	49740	39558	25	10100	100	10000	100	10000	500	2370584	1	49	46675	49755	49755	48164	6	48459	10100	200	10008	200	49755	39447	1	1	10201	100	99	100	100	100	0	0	10000	0	0	0	1	1	1	717	0	16	0	49593	0	10000	100	49756	49756	49756	49756	49756
10204	49755	373	0	0	0	49740	39558	25	10100	100	10000	100	10000	500	2370584	0	49	46675	49755	49755	48164	6	48459	10100	200	10008	200	49755	39447	1	1	10201	100	99	100	100	100	0	0	10000	0	0	0	1	1	1	717	0	16	0	49593	0	10000	100	49756	49756	49756	49756	49756
10204	49755	372	0	0	0	49740	39558	25	10100	100	10000	100	10000	500	2370584	1	49	46675	49755	49755	48164	6	48459	10100	200	10008	200	49755	39447	1	1	10201	100	99	100	100	100	0	0	10000	0	0	0	1	1	1	717	0	16	0	49593	0	10000	100	49756	49756	49756	49756	49756
10204	49755	373	0	0	0	49740	39558	25	10100	100	10000	100	10000	500	2370584	1	49	46675	49755	49755	48164	6	48459	10100	200	10008	200	49755	39447	1	1	10201	100	99	100	100	100	0	0	10000	0	0	0	1	1	1	717	1	16	0	49593	0	10000	100	49756	49756	49756	49756	49756
10204	49755	373	0	0	0	49740	39558	25	10100	100	10000	100	10000	500	2370584	1	49	46675	49755	49755	48164	6	48459	10100	200	10008	200	49755	39447	1	1	10201	100	99	100	100	100	0	0	10000	0	0	0	1	1	1	717	0	16	0	49593	0	10000	100	49756	49756	49756	49756	49756
10204	49755	386	0	0	21	49740	39558	25	10100	100	10000	100	10000	500	2370584	1	49	46675	49755	49755	48164	6	48459	10100	200	10008	200	49755	39447	1	1	10201	100	99	100	100	100	0	0	10000	0	0	0	1	1	1	717	0	16	0	49593	0	10000	100	49756	49756	49756	49756	49756
10204	49755	372	0	0	0	49740	39558	25	10100	100	10000	100	10000	500	2370584	0	49	46675	49755	49755	48164	6	48459	10100	200	10008	200	49755	39447	1	1	10201	100	99	100	100	100	0	0	10000	0	0	0	1	1	1	717	0	16	0	49593	0	10000	100	49756	49756	49756	49756	49756
10204	49755	372	0	0	0	49740	39558	25	10100	100	10000	100	10000	500	2370584	1	49	46675	49755	49755	48164	6	48459	10100	200	10008	200	49755	39447	1	1	10201	100	99	100	100	100	0	0	10000	0	0	0	1	1	1	717	0	16	0	49593	0	10000	100	49756	49756	49756	49756	49756
10204	49755	373	0	0	0	49740	39558	25	10100	100	10000	100	10000	500	2370584	1	49	46675	49755	49755	48164	6	48459	10100	200	10008	200	49755	39447	1	1	10201	100	99	100	100	100	0	0	10000	0	0	0	1	1	1	717	0	16	0	49593	0	10000	100	49756	49756	49756	49756	49756
10204	49755	373	0	0	159	49740	39558	25	10100	100	10000	100	10000	500	2370584	1	49	46675	49755	49755	48164	6	48459	10100	200	10008	200	49755	39447	1	1	10201	100	99	100	100	100	0	0	10000	0	0	0	1	1	1	717	0	16	0	49593	0	10000	100	49756	49756	49756	49756	49756

1000 unrolls and 10 iterations

Result (median cycles for code): 4.9755

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	49755	372	0	0	0	49740	39558	25	10010	10	10000	10	10000	50	2370584	0	49	46675	50300	49755	48207	3	48485	10010	20	10128	20	49755	49755	3	1	10021	10	9	10	10	10	10000	1	11550	0	640	2	16	2	3	49586	10000	10	49756	49756	49756	49756	49756
10024	49755	373	0	0	0	49740	39558	25	10010	10	10000	10	10000	50	2370584	0	49	46675	49755	49755	48179	3	48485	10010	20	10000	20	49755	49755	1	1	10021	10	9	10	10	10	10000	0	3	0	698	2	16	2	2	49586	10000	10	49756	49756	49756	49756	49756
10024	49755	373	0	0	12	49740	39558	25	10010	10	10000	10	10000	50	2370584	1	49	46675	49755	49755	48179	3	48485	10010	20	10000	20	49755	49755	1	1	10021	10	9	10	10	10	10000	1	0	0	640	2	16	3	2	49650	10000	10	49756	49756	49756	49756	49756
10024	49755	373	1	0	0	49740	39558	1077	10010	10	10000	10	10000	50	2370584	0	49	46675	49755	49755	48179	3	48485	10010	20	10000	20	49755	51884	1	1	10021	10	9	10	10	10	10000	0	3	0	640	2	16	2	2	49586	10000	10	49756	49756	49756	49756	49756
10024	49755	372	0	0	0	49740	39558	25	10010	10	10000	10	10000	50	2370584	0	49	46675	49755	49755	48179	3	48485	10010	20	10000	20	49755	49755	1	1	10021	10	9	10	10	10	10000	0	0	0	640	2	16	2	2	49586	10000	10	49756	49756	49756	49756	49756
10024	49755	372	0	1	0	49740	39558	25	10010	10	10000	10	10000	50	2370584	0	49	47228	49755	49755	48179	3	48485	10010	20	10000	20	49755	49755	1	1	10021	10	9	10	10	10	10000	0	0	0	640	2	16	2	2	49586	10000	10	49756	49756	49756	49756	49756
10024	49755	372	0	0	21	49740	39558	25	10010	10	10000	10	10000	50	2370584	0	49	46675	49755	49755	48179	3	48485	10010	20	10000	20	49755	49755	1	1	10021	10	9	10	10	10	10000	0	0	0	640	2	16	2	2	49586	10000	10	49756	49756	49756	49756	49756
10024	49755	372	0	0	0	49740	39558	25	10010	10	10000	10	10000	50	2370584	1	49	46675	49755	49755	48179	3	48485	10010	20	10000	20	49755	49755	1	1	10021	10	9	10	10	10	10000	0	15388	2	640	2	16	2	3	49586	10000	10	49756	49756	49756	49756	49756
10024	49755	373	0	0	0	49740	39558	25	10010	10	10000	10	10000	50	2370584	0	49	46675	49755	49755	48179	3	48485	10010	20	10000	20	49755	49755	1	1	10021	10	9	10	10	10	10000	0	0	0	640	2	16	2	2	49586	10000	10	49756	49756	49756	49756	49756
10024	51388	372	0	0	0	49740	39558	25	10010	10	10000	10	10000	50	2370584	1	49	46675	51413	49755	48179	3	48485	10010	20	10000	20	49755	49755	1	1	10021	10	9	10	10	10	10000	0	0	0	640	2	16	2	2	49586	10000	10	49756	49756	51918	49756	49756

CLREX

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations