Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADDS (shifted immediate, 64-bit)

Test 1: uops

Code:

  adds x0, x0, #3, lsl #12
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004103580619172510001000100062250010351035805388210001000100010354011100110000073127119931000100010361036103610361036
1004103583619172510001000100062250010351035805388210001000100010354011100110000073127119931000100010361036103610361036
1004103570619172510001000100062250010351035805388210001000100010354011100110000073127119931000100010361036103610361036
1004103580619172510001000100062250010351035805388210001000100010354011100110000073127119931000100010361036103610361036
1004103570619172510001000100062250010351035805388210001000100010354011100110000073127119931000100010361036103610361036
1004103570619172510001000100062250110351035805388210001000100010354011100110000073127119931000100010361036103610361036
1004103580619172510001000100062250010351035805388210001000100010354011100110000073127119931000100010361036103610361036
1004103570619172510001000100062250010351035805388210001000100010354011100110000073127119931000100010361036103610361036
1004103579619172510001000100062250110351035805388210001000100010354011100110000073127119931000100010361036103610361036
1004103570619172510001000100062250110351035805388210001000100010354011100110000073127119931000100010361036103610361036

Test 2: Latency 1->2

Code:

  adds x0, x0, #3, lsl #12
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03193f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357508299202510100101001010064715214969551003510035865638732101001020010200100354011102011009910010100100000071012711999510000101001003610036100361003610036
10204100357506199202510100101001010064715214969551003510035865638732101001020010200100354011102011009910010100100000071012711999510000101001003610070100361003610036
10204100357506199202510100101001010064715214969551003510035865638732101001020010200100354011102011009910010100100000071012711999510000101001003610036100361003610036
10204100357506199202510100101001010064715214969551003510035865638732101001020010200100354011102011009910010100100000071012711999510000101001003610036100361003610036
10204100357506199202510100101001010064715214969551003510035865638732101001020010200100354011102011009910010100100010071012711999510000101001003610036100361003610036
10204100357506199202510100101001010064715214969551003510035865638732101001020010200100354011102011009910010100100000071012711999510000101001003610036100361003610036
10204100357506199202510100101001010064715214969551003510035865638732101001020010200100354011102011009910010100100000071012711999510000101001003610036100361003610036
10204100357506199202510100101001010064715204969551003510035865638732101001020010200100354011102011009910010100100000071012711999510000101001003610036100361003610036
10204100357506199202510100101001010064715214969551003510035865638732101001020010200100354011102011009910010100100010071012711999510000101001003610036100361003610036
10204100357506199202510100101001010064715214969551003510035865638732101001020010200100354011102011009910010100100000071012711999510000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03093f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002410035750105991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036
1002410035750145991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036
100241003575061991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036
100241003575061991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036
100241003575061991825100101001010010647246149695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036
1002410035750145991825100101001010010647246149695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036
100241003575061991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036
100241003575061991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036
100241003575061991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036
100241003575061991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  adds x0, x1, #3, lsl #12
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9facc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020420035150061199302520100201002011212972331491695520035200351742571748520112202242022420035641120201100991002010010100001111319162001220000201002003620036200362003620036
2020420035150061199302520100201002011212972331491695520035200351742581748520112202242022420035641120201100991002010010100001111320162001220000201002003620036200362003620036
2020420035150061199302520100201002011212972331491695520035200351742571748620112202242022420035641120201100991002010010100001111320162001220000201002003620036200362003620036
2020420035150061199302520100201002011212972331491695520035200351742581748520112202242022420035641120201100991002010010100001111320162001220000201002003620036200362003620036
2020420035150061199302520100201002011212972330491695520035200351742581748620112202242022420035641120201100991002010010100001111320162001220000201002003620036200362003620036
2020420035150061199302520100201002011212972331491695520035200351742571748620112202242022420035641120201100991002010010100001111320162001220000201002003620036200362003620036
2020420035150082199302520100201002011212972331491695520035200351742581748520112202242022420035641120201100991002010010100001111320162001220000201002003620036200362003620036
2020420035150061199302520100201002011212972331491695520035200351742581748520112202242022420035641120201100991002010010100001111319162001220000201002003620036200362003620036
2020420035150061199302520100201002011212972330491695520035200351742581748520112202242022420035641120201100991002010010100001111320162001220000201002003620036200362003620036
2020420035149061199302520100201002011212972330491695520035200351742581748520112202242022420035641120201100991002010010100001111320162001220000201002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200242003515000006119918252001020010200101297247149169552003520035174283175042001020020200202003564112002110910200101001000001270127111999520000200102003620036200362003620036
200242003515000006119918252001020010200101297247149169552003520035174283175042001020020200202003564112002110910200101001000001270127111999520000200102003620036200362003620036
200242003515000006119918252001020010200101297247149170012003520035174283175042001020020200202003564112002110910200101001000001288127111999520000200102003620036200362003620036
20024200791500001716119918252001020010200101297247149169552003520035174283175042001020020200202003564112002110910200101001000001270127112002920000200102003620036200362003620081
20024200351500010107819918252001020010200101297247149169552003520035174283175042001020020200202003564112002110910200101001000001270127111999520000200102003620036200362003620036
200242003515000006119918252001020010200101297247149169552003520035174283175042001020020200202003564112002110910200101001010001270127111999520000200102003620036200362003620036
200242003515000006119918252001020010200101297247149169552003520035174283175042001020020200202003564112002110910200101001000001270127111999520000200102003620036200362003620036
2002420035150000126119918252001020010200101297247149169552003520035174283175042001020020200202003564112002110910200101001000001270127211999520000200102003620036200362003620036
20024200351500000611991825200102001020092129724714916955200812003517428317504200102002020020200356411200211091020010100100083811270127121999520000200102003620036200362003620036
200242003515011106119918252001020010200101297247149169552003520035174283175042001020020200202003564112002110910200101001000001270127111999520000200102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  adds x0, x8, #3, lsl #12
  adds x1, x8, #3, lsl #12
  adds x2, x8, #3, lsl #12
  adds x3, x8, #3, lsl #12
  adds x4, x8, #3, lsl #12
  adds x5, x8, #3, lsl #12
  adds x6, x8, #3, lsl #12
  adds x7, x8, #3, lsl #12
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020426763200003525801008010080100400500149236552673526735166723166908010080200802002673539118020110099100801001000005110119112673180000801002673626736267362673626736
8020426735200003525801008010080100400500149236552673526735166723166908010080200802002673539118020110099100801001000005110119112673180000801002673626736267362673626736
8020426735200003525801008010080100400500149236552673526735166723166908010080200802002673539118020110099100801001000005110119112673180000801002673626736267362673626736
8020426735200003525801008010080100400500049236552673526735166723166908010080200802002673539118020110099100801001000005110119112673180000801002673626736267362673626736
802042673520005343525801008010080100400500049236552673526735166723166908010080200802002673539118020110099100801001000005110119112673180000801002673626736267362673626736
8020426735200003525801008010080100400500049236552673526735166723166908010080200802002673539118020110099100801001000005110119112673180000801002673626736267362673626736
8020426735200003525801008010080100400500049236552673526735166723166908010080200802002673539118020110099100801001000005110119112673180000801002673626736267362673626736
8020426735201003525801008010080100400500049236552673526735166723166908010080200802002673539118020110099100801001000005110119112673180000801002673626736267362673626736
8020426735200003525801008010080100400500149236552673526735166723166908010080200802002673539118020110099100801001000005110119112673180000801002673626736267862673626736
8020426735200003525801008010080100400500149236552673526735166723166908010080200802002673539118020110099100801001000005110119112673180000801002673626736267362673626736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd2d5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024267112000035258001080010800104000500149236252670526705166653166838001080020800202670539118002110910800101005020091805162670280000800102670626706267062670626706
80024267052000035258001080010800104000500149236252670526705166653166838001080020800202670539118002110910800101005020061805162670280000800102670626706267062670626706
80024267052000035258001080010800104000500049236252670526705166653166838001080020800202670539118002110910800101005020061805152670280000800102670626706267062670626706
8002426705200003525800108001080010400050014923625267052670516665316683800108002080020267053911800211091080010100502001618016162670280000800102670626706267062670626706
800242670520000352580010800108001040005001492362526705267051667331668380010800208002026705391180021109108001010050200161801562670280000800102670626706267062670626706
80024267052001935258001080010800104000500049236252670526705166653166838001080020800202670539118002110910800101005020061806152670280000800102670626706267062670626706
80024267052000035258001080010800104000500049236252670526705166653166838001080020800202670539118002110910800101005020071805162670280000800102670626706267062670626706
800242670520000352580010800108001040005001492362526705267051666531668380010800208002026705391180021109108001010050200161801652670280000800102670626706267062670626706
800242670520000352580010800108001040005001492362526705267051666531668380010800208002026705391180021109108001010050200161801652670280000800102670626706267062670626706
80024267052000022525800108001080010400050004923625267052670516665316683800108002080020267053911800211091080010100502001618016162670280000800102670626706267062670626706