Firestorm: STR (post-index, 32-bit) measurements

Code:

  str w0, [x6], #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	20	22	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1040	8	1	1	1	1	6	14	12	0	12	0	1025	24	2	3	7	25	2000	1000	1000	1000	1000	50754	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1031	7	56	7	21	1008	0	0	34	22	11	1000	7	56	7	1	73	5	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	1	0	0	13	22	1	10	0	1025	0	0	16	4	25	2000	1000	1000	1000	1000	50754	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1038	7	48	6	23	1008	0	0	10	14	10	1028	7	64	7	2	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	1	1	6	11	16	0	13	16	1025	0	11	1	6	25	2000	1000	1000	1000	1000	50754	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1037	9	97	7	30	1008	1	0	24	6	10	1010	7	72	7	1	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	0	1	6	13	18	1	1	0	1025	26	1	6	6	25	2000	1000	1000	1000	1000	50754	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1008	9	72	0	34	1007	1	2	33	20	7	1016	7	64	7	2	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	0	1	0	12	14	2	11	4	1025	18	1	12	6	25	2000	1000	1000	1000	1000	50754	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1036	9	72	3	15	1008	2	2	30	16	13	1024	8	72	7	1	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	1	6	13	12	0	8	12	1025	26	2	0	2	25	2000	1000	1000	1000	1000	50754	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1039	8	89	0	15	1022	2	2	0	0	10	1028	7	52	7	0	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	1	1	1	1	0	12	12	0	1	0	1025	18	1	0	4	25	2000	1000	1000	1000	1000	50754	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1037	8	72	7	30	1018	0	0	18	12	10	1024	8	52	7	1	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	1	6	12	22	2	5	12	1025	14	3	2	4	25	2000	1000	1000	1000	1000	50762	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1022	7	73	6	22	1007	2	0	34	18	7	1031	8	52	7	0	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	0	1	12	13	0	0	5	0	1025	20	0	4	4	25	2000	1000	1000	1000	1000	50746	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1041	8	112	9	27	1007	1	0	26	16	13	1000	7	88	7	0	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	1	1	1	0	0	12	24	1	14	0	1025	22	9	0	5	25	2000	1000	1000	1000	1000	50746	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1027	9	72	5	32	1009	1	1	12	0	10	1013	8	52	7	1	73	3	16	3	3	1037	1000	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 2->2

Code:

  str w0, [x6], #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	23	29	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10209	10040	78	3	4	4	0	0	2355	120	812	1	0	816	93	0	120	10025	784	119	81	93	25	20100	10100	10000	10100	10000	521957	468824	0	0	49	6960	10040	10041	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10978	35	1503	367	0	677	10290	308	0	922	42	980	10948	45	1303	35	0	710	1	17	1	1	10037	10000	0	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	77	5	0	0	0	0	2124	125	827	1	0	808	69	0	112	10025	794	104	90	56	25	20100	10100	10000	10100	10000	522039	468824	1	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10944	28	1506	359	0	678	10289	322	4	956	38	882	10957	38	1285	28	0	729	1	25	2	1	10077	10032	1	0	10000	10100	10092	10092	10092	10145	10092
10204	10090	79	4	0	0	1	1	2466	207	873	1	0	776	86	0	156	10077	795	142	98	59	45	20158	10130	10025	10198	10070	521296	469939	0	0	49	7012	10196	10091	8693	7	8781	20268	204	10078	202	20156	10092	122	3	1	10201	100	99	100	10000	100	10000	100	10978	21	1538	423	0	655	10298	291	0	948	20	1609	10949	25	1340	14	0	727	2	34	3	1	10078	10045	1	0	10000	10100	10041	10041	10091	10041	10041
10204	10040	81	2	0	0	0	0	2394	92	823	1	0	768	84	1	96	10025	811	115	78	46	25	20100	10100	10000	10100	10000	522139	468824	0	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10924	16	1443	365	0	697	10272	309	2	934	34	933	10950	27	1260	14	2	710	1	17	1	1	10037	10000	3	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	77	2	0	0	0	0	2586	111	852	1	0	752	74	0	124	10025	807	106	103	41	25	20100	10100	10000	10100	10000	522095	468826	1	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10960	14	1442	370	0	675	10268	303	0	928	36	881	10970	26	1353	14	0	710	1	17	1	1	10037	10000	0	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	78	2	0	0	0	0	2373	93	864	1	0	776	90	2	100	10025	834	114	92	49	25	20100	10100	10000	10100	10000	522061	468824	1	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10912	14	1500	369	0	684	10278	300	4	938	42	932	10938	25	1330	14	2	710	1	17	1	1	10037	10000	1	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	78	2	2	0	0	0	2277	92	836	1	0	800	81	1	164	10025	819	92	103	50	25	20100	10100	10000	10100	10000	522063	468824	0	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10942	14	1484	363	0	695	10277	299	0	934	42	979	10952	22	1363	14	0	710	1	17	1	1	10037	10000	2	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	78	2	2	0	0	0	2466	89	843	1	0	760	76	0	116	10025	796	117	124	52	25	20100	10100	10000	10100	10000	522017	468824	0	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10952	14	1528	399	0	662	10282	294	0	930	32	985	10954	27	1275	14	0	710	1	17	1	1	10037	10000	1	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	2	2	2	0	0	2328	95	833	1	0	784	82	0	116	10025	821	105	96	55	25	20100	10100	10000	10100	10000	522063	468824	1	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10954	16	1488	417	0	704	10267	324	0	938	56	894	10957	30	1345	14	2	710	1	17	1	1	10037	10000	3	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	2	2	0	0	0	2187	84	853	1	0	744	81	0	116	10025	812	115	127	47	25	20100	10100	10000	10100	10000	522099	468824	0	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10956	12	1429	407	0	663	10274	293	0	902	34	897	10932	25	1351	14	2	710	1	17	1	1	10037	10000	2	0	10000	10100	10041	10041	10041	10041	10041

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10029	10040	75	3	3	3	3	2133	89	798	1	760	73	0	164	10025	778	97	97	34	25	20010	10010	10000	10010	10000	520923	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10927	21	1279	350	2	666	10287	255	0	858	32	861	10900	32	1066	21	0	640	3	16	3	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	76	2	0	0	0	2139	100	836	1	352	104	0	96	10025	800	63	78	44	25	20010	10010	10000	10010	10000	521025	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10884	23	1480	387	0	649	10269	254	0	882	40	882	10896	23	1105	14	0	640	4	16	3	3	10037	10000	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	0	0	2118	92	777	1	760	82	2	168	10025	785	32	70	33	25	20010	10010	10000	10010	10000	521089	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10910	7	1214	333	0	666	10264	264	0	912	32	748	10946	14	1045	7	2	640	4	16	3	3	10037	10000	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	1	0	0	2154	71	795	1	744	73	0	164	10025	786	39	54	38	25	20010	10010	10000	10010	10000	521113	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	2	1	10021	10	9	10	10000	10	10000	10	10929	8	1310	399	0	670	10263	264	0	916	38	833	10877	20	1138	7	0	640	4	16	4	4	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	1	0	0	2346	90	817	1	752	87	0	116	10025	782	90	85	16	25	20010	10010	10000	10010	10000	521121	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10925	8	1405	375	0	652	10273	262	0	902	36	802	10932	18	1085	7	1	640	4	16	4	3	10037	10000	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	1	0	0	2175	89	818	1	752	76	1	112	10025	797	72	65	38	25	20010	10010	10000	10010	10000	521073	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10921	7	1367	384	0	704	10283	272	0	906	46	777	10920	17	1247	7	0	640	3	16	4	4	10037	10000	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	0	0	1	2187	85	804	1	696	77	0	164	10025	776	102	58	52	25	20010	10010	10000	10010	10000	521057	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10873	8	1309	401	0	650	10242	251	0	854	36	767	10912	16	1146	7	0	640	4	16	4	4	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	0	0	1	1932	91	787	1	744	77	0	116	10025	792	76	53	43	25	20010	10010	10000	10010	10000	521105	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10877	7	1338	378	0	678	10266	278	0	884	32	738	10932	15	1105	7	2	640	4	16	4	4	10037	10000	25	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	0	0	0	1986	82	820	1	760	79	0	108	10025	790	71	63	41	25	20010	10010	10000	10010	10000	521073	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10903	7	1299	409	0	678	10265	283	0	902	32	899	10932	15	997	7	1	640	4	16	4	4	10037	10000	12	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	0	1	0	2019	78	827	1	736	76	0	112	10025	769	48	61	35	25	20010	10010	10000	10010	10000	521097	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10905	8	1221	357	0	676	10258	270	0	862	36	762	10876	20	1153	7	1	640	4	16	3	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041

Test 3: throughput

Count: 8

Code:

  str w0, [x6], #8
  str w0, [x7], #8
  str w0, [x8], #8
  str w0, [x9], #8
  str w0, [x10], #8
  str w0, [x11], #8
  str w0, [x12], #8
  str w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80209	40577	302	4	0	4	0	0	2037	390	815	1	712	109	144	40437	782	1900	1887	106	25	160756	81991	80006	80100	80000	417802	1859191	0	1971	49	37373	40459	40465	30343	3	30392	160100	200	80000	200	160000	40434	75	1	1	80201	100	99	100	80000	100	80000	100	80991	41	4353	537	13	882	80301	306	0	919	44	1359	81149	277	4455	41	0	0	5110	13	16	11	11	40514	80947	80000	80100	40457	40456	40488	40427	40468
80204	40424	303	2	0	0	0	0	1746	386	820	1	720	107	144	40451	799	1730	1604	105	25	160683	80672	80005	80100	80000	401313	1858844	0	384	49	37369	40427	40443	30323	3	30486	160100	200	80000	200	160240	40497	85	1	1	80201	100	99	100	80000	100	80000	100	80926	35	4446	481	19	881	80269	286	0	896	74	1120	81136	250	4238	22	0	0	5110	12	16	11	11	40423	80714	80000	80100	40455	40534	40394	40465	40451
80204	40444	303	2	0	0	0	0	2067	385	822	1	744	104	100	40457	787	2058	1938	115	25	160720	82755	80000	80100	80000	403414	1859204	0	329	49	37411	40457	40516	30391	3	30391	160100	200	80000	200	160000	40464	91	1	1	80201	100	99	100	80000	100	80000	100	80952	41	4423	521	16	952	80263	307	0	924	52	1201	81182	254	4596	26	0	0	5110	11	16	11	11	40455	82160	80000	80100	40513	40422	40433	40444	40483
80204	40490	303	3	3	0	0	0	2040	419	841	1	800	114	144	40478	807	2007	1966	122	25	160517	87634	80000	80100	80000	402536	1859600	0	2683	49	37321	40526	40418	30309	3	30511	160100	200	80000	200	160000	40446	75	1	1	80201	100	99	100	80000	100	80000	100	80900	26	4213	515	8	890	80280	260	3	902	70	1255	81185	274	4084	41	0	0	5110	13	16	10	12	40502	82304	80000	80100	40459	40417	40379	40581	40378
80204	40395	302	2	2	2	0	0	1905	358	799	1	728	113	156	40427	798	1835	2196	104	25	161520	80301	80001	80100	80000	410774	1858576	0	362	49	37300	40338	40387	30393	3	30361	160100	200	80000	200	160000	40439	75	1	1	80201	100	99	100	80000	100	80000	100	80931	13	4530	513	9	895	80269	280	2	917	28	1123	81172	267	4561	28	0	0	5110	10	17	13	12	40445	80963	80000	80100	40474	40370	40400	40442	40443
80204	40424	302	1	1	0	0	0	1851	349	809	1	712	109	96	40356	802	1797	1918	108	25	160856	80793	80003	80100	80000	410411	1860520	0	151	49	37377	40474	40390	30370	3	30357	160100	200	80000	200	160000	40388	81	1	1	80201	100	99	100	80000	100	80000	100	80930	15	4219	505	9	909	80278	268	0	928	44	1263	81179	284	3819	27	0	0	5110	13	16	13	12	40438	84437	80000	80100	40453	40418	40441	40462	40365
80204	40442	303	1	1	0	0	0	2001	382	834	1	704	129	92	40429	796	1900	2002	122	25	160923	80947	80001	80100	80000	418725	1859472	0	1553	49	37312	40425	40374	30438	3	30347	160100	200	80000	200	160000	40468	85	1	1	80201	100	99	100	80000	100	80000	100	80930	25	4279	481	22	863	80249	279	0	900	42	1123	81185	272	4285	13	0	0	5110	11	16	10	13	40430	80375	80000	80100	40434	40438	40454	40530	40370
80204	40390	303	1	1	0	0	0	1953	402	807	1	712	112	128	40422	831	1817	2093	128	25	160450	83564	80000	80100	80000	403978	1857932	0	273	49	37387	40409	40436	30311	3	30393	160100	200	80000	200	160000	40466	75	1	1	80201	100	99	100	80000	100	80000	100	80914	28	4486	483	6	931	80270	280	0	920	82	1308	81143	277	4045	38	6	0	5110	11	16	10	13	40444	84555	80000	80100	40440	40539	40484	40410	40455
80204	40447	303	2	0	0	0	0	1836	370	791	1	768	102	112	40504	795	2169	1927	113	25	164897	80513	80000	80100	80000	402632	1863262	0	333	49	37365	40461	40476	30259	3	30391	160100	200	80000	200	160000	40472	75	1	1	80201	100	99	100	80000	100	80000	100	80915	28	4090	483	4	903	80432	259	8	954	48	2028	81138	267	4352	42	0	0	5110	11	17	12	13	40487	85356	80000	80100	40469	40439	40487	40469	40446
80205	40498	303	3	0	0	0	0	2094	356	821	1	720	123	132	40505	793	1782	2084	116	25	161239	80667	80000	80100	80000	411113	1860288	0	553	49	37349	40493	40478	30310	3	30387	160100	200	80000	200	160000	40453	92	1	1	80201	100	99	100	80000	100	80000	100	81280	31	4382	492	165	881	80628	282	0	907	48	4298	81519	247	3866	27	6	0	5110	10	17	11	13	40395	80761	80000	80100	40440	40475	40472	40487	40447

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80029	40637	302	0	0	0	0	0	1947	311	851	2	432	103	256	40393	806	1710	1856	130	25	167181	82272	80000	80010	80000	420001	1853632	0	0	180	49	37240	0	40329	40489	30266	3	30293	160010	20	80000	20	160000	40392	76	1	1	80021	10	9	10	80000	10	80000	10	80879	0	4049	526	6	883	80242	286	0	885	64	1222	81175	225	4481	0	0	0	5020	0	0	4	16	0	4	4	2	40396	80371	0	80000	80010	40391	40497	40378	40414	40339
80024	40425	302	0	0	0	0	0	1806	279	818	2	512	106	276	40390	788	1907	1914	157	25	160289	80572	80000	80010	80000	401208	1854832	0	0	232	49	37350	0	40451	40480	30316	3	30395	160010	20	80000	20	160000	40389	75	1	1	80021	10	9	10	80000	10	80000	10	80918	0	4699	513	5	901	80218	296	0	937	98	1125	81128	215	3859	0	0	0	5020	0	0	3	16	0	4	5	3	40402	80312	0	80000	80010	40309	40330	40410	40433	40427
80024	40347	302	0	0	0	0	0	1845	304	842	2	552	92	240	40381	773	1803	1986	146	25	160383	80436	80000	80010	80000	413089	1862440	0	0	136	49	37377	0	40436	40442	30464	3	30368	160010	20	80000	20	160000	40404	75	1	1	80021	10	9	10	80000	10	80000	10	80857	0	4481	506	4	874	80256	264	0	861	72	1156	81115	234	4277	0	0	0	5020	0	0	3	16	0	4	4	4	40380	87742	0	80000	80010	40415	40379	40409	40359	40334
80024	40502	302	1	1	1	1	0	1863	356	784	2	504	98	240	40420	815	1990	1697	128	25	162133	80650	80002	80010	80000	409881	1856944	0	0	1375	49	37273	0	40415	40403	30340	3	30452	160010	20	80000	20	160000	40401	76	1	1	80021	10	9	10	80000	10	80000	10	80874	13	4059	553	6	867	80229	317	1	874	148	1117	81086	238	4599	13	0	0	5020	0	0	3	16	0	4	3	2	40416	80387	0	80000	80010	40414	40396	40550	40416	40296
80024	40400	302	1	0	1	1	0	2067	305	803	2	432	95	256	40512	785	1796	1755	107	25	160337	86697	80000	80010	80000	414756	1850032	0	0	253	49	37351	0	40347	40332	30343	3	30347	160010	20	80000	20	160000	40309	75	1	1	80021	10	9	10	80000	10	80000	10	80938	13	4694	541	8	880	80254	277	0	906	52	1158	81176	228	4348	13	0	0	5020	0	0	3	17	0	4	3	3	40371	80570	0	80000	80010	40407	40431	40377	40374	40443
80024	40482	303	1	0	0	0	0	1959	275	839	2	528	127	200	40346	769	1942	1841	105	25	160545	80286	80000	80010	80000	401487	1856608	0	0	143	49	37306	0	40441	40373	30382	3	30343	160010	20	80000	20	160000	40354	75	1	1	80021	10	9	10	80000	10	80000	10	80847	14	4214	521	1	855	80274	283	2	891	156	1122	81124	248	4369	13	0	0	5020	0	0	3	16	0	4	1	3	40361	80564	0	80000	80010	40470	40393	40397	40373	40416
80024	40366	303	2	0	0	1	0	1938	350	790	2	496	108	244	40495	790	1785	1647	123	25	160625	80332	80000	80010	80000	405961	1855648	0	0	753	49	37361	0	40383	40431	30327	3	30500	160010	20	80000	20	160000	40332	76	1	1	80021	10	9	10	80000	10	80000	10	80917	12	4837	559	6	853	80229	283	0	880	80	1099	81133	255	4768	14	0	0	5020	0	0	2	17	1	4	2	3	40342	80583	0	80000	80010	40374	40407	40389	40379	40418
80024	40373	302	1	0	1	0	0	1881	279	818	2	488	125	360	40376	774	1877	1901	142	25	160789	84021	80000	80010	80000	400561	1855864	0	0	196	49	37260	0	40371	40387	30327	3	30326	160010	20	80000	20	160240	40341	75	1	1	80021	10	9	10	80000	10	80000	10	80867	15	4331	504	11	864	80239	256	0	912	66	1137	81110	261	4234	13	1	0	5020	0	0	3	18	0	4	2	7	40308	82539	0	80000	80010	40376	40367	40371	40409	40459
80024	40411	303	1	0	0	1	0	1818	296	866	2	440	106	228	40307	788	1744	1916	138	25	160183	80766	80000	80010	80000	415869	1855768	0	0	1957	49	37275	0	40441	40342	30338	3	30300	160252	20	80000	20	160000	40495	76	1	1	80021	10	9	10	80000	10	80000	10	80894	14	4002	547	5	869	80225	267	0	951	108	1121	81100	248	4283	13	2	0	5020	0	0	2	18	0	4	3	5	40399	84716	0	80000	80010	40323	40383	40477	40397	40320
80024	40380	303	1	0	0	0	0	1791	297	794	2	504	104	216	40373	779	1967	1957	142	25	160531	80519	80007	80010	80000	414359	1855816	0	0	205	49	37321	0	40473	40560	30405	3	30454	160010	20	80000	20	160000	40492	76	1	1	80021	10	9	10	80000	10	80000	10	80886	15	4130	515	4	870	80247	283	0	881	92	1088	81126	247	5046	14	0	0	5020	0	0	3	18	0	4	5	2	40326	80643	0	80000	80010	40409	40384	40475	40385	40426

STR (post-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations