Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

EOR (register, lsl, 64-bit)

Test 1: uops

Code:

  eor x0, x0, x1, lsl #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004203515006110001735252000200010003257012035203515753184210001000200020354211100110000731671117812000100020362036203620362036
1004203516006110001735252000200010003257002035203515753184210001000200020354211100110000731671117812000100020362036203620362036
1004203515096110001735252000200010003257012035203515753184210001000200020354211100110000731671117812000100020362036203620362036
1004203515006110001735252000200010003257002035203515753184210001000200020354211100110000731671117812000100020362036203620362036
1004203515006110001735252000200010003257012035203515753184210001000200020354211100110000731671117812000100020362036203620362036
1004203515006110001735252000200010003257012035203515753184210001000200020354211100110000731671117812000100020362036203620362036
1004203516006110001735252000200010003257002035203515753184210001000200020354211100110000731671117812000100020362036203620362036
1004203515008210001735252000200010003257012035203515753184210001000200020354211100110000731671117812000100020362036203620362036
1004203515008410001735252000200010003257012035203515753184210001000200020354211100110000731671117812000100020362036203620362036
10042035150126110001735252000200010003257002035203515753184210001000200020354211100110000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  eor x0, x0, x1, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)033a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020420035150082100001980325201002010010100185342049169550200352003518429318700101001020020200200354211102011009910010100100160710159111979120000101002003620036200362003620036
102042003515008410000198032520100201001010018534204916955020035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
102042003515006110000198032520100201001010018534204916955020035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
102042003515006110027197972520100201001010018531604916955020035200351843531870010125102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
102042003515006110000198032520100201001010018534204916955020035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
102042003515006110000197972520100201251010018534204916955020035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
102042003515006110000198032520100201001010018534204916955020035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
102042003515006110000198032520100201001010018534204916955020035200351842931870010100102002020020035421110201100991001010010000710159211979120000101002003620036200362003620036
1020420035150030710000198032520100201001010018534204916955020035200351842931870010125102002020020035441110201100991001010010000710159161979120000101002003620036200362003620036
102042003515006110000198032520100201001010018534204916955020035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)033f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351496110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640463651979220000100102003620036200362003620036
10024200351506110000197412520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640563651979220000100102003620036200362003620036
10024200351506110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640663551979220000100102003620036200362003620036
100242003515050010000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640579551979220000100102003620036200362003620036
10024200351506110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640563551979220000100102003620036200362003620036
10024200351506110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640563551979220000100102003620036200362003620036
10024200351506110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640563661979220000100102003620036200362003620036
10024200351506110000197432520010200101001018531014916955200352003518451318735100101002020020200354211100211091010010100000640463461979220000100102003620036200362003620036
10024200351506110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640563651979220000100102003620036200362003620036
10024200351506110000197432520010200101001018531014917000200352003518451318718100101002020020200354211100211091010010100000640663651979220000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  eor x0, x1, x0, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515001701000019803252010020100101001853424916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036
102042003515003231000019803252010020100101001853424916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036
102042003515002731000019803252010020100101001853424916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036
10204200351500821000019803252010020100101001853424916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036
102042003515004701000019803252010020100101001853424916955200352003518429318700101001020020200200354211102011009910010100100000735159111979120000101002003620036200362003620036
102042003515001471000019803252010020100101001853424916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036
102042003515002791000019803252010020100101001853424916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002007320174200362003620036
102042003515002791000019803252010020100101001853424916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036
102042003515001031000019803252010020100101001853424916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036
102042003515002801000019803252010020100101001853424916955200352003518429318700101001020020200200354211102011009910010100100149710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351500000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
10024200351500009611000019743252001020010100101853101491695520035200351845131871810010100202002020035841110021109101001010000640263221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853100491695520035200351845131871810010100202002020035421110021109101001010030640263221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010001640263221979220000100102003620036200792003620036
10024200351500000611000019743252001020010100101853100491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853101491695520035200351849631871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  eor x0, x8, x9, lsl #17
  eor x1, x8, x9, lsl #17
  eor x2, x8, x9, lsl #17
  eor x3, x8, x9, lsl #17
  eor x4, x8, x9, lsl #17
  eor x5, x8, x9, lsl #17
  eor x6, x8, x9, lsl #17
  eor x7, x8, x9, lsl #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204267712000000000145800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000000000051103221126717160000801002672626726267262672626726
80204267252010000000115800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000000000051101221126717160000801002672626726267262672626726
80204267252000000000353800002393925160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000000400051101221126717160000801002672626726267262672626726
80204267252000000000444800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000000000051101221126717160000801002672626726267262672626726
80204267252000000000170800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000300000051101221126717160000801002672626726267262672626726
8020426725200001000084800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000000000051101221126717160000801002672626726267262672626726
80204267252000000000509800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000000000051101221126717160000801002672626726267262672626726
80204267252000000000465800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000000000051101221126717160000801002672626726267262672626726
80204267252000000000405800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000000000051101221126717160000801002672626726267262672626726
80204267252000000000546800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000000000051101221126717160000801002672626726267262672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800242673420006180000212802516001016001080010163142149236312671126711166230316685800108002016002026711391180021109108001010050206394426704160000800102671226712267122671226712
8002426711200010380000212802516001016001080010163142049236312671126711166230316685800108002016002026711391180021109108001010050204226626704160000800102671226712267122671226712
800242671120096180000212802516001016001080010163142149236312671126711166230316685800108002016002026711391180021109108001010050204227726704160000800102671226712267122671226712
800242671120006180000212802516001016001080010163142049236312671126711166230316685800108002016002026711391180021109108001010050206223426704160000800102671226712267122671226712
80024267112001594380000212802516001016001080010163142149236312671126711166230316685800108002016002026711391180021109108001010050203223426704160000800102671226712267122671226712
800242671120006180000212802516001016001080010166346049236312671126711166230316685800108002016002026711391180021109108001010050206224726704160000800102671226712267122671226712
8002426711200032280000212802516001016001080010163142049236312671126711166230316685800108002016002026711391180021109108001010050209227626704160000800102671226712267122671226712
800242671120006180000212802516001016001080010163142149236312671126711166230316685800108002016002026711391180021109108001010050205224626704160000800102671226712267122671226712
800242671120006180000212802516001016001080010163142149236312671126711166230316685800108002016002026711391180021109108001010050204226626704160000800102671226712267122671226712
800242671120006180000212802516001016001080010163142049236312671126711166230316685800108002016002026711391180021109108001010050206227626704160000800102671226712267122671226712