Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
eor x0, x0, x1, lsl #17
mov x0, 1 mov x1, 2
(no loop instructions)
Retires: 1.000
Issues: 2.000
Integer unit issues: 2.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 1e | 3f | 4c | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int alu (97) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
1004 | 2035 | 15 | 0 | 0 | 61 | 1000 | 1735 | 25 | 2000 | 2000 | 1000 | 32570 | 1 | 2035 | 2035 | 1575 | 3 | 1842 | 1000 | 1000 | 2000 | 2035 | 42 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 67 | 1 | 1 | 1781 | 2000 | 1000 | 2036 | 2036 | 2036 | 2036 | 2036 |
1004 | 2035 | 16 | 0 | 0 | 61 | 1000 | 1735 | 25 | 2000 | 2000 | 1000 | 32570 | 0 | 2035 | 2035 | 1575 | 3 | 1842 | 1000 | 1000 | 2000 | 2035 | 42 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 67 | 1 | 1 | 1781 | 2000 | 1000 | 2036 | 2036 | 2036 | 2036 | 2036 |
1004 | 2035 | 15 | 0 | 9 | 61 | 1000 | 1735 | 25 | 2000 | 2000 | 1000 | 32570 | 1 | 2035 | 2035 | 1575 | 3 | 1842 | 1000 | 1000 | 2000 | 2035 | 42 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 67 | 1 | 1 | 1781 | 2000 | 1000 | 2036 | 2036 | 2036 | 2036 | 2036 |
1004 | 2035 | 15 | 0 | 0 | 61 | 1000 | 1735 | 25 | 2000 | 2000 | 1000 | 32570 | 0 | 2035 | 2035 | 1575 | 3 | 1842 | 1000 | 1000 | 2000 | 2035 | 42 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 67 | 1 | 1 | 1781 | 2000 | 1000 | 2036 | 2036 | 2036 | 2036 | 2036 |
1004 | 2035 | 15 | 0 | 0 | 61 | 1000 | 1735 | 25 | 2000 | 2000 | 1000 | 32570 | 1 | 2035 | 2035 | 1575 | 3 | 1842 | 1000 | 1000 | 2000 | 2035 | 42 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 67 | 1 | 1 | 1781 | 2000 | 1000 | 2036 | 2036 | 2036 | 2036 | 2036 |
1004 | 2035 | 15 | 0 | 0 | 61 | 1000 | 1735 | 25 | 2000 | 2000 | 1000 | 32570 | 1 | 2035 | 2035 | 1575 | 3 | 1842 | 1000 | 1000 | 2000 | 2035 | 42 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 67 | 1 | 1 | 1781 | 2000 | 1000 | 2036 | 2036 | 2036 | 2036 | 2036 |
1004 | 2035 | 16 | 0 | 0 | 61 | 1000 | 1735 | 25 | 2000 | 2000 | 1000 | 32570 | 0 | 2035 | 2035 | 1575 | 3 | 1842 | 1000 | 1000 | 2000 | 2035 | 42 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 67 | 1 | 1 | 1781 | 2000 | 1000 | 2036 | 2036 | 2036 | 2036 | 2036 |
1004 | 2035 | 15 | 0 | 0 | 82 | 1000 | 1735 | 25 | 2000 | 2000 | 1000 | 32570 | 1 | 2035 | 2035 | 1575 | 3 | 1842 | 1000 | 1000 | 2000 | 2035 | 42 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 67 | 1 | 1 | 1781 | 2000 | 1000 | 2036 | 2036 | 2036 | 2036 | 2036 |
1004 | 2035 | 15 | 0 | 0 | 84 | 1000 | 1735 | 25 | 2000 | 2000 | 1000 | 32570 | 1 | 2035 | 2035 | 1575 | 3 | 1842 | 1000 | 1000 | 2000 | 2035 | 42 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 67 | 1 | 1 | 1781 | 2000 | 1000 | 2036 | 2036 | 2036 | 2036 | 2036 |
1004 | 2035 | 15 | 0 | 12 | 61 | 1000 | 1735 | 25 | 2000 | 2000 | 1000 | 32570 | 0 | 2035 | 2035 | 1575 | 3 | 1842 | 1000 | 1000 | 2000 | 2035 | 42 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 67 | 1 | 1 | 1781 | 2000 | 1000 | 2036 | 2036 | 2036 | 2036 | 2036 |
Code:
eor x0, x0, x1, lsl #17
mov x0, 1 mov x1, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.0035
retire uop (01) | cycle (02) | 03 | 3a | 3f | 4c | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10204 | 20035 | 150 | 0 | 82 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 0 | 49 | 16955 | 0 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 16 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 84 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 0 | 49 | 16955 | 0 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 61 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 0 | 49 | 16955 | 0 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 61 | 10027 | 19797 | 25 | 20100 | 20100 | 10100 | 185316 | 0 | 49 | 16955 | 0 | 20035 | 20035 | 18435 | 3 | 18700 | 10125 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 61 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 0 | 49 | 16955 | 0 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 61 | 10000 | 19797 | 25 | 20100 | 20125 | 10100 | 185342 | 0 | 49 | 16955 | 0 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 61 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 0 | 49 | 16955 | 0 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 61 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 0 | 49 | 16955 | 0 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 59 | 2 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 307 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 0 | 49 | 16955 | 0 | 20035 | 20035 | 18429 | 3 | 18700 | 10125 | 10200 | 20200 | 20035 | 44 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 59 | 1 | 6 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 61 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 0 | 49 | 16955 | 0 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
Result (median cycles for code): 2.0035
retire uop (01) | cycle (02) | 03 | 3f | 4c | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | l1d cache writeback (a8) | ac | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10024 | 20035 | 149 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 0 | 640 | 4 | 63 | 6 | 5 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 61 | 10000 | 19741 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 0 | 640 | 5 | 63 | 6 | 5 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 0 | 640 | 6 | 63 | 5 | 5 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 500 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 0 | 640 | 5 | 79 | 5 | 5 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 0 | 640 | 5 | 63 | 5 | 5 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 0 | 640 | 5 | 63 | 5 | 5 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 0 | 640 | 5 | 63 | 6 | 6 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18735 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 0 | 640 | 4 | 63 | 4 | 6 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 0 | 640 | 5 | 63 | 6 | 5 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 17000 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 0 | 640 | 6 | 63 | 6 | 5 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
Code:
eor x0, x1, x0, lsl #17
mov x0, 1 mov x1, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.0035
retire uop (01) | cycle (02) | 03 | 1e | 3f | 4c | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | l1d cache writeback (a8) | a9 | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10204 | 20035 | 150 | 0 | 170 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 49 | 16955 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 323 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 49 | 16955 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 273 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 49 | 16955 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 82 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 49 | 16955 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 470 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 49 | 16955 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 0 | 735 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 147 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 49 | 16955 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 279 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 49 | 16955 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20073 | 20174 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 279 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 49 | 16955 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 103 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 49 | 16955 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 0 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
10204 | 20035 | 150 | 0 | 280 | 10000 | 19803 | 25 | 20100 | 20100 | 10100 | 185342 | 49 | 16955 | 20035 | 20035 | 18429 | 3 | 18700 | 10100 | 10200 | 20200 | 20035 | 42 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 1 | 4 | 9 | 710 | 1 | 59 | 1 | 1 | 19791 | 20000 | 10100 | 20036 | 20036 | 20036 | 20036 | 20036 |
Result (median cycles for code): 2.0035
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 1e | 3f | 4c | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | ld unit uop (a6) | ac | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10024 | 20035 | 150 | 0 | 0 | 0 | 0 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 2 | 63 | 2 | 2 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 0 | 0 | 0 | 0 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 2 | 63 | 2 | 2 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 0 | 0 | 0 | 0 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 2 | 63 | 2 | 2 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 0 | 0 | 0 | 9 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 84 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 2 | 63 | 2 | 2 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 0 | 0 | 0 | 0 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 0 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 3 | 0 | 640 | 2 | 63 | 2 | 2 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 0 | 0 | 0 | 0 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 2 | 63 | 2 | 2 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 0 | 0 | 0 | 0 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 2 | 63 | 2 | 2 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 0 | 0 | 0 | 0 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 1 | 640 | 2 | 63 | 2 | 2 | 19792 | 20000 | 10010 | 20036 | 20036 | 20079 | 20036 | 20036 |
10024 | 20035 | 150 | 0 | 0 | 0 | 0 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 0 | 49 | 16955 | 20035 | 20035 | 18451 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 2 | 63 | 2 | 2 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
10024 | 20035 | 150 | 0 | 0 | 0 | 0 | 61 | 10000 | 19743 | 25 | 20010 | 20010 | 10010 | 185310 | 1 | 49 | 16955 | 20035 | 20035 | 18496 | 3 | 18718 | 10010 | 10020 | 20020 | 20035 | 42 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 2 | 63 | 2 | 2 | 19792 | 20000 | 10010 | 20036 | 20036 | 20036 | 20036 | 20036 |
Count: 8
Code:
eor x0, x8, x9, lsl #17 eor x1, x8, x9, lsl #17 eor x2, x8, x9, lsl #17 eor x3, x8, x9, lsl #17 eor x4, x8, x9, lsl #17 eor x5, x8, x9, lsl #17 eor x6, x8, x9, lsl #17 eor x7, x8, x9, lsl #17
mov x8, 9 mov x9, 10
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.3341
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3a | 3f | 4c | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
80204 | 26771 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 145 | 80000 | 26094 | 25 | 160100 | 160100 | 80100 | 164318 | 1 | 49 | 23645 | 26725 | 26725 | 16615 | 3 | 16677 | 80100 | 80200 | 160200 | 26725 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 3 | 22 | 1 | 1 | 26717 | 160000 | 80100 | 26726 | 26726 | 26726 | 26726 | 26726 |
80204 | 26725 | 201 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 115 | 80000 | 26094 | 25 | 160100 | 160100 | 80100 | 164318 | 1 | 49 | 23645 | 26725 | 26725 | 16615 | 3 | 16677 | 80100 | 80200 | 160200 | 26725 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 22 | 1 | 1 | 26717 | 160000 | 80100 | 26726 | 26726 | 26726 | 26726 | 26726 |
80204 | 26725 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 353 | 80000 | 23939 | 25 | 160100 | 160100 | 80100 | 164318 | 1 | 49 | 23645 | 26725 | 26725 | 16615 | 3 | 16677 | 80100 | 80200 | 160200 | 26725 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 5110 | 1 | 22 | 1 | 1 | 26717 | 160000 | 80100 | 26726 | 26726 | 26726 | 26726 | 26726 |
80204 | 26725 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 444 | 80000 | 26094 | 25 | 160100 | 160100 | 80100 | 164318 | 1 | 49 | 23645 | 26725 | 26725 | 16615 | 3 | 16677 | 80100 | 80200 | 160200 | 26725 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 22 | 1 | 1 | 26717 | 160000 | 80100 | 26726 | 26726 | 26726 | 26726 | 26726 |
80204 | 26725 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 170 | 80000 | 26094 | 25 | 160100 | 160100 | 80100 | 164318 | 1 | 49 | 23645 | 26725 | 26725 | 16615 | 3 | 16677 | 80100 | 80200 | 160200 | 26725 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 22 | 1 | 1 | 26717 | 160000 | 80100 | 26726 | 26726 | 26726 | 26726 | 26726 |
80204 | 26725 | 200 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 84 | 80000 | 26094 | 25 | 160100 | 160100 | 80100 | 164318 | 1 | 49 | 23645 | 26725 | 26725 | 16615 | 3 | 16677 | 80100 | 80200 | 160200 | 26725 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 22 | 1 | 1 | 26717 | 160000 | 80100 | 26726 | 26726 | 26726 | 26726 | 26726 |
80204 | 26725 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 509 | 80000 | 26094 | 25 | 160100 | 160100 | 80100 | 164318 | 1 | 49 | 23645 | 26725 | 26725 | 16615 | 3 | 16677 | 80100 | 80200 | 160200 | 26725 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 22 | 1 | 1 | 26717 | 160000 | 80100 | 26726 | 26726 | 26726 | 26726 | 26726 |
80204 | 26725 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 465 | 80000 | 26094 | 25 | 160100 | 160100 | 80100 | 164318 | 1 | 49 | 23645 | 26725 | 26725 | 16615 | 3 | 16677 | 80100 | 80200 | 160200 | 26725 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 22 | 1 | 1 | 26717 | 160000 | 80100 | 26726 | 26726 | 26726 | 26726 | 26726 |
80204 | 26725 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 405 | 80000 | 26094 | 25 | 160100 | 160100 | 80100 | 164318 | 1 | 49 | 23645 | 26725 | 26725 | 16615 | 3 | 16677 | 80100 | 80200 | 160200 | 26725 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 22 | 1 | 1 | 26717 | 160000 | 80100 | 26726 | 26726 | 26726 | 26726 | 26726 |
80204 | 26725 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 546 | 80000 | 26094 | 25 | 160100 | 160100 | 80100 | 164318 | 1 | 49 | 23645 | 26725 | 26725 | 16615 | 3 | 16677 | 80100 | 80200 | 160200 | 26725 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 22 | 1 | 1 | 26717 | 160000 | 80100 | 26726 | 26726 | 26726 | 26726 | 26726 |
Result (median cycles for code divided by count): 0.3339
retire uop (01) | cycle (02) | 03 | 1e | 3f | 4c | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
80024 | 26734 | 200 | 0 | 61 | 80000 | 21280 | 25 | 160010 | 160010 | 80010 | 163142 | 1 | 49 | 23631 | 26711 | 26711 | 16623 | 0 | 3 | 16685 | 80010 | 80020 | 160020 | 26711 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 5020 | 6 | 39 | 4 | 4 | 26704 | 160000 | 80010 | 26712 | 26712 | 26712 | 26712 | 26712 |
80024 | 26711 | 200 | 0 | 103 | 80000 | 21280 | 25 | 160010 | 160010 | 80010 | 163142 | 0 | 49 | 23631 | 26711 | 26711 | 16623 | 0 | 3 | 16685 | 80010 | 80020 | 160020 | 26711 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 5020 | 4 | 22 | 6 | 6 | 26704 | 160000 | 80010 | 26712 | 26712 | 26712 | 26712 | 26712 |
80024 | 26711 | 200 | 9 | 61 | 80000 | 21280 | 25 | 160010 | 160010 | 80010 | 163142 | 1 | 49 | 23631 | 26711 | 26711 | 16623 | 0 | 3 | 16685 | 80010 | 80020 | 160020 | 26711 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 5020 | 4 | 22 | 7 | 7 | 26704 | 160000 | 80010 | 26712 | 26712 | 26712 | 26712 | 26712 |
80024 | 26711 | 200 | 0 | 61 | 80000 | 21280 | 25 | 160010 | 160010 | 80010 | 163142 | 0 | 49 | 23631 | 26711 | 26711 | 16623 | 0 | 3 | 16685 | 80010 | 80020 | 160020 | 26711 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 5020 | 6 | 22 | 3 | 4 | 26704 | 160000 | 80010 | 26712 | 26712 | 26712 | 26712 | 26712 |
80024 | 26711 | 200 | 15 | 943 | 80000 | 21280 | 25 | 160010 | 160010 | 80010 | 163142 | 1 | 49 | 23631 | 26711 | 26711 | 16623 | 0 | 3 | 16685 | 80010 | 80020 | 160020 | 26711 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 5020 | 3 | 22 | 3 | 4 | 26704 | 160000 | 80010 | 26712 | 26712 | 26712 | 26712 | 26712 |
80024 | 26711 | 200 | 0 | 61 | 80000 | 21280 | 25 | 160010 | 160010 | 80010 | 166346 | 0 | 49 | 23631 | 26711 | 26711 | 16623 | 0 | 3 | 16685 | 80010 | 80020 | 160020 | 26711 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 5020 | 6 | 22 | 4 | 7 | 26704 | 160000 | 80010 | 26712 | 26712 | 26712 | 26712 | 26712 |
80024 | 26711 | 200 | 0 | 322 | 80000 | 21280 | 25 | 160010 | 160010 | 80010 | 163142 | 0 | 49 | 23631 | 26711 | 26711 | 16623 | 0 | 3 | 16685 | 80010 | 80020 | 160020 | 26711 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 5020 | 9 | 22 | 7 | 6 | 26704 | 160000 | 80010 | 26712 | 26712 | 26712 | 26712 | 26712 |
80024 | 26711 | 200 | 0 | 61 | 80000 | 21280 | 25 | 160010 | 160010 | 80010 | 163142 | 1 | 49 | 23631 | 26711 | 26711 | 16623 | 0 | 3 | 16685 | 80010 | 80020 | 160020 | 26711 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 5020 | 5 | 22 | 4 | 6 | 26704 | 160000 | 80010 | 26712 | 26712 | 26712 | 26712 | 26712 |
80024 | 26711 | 200 | 0 | 61 | 80000 | 21280 | 25 | 160010 | 160010 | 80010 | 163142 | 1 | 49 | 23631 | 26711 | 26711 | 16623 | 0 | 3 | 16685 | 80010 | 80020 | 160020 | 26711 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 5020 | 4 | 22 | 6 | 6 | 26704 | 160000 | 80010 | 26712 | 26712 | 26712 | 26712 | 26712 |
80024 | 26711 | 200 | 0 | 61 | 80000 | 21280 | 25 | 160010 | 160010 | 80010 | 163142 | 0 | 49 | 23631 | 26711 | 26711 | 16623 | 0 | 3 | 16685 | 80010 | 80020 | 160020 | 26711 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 5020 | 6 | 22 | 7 | 6 | 26704 | 160000 | 80010 | 26712 | 26712 | 26712 | 26712 | 26712 |