Firestorm: MOVK (32-bit) measurements

Code:

  movk w0, #0x1234, lsl 16

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	0	0	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	0	0	0	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	0	0	0	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	0	0	0	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	0	0	0	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	0	0	0	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	0	0	0	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	0	0	0	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	453	0	82	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	0	0	0	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	0	0	0	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	156	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	1000	1035	41	1	1	1001	1000	0	0	0	0	0	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->1

Code:

  movk w0, #0x1234, lsl 16

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	12	0	97	9877	25	10100	10100	10117	87686	1	49	6955	10035	10035	8607	7	8734	10117	10240	10240	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	1	1	1	720	16	9965	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	0	12	0	61	9877	25	10100	10100	10117	87686	1	49	6955	10035	10035	8607	7	8734	10117	10240	10240	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	1	1	1	720	16	9965	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10117	87686	1	49	6955	10035	10035	8607	7	8734	10117	10240	10240	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	1	1	1	720	16	9965	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	30	0	61	9877	25	10100	10100	10117	87686	1	49	6955	10035	10035	8607	7	8734	10117	10240	10240	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	1	1	1	720	16	9965	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10117	87686	1	49	6955	10035	10035	8607	7	8734	10117	10240	10240	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	1	1	1	720	16	9965	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	3	0	61	9877	25	10100	10100	10117	87686	1	49	6955	10035	10035	8607	7	8734	10117	10407	10240	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	1	1	1	720	16	9965	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10117	87686	1	49	6955	10035	10035	8607	7	8734	10117	10240	10240	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	1	1	1	720	16	9965	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10117	87686	1	49	6955	10035	10035	8607	7	8734	10117	10240	10240	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	1	1	1	720	16	9965	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10117	87686	1	49	6955	10035	10035	8607	7	8734	10117	10240	10240	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	1	1	1	720	16	9965	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10117	87686	1	49	6955	10035	10035	8607	7	8734	10117	10240	10240	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	1	1	1	720	16	9965	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	42	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	72	0	61	9863	25	10033	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	3	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	10020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036

Test 3: throughput

Count: 8

Code:

  movk w0, #0x1234, lsl 16
  movk w1, #0x1234, lsl 16
  movk w2, #0x1234, lsl 16
  movk w3, #0x1234, lsl 16
  movk w4, #0x1234, lsl 16
  movk w5, #0x1234, lsl 16
  movk w6, #0x1234, lsl 16
  movk w7, #0x1234, lsl 16

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1674

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	13425	100	0	0	3	0	36	25	80100	80100	80100	543180	0	49	10312	13392	13392	3328	3	3347	80100	80200	80200	13392	39	1	1	80201	100	99	100	80100	100	0	5112	2	19	2	2	13389	80000	80100	13393	13393	13393	13393	13393
80204	13392	101	0	0	0	0	511	25	80100	80100	80100	543180	1	49	10312	13392	13392	3328	3	3347	80100	80200	80200	13392	39	1	1	80201	100	99	100	80100	100	0	5112	2	19	2	2	13389	80000	80100	13393	13393	13393	13393	13393
80204	13392	100	0	0	0	0	36	25	80100	80100	80100	543180	0	49	10312	13392	13392	3328	3	3347	80100	80200	80200	13392	39	1	1	80201	100	99	100	80100	100	0	5112	2	19	2	2	13389	80000	80100	13393	13393	13393	13393	13393
80204	13392	100	0	0	9	0	36	25	80100	80100	80100	543180	0	49	10312	13392	13392	3328	3	3347	80100	80200	80200	13392	39	1	1	80201	100	99	100	80100	100	0	5112	2	19	2	2	13389	80000	80100	13393	13393	13393	13393	13393
80204	13392	100	0	0	6	0	36	25	80100	80100	80100	543180	0	49	10312	13392	13392	3328	3	3347	80100	80200	80200	13392	39	1	1	80201	100	99	100	80100	100	0	5112	2	19	2	2	13389	80000	80100	13393	13393	13393	13393	13393
80204	13392	100	0	0	0	0	36	25	80100	80100	80100	543180	0	49	10312	13392	13392	3328	3	3347	80100	80200	80200	13392	39	1	1	80201	100	99	100	80100	100	0	5112	2	19	2	2	13389	80000	80100	13393	13393	13393	13393	13393
80204	13392	101	0	0	0	0	36	25	80100	80100	80100	543180	0	49	10312	13392	13392	3328	3	3347	80100	80200	80200	13392	39	1	1	80201	100	99	100	80100	100	0	5112	2	19	2	2	13389	80000	80100	13393	13393	13393	13393	13393
80204	13392	100	0	0	0	0	36	25	80100	80100	80100	543180	0	49	10312	13392	13392	3328	3	3347	80100	80200	80200	13392	39	1	1	80201	100	99	100	80100	100	0	5112	2	19	2	2	13389	80000	80100	13393	13393	13393	13393	13393
80204	13392	100	0	0	0	0	36	25	80100	80100	80100	543180	0	49	10312	13392	13392	3328	3	3347	80100	80200	80200	13392	39	1	1	80201	100	99	100	80100	100	0	5112	2	19	2	2	13389	80000	80100	13393	13393	13393	13393	13393
80204	13392	100	0	0	0	0	36	25	80100	80100	80100	543180	0	49	10312	13392	13392	3328	3	3347	80100	80200	80200	13392	39	1	1	80201	100	99	100	80100	100	0	5112	2	19	2	2	13389	80000	80100	13393	13393	13393	13393	13393

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	13390	100	0	9	0	36	25	80010	80010	80010	492052	1	49	10292	13372	13372	3330	3	3349	80010	80020	80020	13372	39	1	1	80021	10	9	10	80010	10	0	5020	3	19	2	2	13369	80000	80010	13373	13373	13373	13373	13373
80024	13372	100	0	0	0	36	25	80010	80010	80010	492052	0	49	10292	13372	13372	3330	3	3349	80010	80020	80020	13372	39	1	1	80021	10	9	10	80010	10	0	5020	2	19	2	2	13369	80000	80010	13373	13373	13373	13373	13373
80024	13372	100	0	0	0	36	25	80010	80010	80010	492052	0	49	10292	13372	13372	3330	3	3349	80010	80020	80020	13372	39	1	1	80021	10	9	10	80010	10	0	5020	2	19	2	2	13369	80000	80010	13373	13373	13373	13373	13373
80024	13372	100	0	0	0	36	25	80010	80010	80010	492052	0	49	10292	13372	13372	3330	3	3349	80010	80020	80020	13372	39	1	1	80021	10	9	10	80010	10	0	5020	2	19	2	2	13369	80000	80010	13373	13373	13378	13373	13373
80024	13372	100	0	12	0	36	25	80010	80010	80010	492052	0	49	10292	13372	13372	3330	3	3349	80010	80020	80020	13372	39	1	1	80021	10	9	10	80010	10	0	5020	2	19	2	2	13369	80000	80010	13373	13373	13373	13373	13373
80024	13372	100	0	0	0	36	25	80010	80010	80010	492052	0	49	10292	13372	13372	3330	3	3349	80010	80020	80020	13372	39	1	1	80021	10	9	10	80010	10	0	5020	3	19	2	2	13369	80000	80010	13373	13373	13373	13373	13373
80024	13372	100	0	0	0	36	25	80010	80010	80010	492052	0	49	10292	13372	13372	3330	3	3349	80010	80020	80020	13372	39	1	1	80021	10	9	10	80010	10	0	5020	2	19	2	2	13369	80000	80010	13373	13373	13373	13373	13373
80024	13372	100	0	0	0	36	25	80010	80010	80010	492052	0	49	10292	13372	13372	3330	3	3349	80010	80020	80020	13372	39	1	1	80021	10	9	10	80010	10	0	5020	2	19	2	2	13369	80000	80010	13373	13373	13373	13373	13373
80024	13372	100	0	0	0	36	25	80010	80010	80010	492052	0	49	10292	13372	13372	3330	3	3349	80010	80020	80020	13372	39	1	1	80021	10	9	10	80010	10	0	5020	2	19	2	2	13369	80000	80010	13373	13373	13373	13373	13373
80024	13372	100	0	15	0	36	25	80010	80010	80010	492052	0	49	10292	13372	13372	3330	3	3349	80010	80020	80020	13372	39	1	1	80021	10	9	10	80010	10	0	5020	2	19	2	2	13369	80000	80010	13373	13373	13373	13373	13373

MOVK (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations