Firestorm: MRS (CNTFRQ_EL0) measurements

Code:

  mrs x0, cntfrq_el0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	1e	3f	51	schedule uop (52)	schedule int uop (53)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	82	83	flush restart other nonspec (84)	85	inst all (8c)	91	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	8572	66	0	0	8559	26	1000	1000	49	5494	8572	8572	8191	3	8335	8571	1182	1	1	1001	0	49	3	73	1	110	1	1	8568	1000	1000	8573	8574	8575	8574	8574
1004	8585	66	0	0	8557	26	1000	1000	49	5494	8571	8574	8189	3	8335	8574	1181	1	1	1001	0	26	3	73	1	110	1	1	8568	1000	1000	8574	8573	8573	8572	8575
1004	8571	66	0	0	8557	26	1000	1000	49	5491	8571	8572	8191	3	8335	8574	1182	1	1	1001	0	5	0	73	1	110	1	1	8571	1000	1000	8572	8572	8574	8575	8574
1004	8571	66	0	0	8557	26	1000	1000	49	5494	8571	8571	8189	3	8337	8574	1183	1	1	1001	0	34	6	73	1	114	1	1	8568	1000	1000	8572	8575	8572	8573	8575
1004	8577	70	0	0	8557	26	1000	1000	49	5493	8574	8572	8190	3	8337	8572	1184	1	1	1001	0	0	0	73	1	110	1	1	8569	1000	1000	8574	8573	8573	8574	8573
1004	8573	66	0	0	8556	26	1000	1000	49	5493	8572	8572	8188	3	8335	8585	1183	1	1	1001	0	58	3	73	1	110	1	1	8568	1000	1000	8574	8572	8572	8575	8573
1004	8573	66	0	0	8556	26	1000	1000	49	5492	8573	8573	8190	3	8335	8571	1184	1	1	1001	0	0	0	73	1	110	1	1	8571	1000	1000	8574	8573	8575	8573	8573
1004	8573	67	0	0	8557	26	1000	1000	49	5491	8571	8573	8191	3	8337	8574	1184	1	1	1001	0	0	0	73	1	110	1	1	8571	1000	1000	8578	8575	8575	8573	8575
1004	8573	67	0	0	8557	26	1000	1000	49	5491	8571	8574	8190	3	8335	8573	1181	1	1	1001	0	1	0	73	1	110	1	1	8568	1000	1000	8573	8573	8575	8575	8573
1004	8571	66	0	0	8558	26	1000	1000	49	5494	8574	8572	8190	3	8336	8574	1181	1	1	1001	0	0	0	73	1	110	1	1	8569	1000	1000	8575	8572	8575	8572	8575

Count: 8

Code:

  mrs x0, cntfrq_el0
  mrs x1, cntfrq_el0
  mrs x2, cntfrq_el0
  mrs x3, cntfrq_el0
  mrs x4, cntfrq_el0
  mrs x5, cntfrq_el0
  mrs x6, cntfrq_el0
  mrs x7, cntfrq_el0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 8.5011

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? int retires (ef)	f5	f6	f7	f8	fd
80204	680088	5272	0	0	177	0	680076	26	80100	80100	100	500	0	49	677006	680081	680086	669815	3	669952	100	200	200	680090	1183	1	1	80201	100	99	100	100	100	0	0	1	0	0	0	0	0	5110	2	94	2	2	680083	80000	0	0	80100	680143	680091	680085	680098	680091
80204	680115	5272	0	0	0	0	680408	26	80100	80100	100	500	0	49	677000	680079	680082	669809	3	669958	100	200	200	680083	1183	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	0	5110	2	106	2	2	680085	80000	0	0	80100	680073	680087	680088	680083	680085
80204	680079	5271	0	0	0	0	680073	26	80100	80100	100	500	0	49	677003	680107	680088	669805	3	669951	100	200	200	680072	1181	1	1	80201	100	99	100	100	100	0	0	0	36	0	0	0	0	5110	2	98	2	2	680083	80000	0	0	80100	680080	680084	680088	680099	680086
80204	680447	5271	0	0	0	0	680069	26	80100	80100	100	500	0	49	677012	680082	680084	669818	3	669952	100	200	200	680095	1183	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	0	5110	2	106	2	2	680083	80000	0	0	80100	680103	680085	680074	680090	680084
80204	680088	5272	0	0	0	0	680068	26	80100	80100	100	500	0	49	674336	680072	680084	669819	3	669954	100	200	200	680087	1181	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	0	5110	2	98	2	2	680087	80000	0	0	80100	680078	680089	680084	680084	680075
80204	680081	5271	0	0	0	0	680069	26	80100	80100	100	500	1	49	677005	680087	680089	669810	3	669997	100	200	200	680083	1182	1	1	80201	100	99	100	100	100	0	0	0	39	0	0	0	0	5110	2	102	2	2	680072	80000	0	0	80100	680087	680085	680086	680082	680094
80205	680083	5272	4	0	0	0	680068	26	80100	80100	117	620	0	49	677000	680090	680083	669814	3	669965	100	200	200	680098	1182	1	1	80201	100	99	100	100	100	0	0	1	1854	0	0	0	0	5110	2	94	2	2	680084	80000	0	0	80100	680209	680119	680480	680090	680090
80204	680088	5272	0	0	0	0	680065	26	80100	80100	100	500	0	49	679347	680084	680089	669808	3	669956	100	200	200	680088	1181	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	0	5110	2	102	2	2	680084	80000	0	0	80100	680085	680084	680509	680090	680084
80204	680081	5095	0	0	0	0	680070	26	80100	80100	100	500	0	98	677006	680088	680084	669813	3	669953	100	200	200	680087	1182	2	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	0	5110	2	110	2	2	680077	80000	0	0	80100	680088	680073	680084	680087	680072
80204	680095	5094	0	0	6	0	680462	26	80100	80100	100	500	0	49	676993	680451	680431	669815	3	669960	100	200	200	680086	1181	1	1	80201	100	99	100	100	100	0	0	1	0	0	0	0	0	5110	2	106	2	0	680076	80000	0	0	80100	680091	680091	680087	680081	680081

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 8.5011

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	680096	5272	0	0	0	0	0	189	0	0	680435	26	80044	80010	10	50	0	0	49	676993	0	680501	680110	669843	3	670371	10	20	20	680096	1182	2	1	80021	10	9	10	10	0	10	3	0	3	0	3	0	0	0	0	5020	0	3	102	0	0	0	5	8	680070	80040	80010	680100	680093	680102	680199	680107
80024	680512	5273	0	0	1	0	1	0	88	0	680078	128	80010	80010	10	68	0	0	49	677390	0	680099	680146	669838	7	669988	11	20	20	680107	1181	1	1	80021	10	9	10	10	0	10	0	0	3	0	9	0	0	0	0	5033	0	4	118	0	0	0	4	5	680445	80000	80010	680106	680102	680096	680098	680139
80024	680468	5271	0	0	0	0	0	12	0	0	680090	127	80010	80010	10	62	0	0	49	677011	0	680462	680104	669842	3	669985	10	20	20	680485	1182	1	1	80021	10	9	10	10	0	10	0	1	0	0	24	0	0	0	0	5020	0	4	110	0	0	0	4	3	680093	80038	80010	680099	680106	680567	680098	680104
80024	680095	5272	0	0	0	0	0	12	0	0	680094	127	80048	80010	11	50	0	0	49	677020	0	680100	680096	669826	3	669994	10	20	20	680089	2364	1	1	80021	10	9	10	10	0	10	0	0	0	0	0	0	0	0	0	5020	0	5	110	0	0	0	8	4	680126	80000	80010	680100	680098	680486	680097	680102
80024	680091	5272	0	0	0	0	0	0	0	0	680083	26	80042	80010	10	50	0	1	49	677024	0	680102	680101	669835	3	669983	10	20	20	680106	1181	1	1	80021	10	9	10	10	0	10	0	0	0	0	0	0	0	0	0	5020	0	3	94	0	0	0	3	5	680096	80000	80010	680097	680103	680102	680097	680133
80024	680095	5272	0	0	0	0	0	0	0	0	680084	26	80010	80010	10	50	0	1	49	677022	0	680106	680102	669838	3	669985	10	20	20	680100	1183	1	1	80021	10	9	10	10	0	10	0	0	0	0	0	0	0	0	1	5020	0	3	94	0	0	0	3	4	681952	80000	80010	680099	680102	680152	680102	680096
80024	680096	5272	1	0	0	0	0	12	0	0	681766	26	80045	80010	10	50	0	1	49	674324	0	680098	680096	669834	3	669987	10	20	20	680486	1183	1	1	80021	10	9	10	10	0	10	0	0	0	0	0	0	0	0	0	5020	0	5	110	0	0	0	5	5	680088	80000	80010	680161	681078	680153	680104	680141
82591	680094	5141	0	0	0	0	0	891	0	0	680058	26	80010	80010	12	68	0	1	49	677458	0	680455	680486	669908	7	669974	12	20	22	723395	1181	51	1	80021	10	9	10	10	0	10	0	0	0	0	0	0	0	0	0	5020	0	3	102	8	0	0	5	5	680076	80000	80010	680085	680085	680087	680090	680076
80025	680085	5094	0	0	0	0	0	15	0	0	680067	26	80107	80010	10	50	0	1	49	677004	0	680084	680496	669993	3	669982	10	20	20	680074	1182	1	1	80021	10	9	10	10	0	10	0	0	0	0	0	0	0	0	0	5020	0	4	110	0	0	0	5	4	680435	80000	80010	680072	680083	680087	680085	680084
80024	680439	5094	0	0	0	0	0	0	0	0	680072	26	80010	80010	10	50	0	0	49	677010	0	680076	680076	669834	3	669983	10	20	20	680083	1182	1	1	80021	10	9	10	10	0	10	0	0	3	0	0	0	0	0	0	5020	0	3	102	0	0	0	4	3	680083	80000	80010	680080	680072	680079	680085	680092

MRS (CNTFRQ_EL0)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations