Firestorm: CMN (sxtw, 32-bit) measurements

Code:

  cmn w0, w1, sxtw

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	f5	f6	f7	f8	fd
1004	369	2	0	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	2	0	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	27	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	2	0	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	6	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	73	1	18	1	1	366	1000	370	370	370	370	370

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmn w0, w1, sxtw
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	6	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	1	6	0	1310	1	2	28	3	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	191	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	3	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	711	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	801	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	679	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	935	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	13	27	13	6	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	210	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	11	27	12	10	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	292	19918	32	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	14	27	13	13	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	10	27	13	6	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30156	20035	104	1	1	20021	10	9	10	20010	10010	1	0	1270	12	27	13	13	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	231	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	12	27	13	13	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	12	27	13	13	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	1063	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	13	27	13	12	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	214	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	13	27	14	14	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	5	27	11	13	20042	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmn w0, w1, sxtw
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	30	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	6	17487	20112	20224	30236	20035	104	1	1	20201	100	99	100	20100	10100	0	1	1	1	1318	0	1	16	1	1	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	12	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	321	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	411	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	3	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	726	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	3	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	3	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	24	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	0	0	0	170	19918	25	20010	20010	20010	1297875	1	49	17000	0	20081	20079	17437	3	17528	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	840	1287	0	1	27	1	1	19995	20022	10010	20080	20081	20082	20036	20036
20024	20035	150	0	0	1	1	0	132	132	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	1	3	1270	0	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	0	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	252	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	1	3	1270	0	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	211	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	0	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	7	17504	20093	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	0	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	149	0	0	0	0	0	0	257	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	1	3	1270	0	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	1	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	1	0	0	1270	0	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	13	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	1270	0	1	27	1	1	19995	20000	10010	20036	20036	20036	20067	20036
20024	20035	150	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	1	0	1270	0	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  cmn w0, w1, sxtw
  cmn w0, w1, sxtw
  cmn w0, w1, sxtw
  cmn w0, w1, sxtw
  cmn w0, w1, sxtw
  cmn w0, w1, sxtw
  cmn w0, w1, sxtw
  cmn w0, w1, sxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0f	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26770	200	0	0	0	0	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	54	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	12	0	700	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	2	0	390	0	700	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	700	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	100	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	201	0	0	0	0	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	201	0	1	0	0	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	26722	200	0	0	0	0	0	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5022	11	34	0	10	8	26701	80000	0	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	0	0	0	700	25	80010	80010	80010	400050	0	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5022	7	18	0	10	10	26701	80000	0	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	0	0	0	56	25	80010	80010	80010	400050	0	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5030	10	18	0	7	10	26701	80391	0	0	10	26934	26983	26978	27026	27028
80024	26797	202	4	0	0	0	6	7	924	616	1179	177	80399	80459	80080	405554	1	49	23945	0	27029	26796	16744	27	16887	80412	80493	160986	26977	66	8	1	80021	10	9	10	80010	10	0	0	2	1	4	3180	0	0	5134	11	59	0	8	16	26910	80451	0	0	10	27025	27026	27027	26983	27027
80024	27030	201	2	1	0	0	6	7	804	704	656	170	80396	80459	80213	408899	1	49	23948	0	26842	26980	16738	35	16888	80145	80422	160850	27022	66	8	1	80021	10	9	10	80010	10	4	2	0	1	0	3471	2	0	5121	20	67	0	10	8	26943	80454	0	0	10	26980	27027	26981	27029	27027
80024	26984	202	0	0	1	1	6	7	924	666	1237	173	80462	80464	80416	402883	0	49	23944	0	27119	26979	16767	40	16918	80212	80634	161104	27116	66	9	1	80021	10	9	10	80010	10	2	0	2	0	2	4120	0	0	5156	19	83	0	10	14	27013	80582	0	0	10	27069	26841	27115	27074	26891
80024	26982	202	0	1	1	0	6	2	411	616	1460	110	80395	80207	80347	405578	0	49	23945	0	26983	26845	16734	28	16828	80078	80426	160296	26978	66	1	1	80021	10	9	10	80010	10	0	2	3	0	4	2750	2	0	5030	9	18	2	12	9	26701	80000	0	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5030	9	18	0	12	12	26701	80000	0	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5030	12	18	0	12	9	26701	80000	0	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	0	12	0	0	5030	9	18	0	9	12	26701	80000	0	0	10	26706	26706	26706	26706	26706

CMN (sxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations