Firestorm: LDRSH (post-index, 64-bit) measurements

Code:

  ldrsh x0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1058	8	1	0	0	0	0	54	21	1	0	3	0	1025	10	4	12	9	19	25	2000	1000	1000	1000	1000	52844	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1018	0	0	48	1020	0	0	0	10	17	1023	39	2	28	56	0	10	0	73	2	16	2	2	1037	1000	18	18	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	1	0	58	20	0	0	6	4	1025	0	3	10	11	14	25	2000	1000	1000	1000	1000	52828	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1007	8	1	68	1035	19	0	17	6	24	1030	44	4	22	48	7	1	0	73	2	16	2	2	1037	1000	28	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	0	0	0	51	14	1	0	5	8	1025	17	2	6	5	13	25	2000	1000	1000	1000	1000	52836	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1021	7	2	82	1040	8	0	11	0	27	1016	28	4	21	40	7	30	6	73	2	16	2	2	1037	1000	21	25	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	0	0	0	67	14	1	0	4	4	1025	9	2	8	7	16	25	2000	1000	1000	1000	1000	52836	45825	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	2	1027	8	2	42	1041	4	0	21	6	22	1030	36	3	23	32	7	1	0	73	3	16	2	2	1037	1000	23	25	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	0	60	14	1	0	3	0	1025	10	3	6	3	16	25	2000	1000	1000	1000	1000	52836	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1023	7	2	41	1044	3	1	40	6	20	1035	34	2	19	64	6	1	4	73	2	16	2	2	1037	1000	21	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	2	1	0	41	14	1	0	5	0	1025	11	2	8	3	19	25	2000	1000	1000	1000	1000	52832	45825	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1021	8	0	32	1036	15	0	14	6	26	1024	35	5	22	40	7	1	0	73	2	16	2	2	1037	1000	21	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	1	0	0	50	0	0	0	5	0	1025	0	5	7	7	20	25	2000	1000	1000	1000	1000	52836	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1043	7	0	41	1035	3	0	14	20	16	1024	39	4	26	48	7	1	0	73	2	16	2	2	1037	1000	21	25	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	1	1	0	0	58	14	1	0	5	0	1025	17	3	9	7	13	25	2000	1000	1000	1000	1000	52844	45825	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1008	6	0	33	1059	3	5	20	0	22	1016	33	3	22	40	6	3	0	73	2	16	2	2	1037	1000	21	19	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	0	56	16	1	0	4	0	1025	11	4	5	6	15	25	2000	1000	1000	1000	1000	52820	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1028	8	0	48	1027	3	2	32	6	22	1029	29	4	29	40	7	0	0	73	2	16	2	2	1037	1000	21	21	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	0	49	20	1	0	6	0	1025	15	3	7	14	13	25	2000	1000	1000	1000	1000	52832	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	46	1	1	1001	1000	1000	0	1019	8	2	65	1028	2	0	31	12	29	1034	36	4	23	40	7	1	0	73	2	16	3	3	1037	1000	21	21	1000	1000	1041	1041	1041	1049	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1873

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72071	539	4	0	0	0	0	0	0	0	415	0	811	1	704	5	272	71986	781	4	0	71672	25	50770	40644	10146	40100	10000	615055	2727915	0	49	68893	71936	71998	65299	0	3	65506	50100	40200	10000	70200	10000	71956	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10896	12	148	485	10655	291	11	909	128	39	10906	147	8	133	4	3	8	2610	3	58	2	2	71903	40520	898	892	899	10000	40100	71877	71768	71943	71963	71843
50204	71998	539	4	0	0	0	0	0	0	0	475	0	790	1	688	6	144	71805	791	3	3	71493	25	50795	40632	10135	40100	10000	613857	2713943	0	49	68720	71842	71891	65401	0	3	65465	50100	40200	10000	70200	10000	71929	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10885	4	150	480	10660	262	12	901	72	32	10908	115	8	130	3	0	3	2610	2	58	2	2	71710	40500	1019	1076	1005	10000	40100	71979	71750	71969	72006	71717
50204	71824	537	3	0	0	0	0	0	0	0	483	0	768	1	736	3	100	71932	769	4	1	71724	25	50765	40660	10119	40100	10000	614335	2715780	0	98	68926	71913	72013	65518	0	3	65695	50100	40200	10000	70200	10000	71924	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10934	4	151	508	10635	289	10	930	44	38	10877	128	6	122	1	3	7	2610	2	58	2	2	71706	40512	954	930	1077	10000	40100	71732	71958	71756	71893	71811
50204	72092	536	2	0	1	0	0	0	0	0	501	0	822	1	720	3	112	71844	792	4	3	71469	25	50725	40560	10127	40100	10000	614701	2724688	0	49	68810	71914	71791	65207	0	3	65594	50100	40200	10000	70200	10000	71975	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10894	2	162	515	10642	265	12	944	48	45	10891	126	9	124	2	0	9	2610	2	58	2	2	71678	40560	958	1074	1011	10000	40100	71743	71892	71886	72003	71922
50204	71719	539	2	0	0	0	0	0	0	0	397	0	846	1	632	3	224	71879	788	2	1	71846	25	50740	40632	10133	40100	10000	614837	2722868	0	49	68732	71870	71997	65268	0	3	65463	50100	40391	10000	70200	10000	72095	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10936	6	167	467	10649	268	10	883	72	31	10903	120	8	117	3	3	9	2610	2	58	2	2	71501	40488	916	1080	1039	10000	40100	71750	71852	71692	71676	71912
50204	71816	539	3	0	0	0	3	0	0	0	471	0	842	1	688	1	100	71861	793	2	3	71429	25	50705	40572	10146	40261	10000	614674	2720768	0	49	68947	71942	71796	65406	0	3	65469	50100	40200	10000	70200	10000	71739	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10893	4	151	484	10644	272	12	906	68	35	10917	125	7	107	2	0	6	2610	2	17	2	2	71766	40508	1057	1010	995	10000	40100	71776	72176	71995	71975	72025
50204	71923	539	3	0	2	0	0	0	0	0	473	0	788	1	680	3	116	71843	789	4	2	71454	25	50765	40576	10137	40100	10000	615693	2725615	0	49	68607	71984	71473	65099	0	3	65683	50100	40200	10000	70200	10000	71660	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10913	3	166	514	10603	276	11	920	68	37	10935	128	5	138	2	2	3	2610	2	58	2	2	71701	40468	1034	988	1069	10000	40100	71768	72061	72014	71719	71921
50204	71875	538	2	0	0	0	1	0	0	0	522	0	826	2	696	2	120	71699	785	1	3	71657	25	50765	40624	10120	40100	10000	614088	2719523	0	49	68588	72017	71844	65373	0	3	65599	50100	40200	10000	70200	10000	71889	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10931	10	153	486	10636	281	12	952	78	35	10964	126	5	121	2	3	3	2610	2	58	2	2	71365	40504	919	940	958	10000	40100	71692	71948	71697	72006	71733
50204	71996	539	2	0	0	0	0	0	0	0	523	0	819	1	688	2	116	72011	811	2	2	71477	25	50765	40572	10128	40100	10000	612709	2717193	0	49	68750	71710	71892	65109	0	3	65566	50100	40200	10000	70200	10000	71872	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10912	3	142	481	10639	279	13	901	80	31	10938	127	6	128	2	0	9	2610	2	58	2	2	71614	40468	933	1083	984	10000	40100	71951	71998	71876	71709	71683
50204	71547	537	2	0	2	0	0	0	0	0	459	0	829	1	656	3	128	71912	793	4	3	71679	25	50680	40544	10125	40100	10000	613048	2718284	0	49	68837	71909	71819	65246	0	3	65713	50100	40200	10000	70200	10000	71658	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10879	3	161	523	10653	266	14	928	48	25	10929	133	5	120	1	0	3	2610	2	58	2	2	71452	40500	997	975	976	10000	40100	71795	71843	71677	71853	71838

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1758

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	24	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c3	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	71735	537	0	0	0	0	0	0	617	0	822	1	0	720	0	152	71751	799	4	2	71584	25	50705	40494	10135	40010	10000	629831	2714998	1	49	68505	71870	71825	65134	0	3	65468	50010	40020	10000	70020	10000	71817	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10916	0	154	481	10683	283	14	925	78	43	10918	145	6	130	0	5	0	2520	0	7	65	3	3	71769	40536	938	938	944	10000	40010	71870	71848	71627	71871	72034
50024	71787	538	0	0	0	0	0	0	563	0	801	1	0	744	6	92	71849	786	5	2	71552	25	50650	40569	10127	40010	10000	631759	2719608	0	49	68796	71768	71915	65178	0	3	65518	50010	40020	10000	70377	10000	71712	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10883	0	163	494	10624	260	13	879	82	43	10908	126	6	130	0	5	0	2520	0	2	65	2	2	71712	40528	866	1006	904	10000	40010	71822	71854	71835	71852	72042
50024	71715	537	0	0	0	0	0	0	555	0	813	1	0	704	1	100	71942	750	4	1	71495	25	50645	40538	10134	40010	10000	630108	2718318	0	49	68680	71593	71774	65202	0	3	65544	50010	40020	10000	70020	10000	71848	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10862	0	162	490	10700	256	11	870	34	41	10970	127	4	122	0	5	0	2520	0	2	65	2	2	71550	40548	968	978	938	10000	40010	71680	71765	71724	71675	71888
50024	71763	537	0	0	0	0	0	0	577	0	806	1	0	712	0	100	71776	788	5	1	71470	25	50690	40522	10136	40010	10000	629324	2716659	0	49	68689	71826	71812	65317	0	3	65612	50010	40020	10000	70020	10000	71880	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10886	0	138	509	10623	268	9	891	80	35	10879	133	3	127	0	2	0	2520	0	3	65	2	2	71572	40512	950	954	932	10000	40010	71900	71817	71798	71836	71838
50024	71710	539	0	0	0	1	0	0	590	0	815	1	0	688	1	148	71723	775	5	2	71489	25	50685	40490	10130	40010	10000	630575	2716803	0	49	68600	71884	71647	65234	0	3	65494	50010	40020	10000	70020	10000	71837	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10892	0	149	473	10639	261	11	902	78	35	10889	122	5	130	0	6	0	2520	0	2	65	2	2	71459	40520	934	938	1026	10000	40010	71805	71629	71810	71811	71863
50024	71702	538	0	0	0	0	0	0	553	0	825	1	0	736	0	108	71714	764	4	3	71442	25	50625	40530	10128	40010	10000	630955	2720668	0	49	68697	71872	71866	65026	0	3	65411	50010	40020	10000	70020	10000	71550	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10895	0	152	506	10636	257	11	867	86	40	10936	118	4	129	0	3	1	2520	0	2	65	2	3	71602	40544	956	884	982	10000	40010	71671	71716	71693	71609	71731
50024	71616	537	0	0	0	1	0	0	570	0	807	1	0	768	0	108	71750	806	4	0	71510	25	50685	40522	10123	40010	10000	631069	2714550	0	49	68610	71834	71729	65140	0	3	65267	50010	40020	10000	70020	10000	71597	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10930	0	165	534	10624	267	14	904	38	45	10898	132	4	131	0	3	0	2520	0	2	65	3	3	71743	40532	956	844	916	10000	40010	71710	71904	71790	71898	71842
50024	71744	538	0	0	0	1	0	0	614	0	826	1	0	760	0	152	71827	762	3	3	71449	25	50660	40510	10120	40010	10000	629615	2721647	0	49	68672	71583	71724	65258	0	3	65390	50010	40020	10000	70020	10000	71542	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10930	0	147	498	10636	244	12	880	80	40	10885	120	5	117	0	4	0	2520	0	3	65	2	2	71624	40532	920	886	832	10000	40010	71887	71559	71839	71715	71623
50024	71697	537	0	0	0	0	0	0	508	0	828	1	0	712	0	104	71670	778	4	0	71473	25	50630	40498	10131	40010	10000	629803	2713816	0	49	68507	71838	71598	65372	0	3	65615	50010	40020	10000	70020	10000	71792	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10873	0	136	497	10638	273	14	893	78	40	10958	122	3	125	0	3	0	2520	0	2	65	3	3	71649	40548	906	904	958	10000	40010	71811	71773	71823	71835	71828
50024	71768	537	0	0	0	0	0	0	609	0	799	1	0	688	1	116	71726	784	14	2	71394	25	50640	40510	10130	40010	10000	629677	2719314	0	49	68755	72004	71781	65405	0	3	65407	50010	40020	10000	70020	10000	71763	62	1	1	40021	10	9	10	10000	30010	10000	0	10	10929	0	156	516	10680	259	12	903	80	49	10900	134	4	119	0	9	0	2520	0	2	65	4	3	71658	40580	988	958	844	10000	40010	71839	71745	71815	71894	71803

Test 3: throughput

Count: 8

Code:

  ldrsh x0, [x6], #8
  ldrsh x0, [x7], #8
  ldrsh x0, [x8], #8
  ldrsh x0, [x9], #8
  ldrsh x0, [x10], #8
  ldrsh x0, [x11], #8
  ldrsh x0, [x12], #8
  ldrsh x0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3653

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29612	221	1	0	0	1	0	0	6796	799	1	688	103	220	29415	787	415	2091	2354	1947	25	160176	80168	80000	80120	80017	400835	1274509	1	47	49	26151	29241	29106	9198	0	6	9124	160134	80220	80020	80224	80020	29143	35	1	1	80201	100	99	22	100	80000	100	80000	0	100	80891	36	394	5692	0	85637	695	9	840	50	5162	86457	691	125	5456	5322	50	9	18	1	1	1	5117	1	16	1	1	29230	25	80079	370	350	87	80000	80100	29141	29173	29197	29193	29255
160204	29284	219	3	0	3	1	0	0	6249	762	1	656	94	132	29228	826	456	1957	1867	1979	25	160161	80166	80000	80116	80014	400905	1293791	1	59	49	26083	29496	29045	9313	0	6	8975	160135	80220	80020	80224	80020	29461	35	1	1	80201	100	99	8	100	80000	100	80000	1	100	80934	67	390	5370	0	85702	713	9	863	38	4828	86155	695	107	5156	5564	71	3	8	1	1	1	5117	1	16	1	1	29364	29	80084	323	310	79	80000	80100	29174	29091	29044	29126	29382
160204	29406	219	4	0	0	0	0	0	6795	794	1	680	99	96	29206	752	429	2050	1925	1800	25	160174	80169	80000	80124	80012	400882	1288570	1	50	49	26082	29128	29335	9156	0	6	9048	160133	80220	80020	80228	80020	29244	35	1	1	80201	100	99	11	100	80000	100	80000	0	100	80952	53	405	4930	0	85563	707	8	890	38	4700	86099	768	132	5239	5104	69	0	4	1	1	1	5117	1	16	1	1	29302	31	80074	296	364	74	80000	80100	29213	28927	29149	29223	29369
160204	29392	219	4	0	0	0	0	0	7190	795	1	712	92	148	29386	780	493	2030	2025	1862	25	160168	80173	80000	80120	80015	400859	1296510	0	57	49	26235	28919	29196	9104	0	23	9560	160125	80220	80020	80224	80020	29291	35	1	1	80201	100	99	18	100	80000	100	80000	0	100	80919	51	358	5459	28	86359	714	12	881	38	5027	85878	708	133	5519	5165	49	3	0	1	1	1	5117	1	16	1	1	29245	20	80067	389	354	79	80000	80100	29216	29492	29211	29245	29032
160204	29013	218	3	0	0	0	0	0	7147	806	1	680	94	100	29038	788	443	2101	2041	2005	25	160185	80181	80000	80120	80020	400860	1282944	1	65	49	26081	29226	28954	9237	0	3	9192	160100	80200	80000	80200	80000	29228	35	1	1	80201	100	99	16	100	80000	100	80000	0	100	80947	68	415	5498	0	85373	710	15	874	28	5793	85786	728	131	4843	5382	51	3	3	0	0	0	5110	2	16	2	2	29414	36	80052	339	364	92	80000	80100	29227	29258	29171	29260	29213
160204	29258	221	3	0	3	0	0	0	7095	780	1	688	116	116	29423	773	483	2026	2069	2129	25	160164	80155	80000	80100	80000	400806	1299618	0	66	49	26060	29312	29229	9118	0	3	9083	160100	80200	80000	80200	80000	29523	35	1	1	80201	100	99	16	100	80000	100	80000	0	100	80891	69	341	6178	0	85535	667	13	863	38	4950	85948	794	133	5381	5374	65	11	5	0	0	0	5110	2	16	2	2	29155	38	80060	318	386	66	80000	80100	29392	29468	29216	29323	29326
160204	29487	218	4	0	4	0	0	0	7234	778	1	672	99	116	29412	783	403	2189	2049	1806	25	160156	80145	80000	80100	80000	400766	1286384	1	50	49	26229	29123	29201	9179	0	3	8935	160100	80200	80000	80200	80000	29326	35	1	1	80201	100	99	11	100	80000	100	80000	0	100	80890	58	387	5585	0	84912	701	11	890	42	5605	86164	771	132	5556	5412	51	3	3	0	0	0	5110	2	16	2	2	29055	27	80061	407	308	104	80000	80100	29057	29115	29053	29076	29195
160204	29142	217	3	3	0	0	0	0	6708	787	1	664	85	132	29343	801	503	2211	2098	1949	25	160165	80163	80000	80100	80000	400753	1292855	1	88	49	26035	29119	29542	9199	0	3	9064	160100	80200	80000	80200	80000	29449	35	1	1	80201	100	99	13	100	80000	100	80000	0	100	80965	75	390	5678	0	85548	758	15	894	48	5519	86284	833	124	5453	4858	55	0	4	0	0	0	5110	2	17	2	2	29141	30	80051	399	369	95	80000	80100	29230	29371	29045	29135	29252
160204	29552	220	3	0	0	0	0	0	7333	815	1	712	86	136	29269	772	497	2003	1938	2116	25	160163	80163	80000	80100	80000	400762	1291719	0	64	49	26173	29520	29365	9450	0	3	9232	160100	80200	80000	80200	80000	29197	35	1	1	80201	100	99	15	100	80000	100	80000	0	100	80924	64	365	5561	0	85526	680	10	881	102	5142	86400	701	129	4828	5392	69	3	6	0	0	0	5110	2	16	2	2	29070	26	80064	349	356	95	80000	80100	29166	29348	29404	29364	29317
160204	28935	220	3	0	0	0	0	0	6237	781	1	696	83	128	29036	819	495	1938	2014	1951	25	160154	80167	80000	80100	80000	400787	1292946	0	56	49	26092	29198	29505	8937	0	3	9104	160100	80200	80000	80200	80000	29397	35	1	1	80201	100	99	13	100	80000	100	80000	0	100	80943	43	427	5149	0	84840	744	12	910	68	5409	86502	697	127	4904	5386	67	0	0	0	0	0	5110	2	17	2	2	29137	29	80055	393	326	89	80000	80100	29437	29254	29444	29527	29191

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d0	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29734	220	0	1	0	0	0	1	0	6809	789	1	696	99	112	29807	796	307	1872	1902	2051	25	160074	80084	80000	80010	80000	400299	1296081	0	57	49	26106	29631	29420	9288	0	3	9338	160010	80020	80000	80020	80000	29371	35	1	1	80021	10	9	30	10	80000	10	80000	0	10	80880	18	379	6016	85300	623	11	929	36	5437	86002	816	109	4861	5294	17	1	5	5020	16	25	16	0	0	9	7	29406	34	80061	571	530	107	80000	80010	29509	29248	29524	29409	29323
160024	29465	220	0	1	0	0	0	0	0	6765	808	1	736	90	140	29203	811	309	1850	1825	2126	25	160086	80078	80000	80010	80000	400373	1301900	0	64	49	26247	29269	29238	9197	0	3	9289	160010	80020	80000	80020	80000	29138	35	1	1	80021	10	9	35	10	80000	10	80000	0	10	80913	18	374	5197	85201	702	12	898	30	5200	86052	753	122	4904	4597	18	0	4	5020	15	7	15	0	0	7	11	29373	20	80063	627	443	127	80000	80010	29420	29317	29298	29279	29266
160024	29423	221	0	1	0	0	0	0	0	7614	864	1	744	104	188	29423	795	329	1863	1712	2148	25	160078	80078	80000	80010	80000	400324	1308450	0	64	49	26452	29481	29445	9274	0	3	9410	160010	80020	80000	80020	80000	29583	35	1	1	80021	10	9	28	10	80000	10	80000	0	10	80986	17	372	6044	85470	650	11	919	76	5406	86472	812	123	5544	4626	16	6	4	5020	15	13	16	0	0	7	7	29210	29	80069	563	505	92	80000	80010	29344	29222	29357	29547	29239
160024	29377	220	0	1	0	1	0	0	0	6827	793	1	728	113	228	29361	771	350	2044	2036	2047	25	160064	80060	80000	80010	80000	400346	1290410	0	59	49	26227	29403	29216	9415	0	3	9560	160010	80020	80000	80020	80000	29587	35	1	1	80021	10	9	38	10	80000	10	80000	0	10	80894	19	390	5383	86113	654	12	872	80	5226	85951	743	131	5350	5266	16	0	7	5020	15	8	16	0	0	5	13	29371	20	80061	564	488	96	80000	80010	29367	29362	29160	29433	29268
160024	29391	219	0	1	1	0	0	0	0	7002	777	1	768	92	116	29278	789	306	1813	1919	2369	25	160068	80077	80000	80010	80000	400351	1303069	0	58	49	26346	29388	29460	9466	0	3	9481	160010	80020	80000	80020	80000	29457	35	1	1	80021	10	9	41	10	80000	10	80000	0	10	80948	20	441	6009	85278	695	14	853	34	5776	85892	753	139	5066	5018	18	0	7	5020	15	5	16	0	0	8	6	29234	29	80079	513	525	97	80000	80010	29217	29467	29436	29401	29302
160024	29143	219	0	1	0	0	0	0	0	6731	781	1	712	84	216	29258	790	307	1804	1814	2134	25	160072	80078	80000	80010	80000	400424	1287235	0	70	49	26146	29163	29567	9376	0	3	9497	160010	80020	80000	80020	80000	29250	35	1	1	80021	10	9	36	10	80000	10	80000	1	10	80920	18	444	5482	84971	696	10	881	74	5380	85709	712	132	4847	4249	17	0	4	5020	18	9	16	0	0	6	7	29256	35	80078	503	552	105	80000	80010	29446	29561	29473	29725	29607
160024	29631	221	0	1	1	0	0	0	0	6547	811	1	704	109	120	29356	816	325	1752	1961	1958	25	160075	80087	80130	80010	80000	400358	1293406	0	62	49	26370	29571	29295	9688	0	3	9423	160010	80020	80000	80020	80000	29254	35	1	1	80021	10	9	28	10	80000	10	80000	0	10	80891	18	367	5258	85108	650	13	865	24	5176	85785	765	139	4992	4752	15	6	5	5020	15	8	16	0	0	7	9	29451	26	80073	561	532	89	80000	80010	29323	29566	29247	29285	29210
160024	29412	220	0	1	0	0	0	0	0	6942	809	1	688	115	148	29343	803	314	1676	1792	2040	25	160076	80064	80000	80010	80000	400321	1298402	0	73	49	26318	29552	29359	9282	0	3	9625	160010	80020	80000	80020	80000	29427	35	1	1	80021	10	9	23	10	80000	10	80000	0	10	80950	18	379	6212	85050	620	11	882	30	5368	86042	774	131	5040	5358	18	3	8	5020	15	9	16	0	0	13	9	29429	24	80050	560	458	102	80000	80010	29408	29511	29399	29390	29289
160024	29512	220	1	1	0	0	0	0	0	7028	813	1	648	99	196	29607	798	338	1910	1852	2144	25	160067	80073	80000	80010	80000	400366	1288878	0	55	49	26161	29283	29324	9270	0	3	9422	160010	80020	80000	80020	80000	29233	35	1	1	80021	10	9	42	10	80000	10	80000	0	10	80926	18	386	5689	85508	656	12	904	72	4929	85552	715	124	4753	4587	18	1	3	5020	15	10	16	0	0	6	8	29324	24	80064	486	520	105	80000	80010	29369	29361	29566	29434	29340
160024	29404	221	0	1	0	0	0	0	1	7366	777	1	712	120	240	29353	791	341	1773	1787	2198	25	160087	80077	80000	80010	80000	400366	1300762	0	65	49	26367	29561	29249	9412	0	3	9291	160010	80020	80000	80020	80000	29502	35	3	1	80021	10	9	40	10	80000	10	80000	0	10	80922	18	402	5321	85402	629	12	866	48	5097	85686	793	128	5015	5341	18	0	3	5020	15	12	16	0	0	6	8	29218	24	80053	577	557	96	80000	80010	29290	29419	29367	29418	29362

LDRSH (post-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations